Hardware patch circuit applied to CPU integrated display card

Abstract

The utility model relates to a hardware patch circuit applied to a CPU (Central Processing Unit) integrated display card, which comprises a CPU provided with an SME (System Management Equipment) bus and a JTAG (Joint Test Action Group) bus; the hardware patch circuit further comprises an I / O expander and a logic control module. The hardware patch circuit applied to the CPU integrated display card is ingenious in design; in the startup process, a CPU (Central Processing Unit) converts JTAG (Joint Test Action Group) data through an SME bus conversion I / O (Input / Output) expander, reads set display related settings in the CPU for adaptation before a CPUTRST signal is activated, and finally outputs a group of fixed data and locks a JTAG signal after the CPUTRST signal is activated; signals input / output by the I / O expander are transmitted to the CPU through a JTAG bus to realize interactive matching; the logic control module completes enabling in the startup process of the computer through an ENABLE signal, and performs circuit initialization through an RST signal; according to the solution of the hardware level, the patch success rate is increased, and normal operation of a hardware patch circuit is ensured.

Description

TECHNICAL FIELD

[0001] The utility model relates to computer hardware technical field more specifically, relate to a kind of hardware patch circuit applied to CPU integrated graphic card. BACKGROUND

[0002] With X86 PC computer more and more mature, but domestic PC platform is in a long-term disadvantage compared with Intel / AMD, in the limitation of CPU using different nanometer technology and packaging level, there is bottleneck in the integration of some functional modules, and it cannot be broken through, currently domestic CPU has bottleneck in integrated graphic card technology, especially when integrating graphic card function into CPU, often cannot display or crash phenomenon appears;

[0003] Prior art usually relies on software patch dynamic repair after starting, but software driver patch cannot solve hardware level initialization failure problem, which can lead to random display failure or crash phenomenon of kernel display, has high risk, cannot guarantee that integrated graphic card can be normally initialized every time starting;When software patch cannot solve the problem, integrated graphic card can only be abandoned, and independent graphic card is used instead, but it will increase hardware cost and system complexity, which is not conducive to market promotion. UTILITY MODEL CONTENT

[0004] The utility model solves the technical problems, and provides a hardware patch circuit applied to CPU integrated graphic card to solve the low success rate of integrating graphic card function into CPU and the potential risk in the prior art.

[0005] The technical scheme adopted by the utility model to solve its technical problems is: a hardware patch circuit applied to CPU integrated graphic card, including CPU, and SME bus and JTAG bus are arranged on the CPU;Wherein, the hardware patch circuit further includes I / O expander and logic control module;The CPU converts I / O expander conversion JTAG signal data through SME bus, reads the internal integrated graphic card related setting of CPU before CPUTRST signal activation and adapts, finally after CPUTRST signal activation, a group of fixed data is output to lock JTAG signal;The signal input / output of I / O expander is transmitted to the CPU through JTAG bus;The logic control module is enabled in the process of computer starting through ENABLE signal, and circuit initialization is carried out through RST signal.

[0006] The hardware patch circuit, wherein the hardware patch circuit further includes level converter;The level converter converts the JTAG signal output by the I / O expander into the level signal required by the JTAG bus.

[0007] The hardware patch circuit, wherein the level signal is less than the JTAG signal.

[0008] The hardware patch circuit, wherein the CPU is further provided with a BIOS; and the BIOS is provided with a patch code.

[0009] The hardware patch circuit, wherein the chip model of the I / O expander is PCA9557.

[0010] The hardware patch circuit, wherein the chip model of the level converter is RS0104YT, and the level converter supports voltage conversion between 1.65V-5.5V on the A side and 2.3V-5.5V on the B side.

[0011] The hardware patch circuit, wherein the logic control module resets the circuit system through an RST signal and enables an ENABLE signal in the early stage of starting, so as to trigger the patch code to be automatically injected in the BIOS initialization stage and repair the graphic configuration error.

[0012] The hardware patch circuit, wherein the JTAG signal output by the I / O expander is 3.3V; and the level signal output by the level converter after conversion is 1.8V.

[0013] The hardware patch circuit applied to the CPU integrated graphic card has the advantages that: in the starting process, the CPU converts the JTAG data through the SME bus and the I / O expander, reads the internal integrated graphic related settings before the CPU T RST signal is activated, and finally outputs a group of fixed data after the CPU T RST signal is activated, so as to lock the JTAG signal; the signals input / output by the I / O expander are transmitted to the CPU through the JTAG bus, so as to realize interactive matching; the logic control module is enabled in the starting process of the computer through the ENABLE signal, and is initialized through the RST signal, so as to ensure the normal operation of the hardware patch circuit. Through the above process, the hardware patch circuit can automatically complete the patch of the integrated graphic card in the starting process, ensure the normal initialization and display of the integrated graphic card, and solve the problems of display failure and system crash; the hardware patch circuit avoids the instability of the software patch, improves the success rate of the patch through the hardware-level solution, has low cost, improves the stability and reliability of the integrated graphic card, helps to enhance the confidence of consumers in the domestic CPU, and promotes market promotion. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the present application will be further described below with reference to the drawings and embodiments. The drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the premise that they do not pay creative labor.

[0015] Figure 1 is a schematic diagram of a hardware patch circuit applied to a CPU integrated display card according to a preferred embodiment of the present application;

[0016] Figure 2 is a circuit diagram of a hardware patch circuit according to a preferred embodiment of the present application;

[0017] Figure 3 is a circuit diagram of a level converter according to a preferred embodiment of the present application;

[0018] Figure 4 is a circuit diagram of an I / O expander according to a preferred embodiment of the present application;

[0019] Figure 5 is a control circuit diagram of a logic control module according to a preferred embodiment of the present application. DETAILED DESCRIPTION

[0020] The terms "first", "second", "third", and "fourth" and the like in the description and claims of the present application and the drawings hereto are used for distinguishing between similar objects, not necessarily described in a particular order. Also, the terms "comprises", "comprising", "includes", "including" and the like are to be construed open-ended, allowing for instances where there are equivalents. For example, a process, method, article, or apparatus that comprises a list of steps or elements is not necessarily limited to the listed steps or elements, but can include additional steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0021] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It is expressly understood that any of the embodiments described herein can be combined with any of the other embodiments unless specifically noted otherwise.

[0022] "Multiple" means two or more. "And / or", describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0023] Moreover, the terms "upper, lower, front, rear, left, right, upper end, lower end, longitudinal direction" and the like indicating the orientation are all with reference to the attitude position of the device or equipment described in the present scheme in the normal use.

[0024] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0025] The hardware patch circuit applied to the CPU integrated display card of the preferred embodiment of the present application, as shown in Figures 1-5 The hardware patch circuit further comprises an I / O expander and a logic control module. The CPU converts the JTAG signal data through the SME bus conversion I / O expander. Before the CPU TRST signal is activated, the CPU internal integrated display related settings are read and adapted. Finally, after the CPU TRST signal is activated, a set of fixed data is output to lock the JTAG signal. The input / output signals of the I / O expander are transmitted to the CPU through the JTAG bus. The logic control module completes the enablement during the computer boot process through the ENABLE signal, and performs circuit initialization through the RST signal. The ENABLE signal and the RST signal line connected to the logic control module ensure correct enablement and initialization during the boot process.

[0026] It is worth noting that in the present embodiment, CPUTRST represents Test Reset, which is a control signal used to enter the CPU into test mode or reset the test logic circuit. When the CPUTRST signal is activated, the CPU will enter the test mode for hardware testing and fault diagnosis. The test equipment can place the CPU in test mode through the CPUTRST signal, and reset it after the test is completed, so that it returns to the normal working mode.

[0027] This hardware patching circuit for CPU integrated graphics is ingeniously designed. During boot, the CPU uses the SME bus to convert I / O expanders to JTAG data. Before the CPU TRST signal is activated, it reads the CPU's internal integrated graphics settings for adaptation. Finally, after the CPU TRST signal is activated, it outputs a set of fixed data to lock the JTAG signal. The input / output signals of the I / O expanders are transmitted to the CPU via the JTAG bus for interactive matching. The logic control module enables the computer during boot using the ENABLE signal and initializes the circuit using the RST signal, ensuring the normal operation of the hardware patching circuit. Through this process, the hardware patching circuit can automatically patch the integrated graphics card during boot, ensuring that the integrated graphics card can initialize and display normally, thus solving the problems of display failure and crashes. Moreover, this hardware patching circuit avoids the instability of software patches, improving the success rate of patching through a hardware-level solution. It is not only low-cost but also improves the stability and reliability of integrated graphics cards, which helps to enhance consumer confidence in domestic CPUs and promote market promotion.

[0028] Furthermore, to make the hardware patching circuit more compatible with CPUs and other components of different voltage standards, increasing the system's versatility and flexibility, the hardware patching circuit also includes a level converter. The level converter converts the JTAG signal output from the I / O expander into the level signal required by the JTAG bus, which not only helps reduce noise and distortion during signal transmission and improve signal integrity, but also provides stronger driving capability, enabling the signal to effectively drive the load on the JTAG bus.

[0029] Furthermore, the voltage level is lower than the JTAG signal. In this embodiment, the JTAG signal output by the I / O expander is 3.3V; the voltage level output by the level converter is 1.8V. This helps the hardware patch circuit better adapt to the low-voltage design trend of modern electronic devices, while also bringing benefits such as reduced power consumption, reduced heat generation, and improved reliability.

[0030] Furthermore, to ensure that hardware problems are automatically repaired or optimized before the operating system loads, a BIOS is also installed on the CPU. The BIOS contains patch code, which can ensure the correct configuration and operation of the hardware in the early stages of system startup, thereby improving the performance of the entire computer system and the user experience.

[0031] Furthermore, the I / O expander's chip model is PCA9557.

[0032] Furthermore, the level converter chip model is RS0104YT, which supports voltage conversion between side A (1.65V~5.5V) and side B (2.3V~5.5V).

[0033] Furthermore, the logic control module resets the circuit system via the RST signal and enables the ENABLE signal early in the boot process, triggering the automatic injection of patch code during the BIOS initialization phase to fix the integrated graphics configuration error. By fixing the problem at the hardware level, the resource consumption at the operating system and application levels can be reduced, optimizing the use of system resources. This ensures that the patch code is automatically injected at the correct time, thus resolving the integrated graphics configuration error in the early stages of system startup, providing users with a more stable, reliable, and efficient computing experience.

[0034] After powering on, the hardware patching circuit is enabled via the enable signal of the logic control module. The circuit is initialized via the RST signal to ensure its proper functioning. The integrated graphics card is then checked for proper display to confirm the effectiveness of the hardware patching circuit.

[0035] The hardware patching circuit is integrated into the motherboard design of the domestic CPU; during the boot process, the hardware patching circuit can automatically patch the integrated graphics card to ensure normal system display.

[0036] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A hardware patching circuit for CPU integrated graphics cards, comprising a CPU, wherein the CPU is provided with an SME bus and a JTAG bus; characterized in that, The hardware patching circuit also includes an I / O expander and a logic control module. The CPU converts the JTAG signal data through the I / O expander via the SME bus. Before the CPU TRST signal is activated, it reads and adapts the relevant settings of the integrated graphics inside the CPU. Finally, after the CPU TRST signal is activated, it outputs a set of fixed data to lock the JTAG signal. The input / output signals of the I / O expander are transmitted to the CPU through the JTAG bus. The logic control module is enabled during the computer startup process via the ENABLE signal and initialized via the RST signal.

2. The hardware patching circuit according to claim 1, characterized in that, The hardware patching circuit also includes a level converter; the level converter converts the JTAG signal output by the I / O expander into the level signal required by the JTAG bus.

3. The hardware patching circuit according to claim 2, characterized in that, The level signal is lower than the JTAG signal.

4. The hardware patching circuit according to any one of claims 1-3, characterized in that, The CPU also has a BIOS; the BIOS contains patch code.

5. The hardware patching circuit according to claim 1, characterized in that, The chip model of the I / O expander is PCA9557.

6. The hardware patching circuit according to claim 2, characterized in that, The level converter chip model is RS0104YT, which supports voltage conversion between side A (1.65V~5.5V) and side B (2.3V~5.5V).

7. The hardware patching circuit according to any one of claims 1-3, 5 and 6, characterized in that, The logic control module resets the circuit system via the RST signal and enables the ENABLE signal in the early power-on stage, triggering the automatic injection of patch code during the BIOS initialization phase to fix the integrated graphics configuration error.

8. The hardware patching circuit according to claim 3, characterized in that, The JTAG signal output by the I / O expander is 3.3V; the level signal output by the level converter is 1.8V.

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