N-channel metal oxide semiconductor (NMOS) tube gate drive circuit
By using a discrete component-designed NMOS gate drive circuit, the circuit structure is simplified and the cost is reduced, solving the problem of complex and costly NMOS gate drivers in the prior art, and realizing flexible gate drive in high-frequency and high-current applications.
Patent Information
- Application Number
- CN202520432066.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-03-13
AI Technical Summary
Existing NMOS transistor gate driver circuits are complex and costly, necessitating simplification of the circuit structure and reduction of costs.
Discrete components are used to replace integrated chips to design the gate drive circuit of NMOS transistors, including upper and lower bridge arm drive circuits. A push-pull module composed of bootstrap capacitors and transistors is used to provide drive signals for the NMOS transistors to achieve gate drive.
It simplifies the circuit structure, improves circuit flexibility, and realizes gate drive of NMOS transistors at extremely low cost, making it suitable for high-frequency, high-current applications.
Smart Images
Figure CN223899204U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit technology, and in particular to an NMOS transistor gate drive circuit. Background Technology
[0002] N-channel metal-oxide-semiconductor field-effect transistors (NMOS transistors) are commonly used in control systems across various industries, especially in high-frequency and high-current applications where dedicated integrated gate drivers are required to drive them. They are indispensable in power supply and brushless motor control systems. However, current gate driver circuits are complex and relatively expensive.
[0003] In other words, how to provide a new type of NMOS transistor gate drive circuit that uses discrete components to replace integrated chips, thereby simplifying the circuit structure and reducing costs, is a technical problem that urgently needs to be solved in this field. Utility Model Content
[0004] To address the aforementioned problems, this utility model aims to provide an NMOS transistor gate drive circuit that solves at least one of the above-mentioned technical issues.
[0005] This utility model provides an NMOS transistor gate driving circuit, the NMOS transistor gate driving circuit comprising:
[0006] A first NMOS transistor Q1, an upper bridge arm driving circuit that provides a driving signal to the first NMOS transistor Q1, a second NMOS transistor Q2, and a lower bridge arm driving circuit that provides a driving signal to the second NMOS transistor Q2;
[0007] The upper bridge arm drive circuit includes a bootstrap capacitor module, an upper bridge arm push module, and an upper bridge arm pull module. The first terminal of the bootstrap capacitor module is connected to an external first PWM signal. The second terminal of the bootstrap capacitor module is connected to both the first terminal of the upper bridge arm push module and the first terminal of the upper bridge arm pull module. The second terminals of both the upper bridge arm push module and the upper bridge arm pull module are connected to the gate of the first NMOS transistor Q1. The drain of the first NMOS transistor Q1 is connected to the DC bus voltage. The third terminals of both the bootstrap capacitor module and the upper bridge arm pull module are connected to the gate of the first NMOS transistor Q1. The source of Q1 is connected, and the source of the first NMOS transistor Q1 is connected to the load as the output terminal; the lower bridge arm drive circuit includes a lower bridge arm push module and a lower bridge arm pull module. The first terminal of the lower bridge arm push module and the first terminal of the lower bridge arm pull module are both connected to the second PWM signal. The second terminal of the lower bridge arm push module and the second terminal of the lower bridge arm pull module are both connected to the gate of the second NMOS transistor Q2. The third terminal of the lower bridge arm pull module is connected to the source of the second NMOS transistor Q2 and grounded. The drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1.
[0008] Specifically, when both the first PWM signal and the second PWM signal are high, the first NMOS transistor Q1 is turned on and the second NMOS transistor Q2 is turned off; when both the first PWM signal and the second PWM signal are low, the first NMOS transistor Q1 is turned off and the second NMOS transistor Q2 is turned on.
[0009] Preferably, the bootstrap capacitor module includes:
[0010] The first resistor R1, one end of which is the first terminal of the bootstrap capacitor module.
[0011] The base of the first transistor Q3 is connected to the other end of the first resistor R1.
[0012] The base of the second transistor Q4 is connected to the collector of the first transistor Q3, and the collector of the second transistor Q4 is the second terminal of the bootstrap capacitor module.
[0013] The second resistor R2 has one end connected to the emitter of the first transistor Q3, and the other end grounded.
[0014] The first diode D1, the cathode of the first diode D1 is connected to the emitter of the second transistor Q4;
[0015] A first power supply is connected to the anode of the first diode D1;
[0016] The first capacitor C1 has one end connected to the emitter of the first transistor Q3, and the other end of the first capacitor C1 is the third terminal of the bootstrap capacitor module.
[0017] Preferably, the upper bridge arm pusher module includes:
[0018] The second diode D2, the anode of the second diode D2 is the first end of the upper bridge arm push module;
[0019] The third resistor R3 has one end connected to the cathode of the second diode D2, and the other end of the third resistor R3 is the second end of the upper bridge arm push module.
[0020] Preferably, the upper bridge arm tensioning module includes:
[0021] The third transistor Q5, the base of the third transistor Q5 is the first terminal of the upper bridge arm pull module, and the collector of the third transistor Q5 is the third terminal of the upper bridge arm pull module;
[0022] The fourth resistor R4 is connected between the base and collector of the third transistor Q5;
[0023] The fifth resistor R5 has one end connected to the emitter of the third transistor Q5, and the other end is the second end of the upper bridge arm pull module.
[0024] Preferably, the lower bridge arm pusher module includes:
[0025] The sixth resistor R6, one end of which is the first end of the lower bridge arm push module;
[0026] The fourth transistor Q6, the emitter of which is connected to the other end of the sixth resistor R6;
[0027] The second power supply is connected to the base of the fourth transistor Q6;
[0028] The fifth transistor Q7 has its base connected to the collector of the fourth transistor Q6, and its emitter connected to the first power supply.
[0029] The seventh resistor R7 is connected between the base and emitter of the fifth transistor Q7;
[0030] The eighth resistor R8 has one end connected to the collector of the fifth transistor Q7, and the other end is the second end of the lower bridge arm push module.
[0031] Preferably, the lower bridge arm pull module includes:
[0032] The ninth resistor R9, one end of which is the first end of the lower bridge arm pull module;
[0033] The sixth transistor Q8 has its base connected to the other end of the ninth resistor R9, and its emitter is grounded.
[0034] The tenth resistor R10 has one end connected to the collector of the sixth transistor Q8, and the other end is the second end of the lower bridge arm pull module.
[0035] Preferably, the NMOS transistor gate drive circuit further includes:
[0036] The second capacitor C2 is connected between the gate and source of the first NMOS transistor Q1;
[0037] The third capacitor C3 is connected between the gate and source of the second NMOS transistor Q2.
[0038] Preferably, the first transistor Q3, the fourth transistor Q6, and the sixth transistor Q8 are all NPN transistors, and all are model 2N3904.
[0039] The second transistor Q4, the third transistor Q5, and the fifth transistor Q7 are all PNP transistors, and all of them are model SS8550.
[0040] Preferably, the first power supply provides 12V DC power, and the second power supply provides 5V DC power.
[0041] Preferably, the first diode D1 is of type IN4007 and the second diode D2 is of type IN4148.
[0042] Compared with the prior art, the beneficial effects of this utility model are:
[0043] Specifically, this utility model provides an NMOS transistor gate driving circuit, including a first NMOS transistor Q1, an upper bridge arm driving circuit, a second NMOS transistor Q2, and a lower bridge arm driving circuit. The upper bridge arm driving circuit includes a bootstrap capacitor module, an upper bridge arm push module, and an upper bridge arm pull module; the lower bridge arm driving circuit includes a lower bridge arm push module and a lower bridge arm pull module. The first terminal of the bootstrap capacitor module is connected to an external first PWM signal, and the second terminal of the bootstrap capacitor module is connected to the first terminal of the upper bridge arm push module and the first terminal of the upper bridge arm pull module, respectively. The second terminals of the upper bridge arm push module and the upper bridge arm pull module are both connected to the gate of the first NMOS transistor Q1. The drain of S-channel transistor Q1 is connected to the DC bus voltage. The third terminal of the bootstrap capacitor module and the third terminal of the upper bridge arm pull-up module are both connected to the source of the first NMOS transistor Q1. The source of the first NMOS transistor Q1 is connected to the load as the output terminal. The first terminal of the lower bridge arm push module and the first terminal of the lower bridge arm pull-up module are both connected to the second PWM signal. The second terminal of the lower bridge arm push module and the second terminal of the lower bridge arm pull-up module are both connected to the gate of the second NMOS transistor Q2. The third terminal of the lower bridge arm pull-up module is connected to the source of the second NMOS transistor Q2 and grounded. The drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1. The first PWM signal and the second PWM signal are synchronous. The upper bridge arm drive circuit provides a drive signal to the first NMOS transistor Q1, and the lower bridge arm drive circuit provides a drive signal to the second NMOS transistor Q2. A bootstrap capacitor module provides a gate drive voltage to the first NMOS transistor Q1. When the first PWM signal is high, this gate drive voltage drives the first NMOS transistor Q1 to conduct after passing through the upper bridge arm push module. At this time, the second PWM signal is low and, after passing through the lower bridge arm pull module, puts the second NMOS transistor Q2 in the off state. When the first PWM signal is low, the first NMOS transistor Q1 is turned off after passing through the upper bridge arm pull module. At this time, the second PWM signal is high, and this high level, after passing through the lower bridge arm push module, turns the second NMOS transistor Q2 on. The NMOS transistor gate drive circuit provided in this application uses discrete components instead of integrated chips, enabling fine adjustment of various parameters, simplifying the circuit structure while improving circuit flexibility, and achieving NMOS transistor gate drive at extremely low cost.
[0044] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is a schematic diagram of the overall structure of the NMOS transistor gate drive circuit in the embodiments of this application;
[0047] Figure 2 This is a schematic diagram showing the specific connection of the NMOS transistor gate drive circuit in the embodiments of this application. Detailed Implementation
[0048] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art are within the scope of protection of this utility model; wherein the keyword "and / or" involved in this embodiment indicates two situations, and or. In other words, A and / or B mentioned in the embodiments of this specification indicates two situations, A and B, and A or B, describing three states of A and B. For example, A and / or B means: only A is included and not B; only B is included and not A; and A and B are included.
[0049] Furthermore, in the embodiments of this specification, when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intervening component present. When a component is considered to be "set on" another component, it can be directly set on the other component or there may be an intervening component present.
[0050] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0051] Example 1
[0052] Please see Figure 1-2Specifically, in this embodiment of the NMOS transistor gate drive circuit, the NMOS transistor gate drive circuit provided in this application specifically includes a first NMOS transistor Q1, an upper bridge arm drive circuit that provides a drive signal to the first NMOS transistor Q1, a second NMOS transistor Q2, and a lower bridge arm drive circuit that provides a drive signal to the second NMOS transistor Q2. The upper bridge arm drive circuit includes a bootstrap capacitor module, an upper bridge arm push module, and an upper bridge arm pull module. The first terminal of the bootstrap capacitor module is connected to an external first PWM signal, and the second terminal of the bootstrap capacitor module is connected to the first terminal of the upper bridge arm push module and the first terminal of the upper bridge arm pull module, respectively. The second terminals of the upper bridge arm push module and the upper bridge arm pull module are both connected to the gate of the first NMOS transistor Q1. The drain of the first NMOS transistor Q1 is connected to the DC bus voltage. The third terminal of the bootstrap capacitor module and the third terminal of the upper bridge arm pull module are connected to the gate of the first NMOS transistor Q1. The first terminal of the first NMOS transistor Q1 is connected to the source of the second NMOS transistor Q1, and the source of the first NMOS transistor Q1 is connected to the load as the output terminal. The lower bridge arm drive circuit includes a lower bridge arm push module and a lower bridge arm pull module. The first terminal of the lower bridge arm push module and the first terminal of the lower bridge arm pull module are both connected to the second PWM signal. The second terminal of the lower bridge arm push module and the second terminal of the lower bridge arm pull module are both connected to the gate of the second NMOS transistor Q2. The third terminal of the lower bridge arm pull module is connected to the source of the second NMOS transistor Q2 and grounded. The drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1. When both the first PWM signal and the second PWM signal are high, the first NMOS transistor Q1 is turned on and the second NMOS transistor Q2 is turned off. When both the first PWM signal and the second PWM signal are low, the first NMOS transistor Q1 is turned off and the second NMOS transistor Q2 is turned on. The first PWM signal and the second PWM signal are synchronous.
[0053] Specifically, this utility model provides an NMOS transistor gate driving circuit, including a first NMOS transistor Q1, an upper bridge arm driving circuit, a second NMOS transistor Q2, and a lower bridge arm driving circuit. The upper bridge arm driving circuit includes a bootstrap capacitor module, an upper bridge arm push module, and an upper bridge arm pull module; the lower bridge arm driving circuit includes a lower bridge arm push module and a lower bridge arm pull module. The first terminal of the bootstrap capacitor module is connected to an external first PWM signal, and the second terminal of the bootstrap capacitor module is connected to the first terminal of the upper bridge arm push module and the first terminal of the upper bridge arm pull module, respectively. The second terminals of the upper bridge arm push module and the upper bridge arm pull module are both connected to the gate of the first NMOS transistor Q1. The drain of S-channel transistor Q1 is connected to the DC bus voltage. The third terminal of the bootstrap capacitor module and the third terminal of the upper bridge arm pull-up module are both connected to the source of the first NMOS transistor Q1. The source of the first NMOS transistor Q1 is connected to the load as the output terminal. The first terminal of the lower bridge arm push module and the first terminal of the lower bridge arm pull-up module are both connected to the second PWM signal. The second terminal of the lower bridge arm push module and the second terminal of the lower bridge arm pull-up module are both connected to the gate of the second NMOS transistor Q2. The third terminal of the lower bridge arm pull-up module is connected to the source of the second NMOS transistor Q2 and grounded. The drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1. The first PWM signal and the second PWM signal are synchronous. The upper bridge arm drive circuit provides a drive signal to the first NMOS transistor Q1, and the lower bridge arm drive circuit provides a drive signal to the second NMOS transistor Q2. A bootstrap capacitor module provides a gate drive voltage to the first NMOS transistor Q1. When the first PWM signal is high, this gate drive voltage drives the first NMOS transistor Q1 to conduct after passing through the upper bridge arm push module. At this time, the second PWM signal is high and, after passing through the lower bridge arm pull module, puts the second NMOS transistor Q2 in the off state. When the first PWM signal is low, the first NMOS transistor Q1 is turned off after passing through the upper bridge arm pull module. At this time, the second PWM signal is low, and this low level, after passing through the lower bridge arm push module, turns the second NMOS transistor Q2 on. The NMOS transistor gate drive circuit provided in this application uses discrete components instead of integrated chips, enabling fine adjustment of various parameters, simplifying the circuit structure while improving circuit flexibility, and achieving NMOS transistor gate drive at extremely low cost.
[0054] In one possible implementation, the bootstrap capacitor module includes a first resistor R1, a first transistor Q3, a second transistor Q4, a second resistor R2, a first diode D1, a first power supply, and a first capacitor C1. One end of the first resistor R1 is the first terminal of the bootstrap capacitor module, and the base of the first transistor Q3 is connected to the other end of the first resistor R1. The base of the second transistor Q4 is connected to the collector of the first transistor Q3, and the collector of the second transistor Q4 is the second terminal of the bootstrap capacitor module. One end of the second resistor R2 is connected to the emitter of the first transistor Q3, and the other end of the second resistor R2 is grounded. The cathode of the first diode D1 is connected to the emitter of the second transistor Q4. The first power supply is connected to the anode of the first diode D1. One end of the first capacitor C1 is connected to the emitter of the first transistor Q3, and the other end of the first capacitor C1 is the third terminal of the bootstrap capacitor module.
[0055] Specifically, the first capacitor C1 is a bootstrap capacitor used to provide the gate drive voltage to the first NMOS transistor Q1, and the voltage provided by the first capacitor C1 is always maintained at around 12V. The first diode D1 is a unidirectional charging diode of the bootstrap capacitor, and the model can be IN4007. The first transistor Q3 is an NPN transistor, and the model can be 2N3904, which is used as the driving transistor of the upper bridge arm driving circuit. The second transistor Q4 is a PNP transistor, and the model can be SS8550, which is used as the charging transistor of the first NMOS transistor Q1. The first power supply is used to provide 12V DC power.
[0056] like Figure 1 As shown, when the H_PWM input is high, the first transistor Q3 is turned on, and Q3 is in a saturated state, causing the second transistor Q4 to turn on, and the charging of the first NMOS transistor Q1 begins through the upper bridge arm push module; when the H_PWM input is low, the first transistor Q3 and the second transistor Q4 are turned off, and the upper bridge arm pull module causes the first NMOS transistor Q1 to discharge.
[0057] In one possible implementation, the upper bridge arm push module includes a second diode D2 and a third resistor R3. The anode of the second diode D2 is the first terminal of the upper bridge arm push module; one end of the third resistor R3 is connected to the cathode of the second diode D2, and the other end of the third resistor R3 is the second terminal of the upper bridge arm push module.
[0058] Among them, the second diode D2 is the unidirectional charging (push) diode of the first NMOS transistor Q1, and the model of the second diode D2 can be IN4148; the third resistor R3 is the charging (push) deceleration resistor of the first NMOS transistor Q1 to prevent the drain falling edge of Q1 from falling too fast during charging and causing resonance.
[0059] In one possible implementation, the upper bridge arm pull module includes a third transistor Q5, a fourth resistor R4, and a fifth resistor R5. The base of the third transistor Q5 is the first terminal of the upper bridge arm pull module, and the collector of the third transistor Q5 is the third terminal of the upper bridge arm pull module. The fourth resistor R4 is connected between the base and collector of the third transistor Q5. One end of the fifth resistor R5 is connected to the emitter of the third transistor Q5, and the other end of the fifth resistor R5 is the second terminal of the upper bridge arm pull module.
[0060] Specifically, the third transistor Q5 is the discharge (pull-up) transistor of the first NMOS transistor Q1. The third transistor Q5 is a PNP transistor, and the model can be selected as SS8550; the fourth resistor R4 is the discharge (pull-up) drive resistor of Q1; when the first NMOS transistor Q1 is turned off, the fourth resistor R4 turns on the third transistor Q5, so that the first NMOS transistor Q1 discharges quickly; the fifth resistor R5 is the discharge (pull-up) deceleration resistor of the first NMOS transistor Q1, to prevent the discharge from being too fast and causing resonance at the rising edge of the drain of the first NMOS transistor Q1.
[0061] In one possible implementation, the lower bridge arm push module includes a sixth resistor R6, a fourth transistor Q6, a second power supply, a fifth transistor Q7, a seventh resistor R7, and an eighth resistor R8. One end of the sixth resistor R6 is the first end of the lower bridge arm push module; the emitter of the fourth transistor Q6 is connected to the other end of the sixth resistor R6; the second power supply is connected to the base of the fourth transistor Q6; the base of the fifth transistor Q7 is connected to the collector of the fourth transistor Q6, and the emitter of the fifth transistor Q7 is connected to the first power supply; the seventh resistor R7 is connected between the base and emitter of the fifth transistor Q7; one end of the eighth resistor R8 is connected to the collector of the fifth transistor Q7, and the other end of the eighth resistor R8 is the second end of the lower bridge arm push module.
[0062] Among them, the sixth resistor R6 is used for current limiting; the fourth transistor Q6 is an NPN transistor, and the model can be selected as 2N3904, which serves as the charging driver transistor; the second power supply is used to provide 5V DC power; the seventh resistor R7 is connected between the base and emitter of the fifth transistor Q7 to facilitate the turn-off of Q5; the fifth transistor Q7 is a PNP transistor, and the model can be selected as SS8550, which serves as the charging (push) transistor of the second NMOS transistor Q2; the eighth resistor R8 is the charging deceleration resistor of the second NMOS transistor Q2 to prevent resonance caused by the drain falling edge of Q2 being too fast during charging.
[0063] When the L_PWM input is low, the fourth transistor Q6 is in saturation, causing the fifth transistor Q7 to conduct and begin charging (pushing) the second NMOS transistor Q2. When the L_PWM input is high, the fourth transistor Q6 and the fifth transistor Q7 are cut off, and the sixth transistor Q8 conducts, causing the second NMOS transistor Q2 to discharge rapidly.
[0064] In one possible implementation, the lower bridge arm pull-up module includes a ninth resistor R9, a sixth transistor Q8, and a tenth resistor R10. One end of the ninth resistor R9 is the first end of the lower bridge arm pull-up module; the base of the sixth transistor Q8 is connected to the other end of the ninth resistor R9, and the emitter of the sixth transistor Q8 is grounded; one end of the tenth resistor R10 is connected to the collector of the sixth transistor Q8, and the other end of the tenth resistor R10 is the second end of the lower bridge arm pull-up module.
[0065] In this application, the sixth transistor Q8 is an NPN transistor, and the model number is 2N3904. It serves as the discharge (pull-up) transistor for the second NMOS transistor Q2. R10 is a discharge deceleration resistor to prevent the drain rising edge of the second NMOS transistor Q2 from being too fast and causing resonance. The ninth resistor R9 is used for current limiting.
[0066] In one possible implementation, the NMOS transistor gate drive circuit further includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 is connected between the gate and source of the first NMOS transistor Q1; the third capacitor C3 is connected between the gate and source of the second NMOS transistor Q2. This reduces the charging speed of the first NMOS transistor Q1 by using the second capacitor C2 and reduces the charging speed of the second NMOS transistor Q2 by using the third capacitor C3.
[0067] It should be noted that H_PWM is low when Q1 is turned off, and L_PWM is high when Q2 is turned off; the dead time needs to be controlled by the controller and cannot be driven simultaneously.
[0068] In practical applications, the switching devices Q1 and Q2 of the upper and lower bridge arms cannot be turned on simultaneously, otherwise it will cause a short circuit and damage the devices. Furthermore, the turn-on and turn-off of the two switching devices in the upper and lower bridge arms require a certain amount of time. Without a dead time, one switching device may not be completely turned off before the other has already started turning on, resulting in a shoot-through. Therefore, a time interval where both switching devices are in the off state can be inserted during the transition between the two synchronous PWM signals—the dead time—to ensure that one switching device is completely turned off before the other turns on, thus protecting the devices in the circuit from damage.
[0069] In general, when the H_PWM input is low and the L_PWM input is low, the first transistor Q3 and the second transistor Q4 are cut off. The fourth resistor R4 turns on the third transistor Q5, causing Q1 to be cut off. At the same time, the fourth transistor Q6 and the fifth transistor Q7 turn on, causing Q2 to turn on. A circuit is formed between the first power supply, the first capacitor C1 and Q2 to charge the first capacitor C1. At this time, the output terminal (VOUT) connected to the load is grounded and disconnected from the DC bus voltage (HV+ terminal).
[0070] When the H_PWM input is high and the L_PWM input is high, the first transistor Q3, the second transistor Q4, and the first NMOS transistor Q1 are turned on. At the same time, the sixth transistor Q8 is turned on, and the fourth transistor Q6 and the fifth transistor Q7 are turned off, causing the second NMOS transistor Q2 to be turned off. At this time, the output terminal (VOUT) connected to the load is connected to the DC bus voltage (HV+ terminal).
[0071] The DC bus voltage is related to the specific load connected to it.
[0072] like Figure 2 As shown, when the load is a resistive load, a resistor R11 can be connected to the output terminal (VOUT terminal) of this application, and the end of the resistor R11 away from the output terminal is grounded. The resistance value of the resistor R11 is 10KΩ. When the load is an inductive load, the resistor R11 is not required.
[0073] In the specific circuit configuration provided in this application, the resistance values of the first resistor R1 can be selected as 2KΩ, the second resistor R2 can be selected as 2KΩ, the third resistor R3 can be selected as 10Ω, the fourth resistor R4 can be selected as 2.2KΩ, the fifth resistor R5 can be selected as 5.1Ω, the sixth resistor R6 can be selected as 2KΩ, the seventh resistor R7 can be selected as 1KΩ, the eighth resistor R8 can be selected as 10Ω, the ninth resistor R9 can be selected as 2KΩ, the tenth resistor R10 can be selected as 5.1Ω, the first capacitor C1 can be selected as 47μF, and the second capacitor C2 and the third capacitor C3 can be selected as 100pF.
[0074] This circuit is suitable for use in various brushless DC motors, brushed DC electrodes, power converters, and power control devices that require gate drive circuits, achieving gate drive at extremely low cost. It adapts to the bus voltage, reaching over 200V, depending on the voltage rating of the transistor and MOSFET; the frequency can reach over 100kHz, depending on the matching relationship between the transistor drive resistor and the MOSFET parasitic capacitance; and the discrete components used can be flexibly adjusted.
[0075] This circuit is flexible in use, as it uses discrete components, allowing for fine adjustment of various parameters. The lower bridge arm NMOS (Q2 and lower bridge arm drive circuit) of this application can be implemented independently and can be used independently in NMOS circuits that only require one lower bridge arm, such as in scenarios like DC brushed motors, DC heaters, and high-power lighting control. The upper bridge arm drive circuit is usually used simultaneously with the lower bridge arm drive circuit, but it can also be used independently in special cases, such as DC heaters (resistive loads).
[0076] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.
[0077] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model's technical solution. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the content of the present utility model's technical solution shall still fall within the scope of the present utility model's technical solution.
Claims
1. An NMOS transistor gate drive circuit, characterized in that, The NMOS transistor gate drive circuit includes: A first NMOS transistor Q1, an upper bridge arm driving circuit that provides a driving signal to the first NMOS transistor Q1, a second NMOS transistor Q2, and a lower bridge arm driving circuit that provides a driving signal to the second NMOS transistor Q2; The upper bridge arm drive circuit includes a bootstrap capacitor module, an upper bridge arm push module, and an upper bridge arm pull module. The first terminal of the bootstrap capacitor module is connected to an external first PWM signal. The second terminal of the bootstrap capacitor module is connected to both the first terminal of the upper bridge arm push module and the first terminal of the upper bridge arm pull module. The second terminals of both the upper bridge arm push module and the upper bridge arm pull module are connected to the gate of the first NMOS transistor Q1. The drain of the first NMOS transistor Q1 is connected to the DC bus voltage. The third terminals of both the bootstrap capacitor module and the upper bridge arm pull module are connected to the gate of the first NMOS transistor Q1. The source of Q1 is connected, and the source of the first NMOS transistor Q1 is connected to the load as the output terminal; the lower bridge arm drive circuit includes a lower bridge arm push module and a lower bridge arm pull module. The first terminal of the lower bridge arm push module and the first terminal of the lower bridge arm pull module are both connected to the second PWM signal. The second terminal of the lower bridge arm push module and the second terminal of the lower bridge arm pull module are both connected to the gate of the second NMOS transistor Q2. The third terminal of the lower bridge arm pull module is connected to the source of the second NMOS transistor Q2 and grounded. The drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1. Specifically, when both the first PWM signal and the second PWM signal are high, the first NMOS transistor Q1 is turned on and the second NMOS transistor Q2 is turned off; when both the first PWM signal and the second PWM signal are low, the first NMOS transistor Q1 is turned off and the second NMOS transistor Q2 is turned on.
2. The NMOS transistor gate drive circuit as described in claim 1, characterized in that, The bootstrap capacitor module includes: The first resistor R1, one end of which is the first terminal of the bootstrap capacitor module. The base of the first transistor Q3 is connected to the other end of the first resistor R1. The base of the second transistor Q4 is connected to the collector of the first transistor Q3, and the collector of the second transistor Q4 is the second terminal of the bootstrap capacitor module. The second resistor R2 has one end connected to the emitter of the first transistor Q3, and the other end grounded. The first diode D1, the cathode of the first diode D1 is connected to the emitter of the second transistor Q4; A first power supply is connected to the anode of the first diode D1; The first capacitor C1 has one end connected to the emitter of the first transistor Q3, and the other end of the first capacitor C1 is the third terminal of the bootstrap capacitor module.
3. The NMOS transistor gate drive circuit as described in claim 2, characterized in that, The upper bridge arm push module includes: The second diode D2, the anode of the second diode D2 is the first end of the upper bridge arm push module; The third resistor R3 has one end connected to the cathode of the second diode D2, and the other end of the third resistor R3 is the second end of the upper bridge arm push module.
4. The NMOS transistor gate drive circuit as described in claim 3, characterized in that, The upper bridge arm tension module includes: The third transistor Q5, the base of the third transistor Q5 is the first terminal of the upper bridge arm pull module, and the collector of the third transistor Q5 is the third terminal of the upper bridge arm pull module; The fourth resistor R4 is connected between the base and collector of the third transistor Q5; The fifth resistor R5 has one end connected to the emitter of the third transistor Q5, and the other end is the second end of the upper bridge arm pull module.
5. The NMOS transistor gate drive circuit as described in claim 4, characterized in that, The lower bridge arm pusher module includes: The sixth resistor R6, one end of which is the first end of the lower bridge arm push module; The fourth transistor Q6, the emitter of which is connected to the other end of the sixth resistor R6; The second power supply is connected to the base of the fourth transistor Q6; The fifth transistor Q7 has its base connected to the collector of the fourth transistor Q6, and its emitter connected to the first power supply. The seventh resistor R7 is connected between the base and emitter of the fifth transistor Q7; The eighth resistor R8 has one end connected to the collector of the fifth transistor Q7, and the other end is the second end of the lower bridge arm push module.
6. The NMOS transistor gate drive circuit as described in claim 5, characterized in that, The lower bridge arm support module includes: The ninth resistor R9, one end of which is the first end of the lower bridge arm pull module; The sixth transistor Q8 has its base connected to the other end of the ninth resistor R9, and its emitter is grounded. The tenth resistor R10 has one end connected to the collector of the sixth transistor Q8, and the other end is the second end of the lower bridge arm pull module.
7. The NMOS transistor gate drive circuit as described in claim 6, characterized in that, The NMOS transistor gate drive circuit also includes: The second capacitor C2 is connected between the gate and source of the first NMOS transistor Q1; The third capacitor C3 is connected between the gate and source of the second NMOS transistor Q2.
8. The NMOS transistor gate drive circuit as described in claim 7, characterized in that: The first transistor Q3, the fourth transistor Q6, and the sixth transistor Q8 are all NPN transistors, and all of them are model 2N3904. The second transistor Q4, the third transistor Q5, and the fifth transistor Q7 are all PNP transistors, and all of them are model SS8550.
9. The NMOS transistor gate drive circuit as described in claim 8, characterized in that, The first power supply provides 12V DC power, and the second power supply provides 5V DC power.
10. The NMOS transistor gate drive circuit as described in claim 9, characterized in that, The first diode D1 is of type IN4007, and the second diode D2 is of type IN4148.