Solar cell coating monitoring sheet

Abstract

The utility model provides a solar cell coating monitoring piece. The solar cell coating monitoring piece comprises a semiconductor substrate, a first passivation contact structure and a second passivation contact structure. The semiconductor substrate is provided with a first surface and a second surface which are opposite to each other, the first passivation contact structure comprises a first dielectric layer and a first doping layer which are sequentially stacked on the first surface, and the second passivation contact structure comprises a second dielectric layer and a second doping layer which are sequentially stacked on the second surface; and the doping types of the first doping layer and the second doping layer are the same. The solar cell film coating monitoring piece can be used for selectively managing and controlling the film coating process and reflecting whether the film coating process is abnormal or not.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic technology, and in particular to a solar cell coating monitoring sheet. Background Technology

[0002] Tunnel oxide passivated contact (TOC) solar cells are a type of crystalline silicon solar cell with high conversion efficiency. They are characterized by a passivated contact structure on the silicon wafer that includes a tunneling dielectric layer and a doped polycrystalline silicon layer. This passivated contact structure can significantly reduce carrier recombination loss while maintaining good carrier transport performance, thus achieving high photoelectric conversion efficiency.

[0003] In actual production, the tunneling dielectric layer and the doped polycrystalline silicon layer are typically prepared using a coating process. Even slight fluctuations in coating conditions can affect the efficiency of solar cells. Therefore, it is necessary to control the coating process to ensure that the produced solar cells have stable and high conversion efficiencies. However, it is currently difficult to selectively control individual coating processes. Specifically, the surface of the semi-finished cell after the coating process has not yet formed passivation, so its related performance cannot be accurately tested during the coating process. Furthermore, if subsequent processes are completed after the coating process and testing is performed, the test results are affected by these subsequent processes, making it difficult to eliminate interference and determine whether any abnormalities have occurred in the coating process. Utility Model Content

[0004] Therefore, it is necessary to provide a solar cell coating monitoring chip that can selectively control the coating process and indicate whether any abnormalities occur in the coating process.

[0005] According to embodiments of this disclosure, a solar cell coating monitoring chip is provided, comprising: a semiconductor substrate, a first passivation contact structure, and a second passivation contact structure;

[0006] The semiconductor substrate has a first surface and a second surface opposite to each other. The first passivation contact structure includes a first dielectric layer and a first doped layer stacked sequentially on the first surface. The second passivation contact structure includes a second dielectric layer and a second doped layer stacked sequentially on the second surface. The first doped layer and the second doped layer have the same doping type.

[0007] In some embodiments of this disclosure, the first doped layer and the second doped layer are made of the same material.

[0008] In some embodiments of this disclosure, both the first doped layer and the second doped layer are doped polysilicon layers, and the doping elements in the first doped layer and the second doped layer are the same.

[0009] In some embodiments of this disclosure, the first doped layer and the second doped layer have the same thickness.

[0010] In some embodiments of this disclosure, the first dielectric layer and the second dielectric layer are made of the same material.

[0011] In some embodiments of this disclosure, both the first dielectric layer and the second dielectric layer are silicon oxide layers.

[0012] In some embodiments of this disclosure, the first dielectric layer and the second dielectric layer have the same thickness.

[0013] In some embodiments of this disclosure, both the first surface and the second surface are flat surfaces.

[0014] In some embodiments of this disclosure, the semiconductor substrate is a silicon wafer.

[0015] In some embodiments of this disclosure, the thickness of the first dielectric layer is 1 nm to 3 nm, and the thickness of the second dielectric layer is 1 nm to 3 nm; and / or,

[0016] The thickness of the first doped layer is 80 nm to 130 nm; and / or, the thickness of the second doped layer is 80 nm to 130 nm.

[0017] At least one embodiment of this disclosure includes a solar cell coating monitoring chip comprising a semiconductor substrate, a first passivation contact structure, and a second passivation contact structure. The first passivation contact structure includes a first dielectric layer and a first doped layer, and the second passivation contact structure includes a stacked second dielectric layer and a second doped layer. The first and second passivation contact structures can be fabricated in the same coating process and are used to passivate opposite surfaces of the semiconductor substrate, respectively, enabling more accurate measurement of the monitoring chip's performance. Furthermore, since the first and second doped layers have the same doping type, they have the same minority carrier type, which is beneficial for measuring parameters related to the passivation effect, such as minority carrier lifetime and open-circuit voltage. The passivation effect is directly related to the coating conditions, and parameters related to the passivation effect can directly reflect whether there are any abnormalities in the coating process. Therefore, this solar cell coating monitoring chip can be used to selectively control the coating process and indicate whether any abnormalities have occurred during the coating process. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the cross-sectional structure of a solar cell coated monitoring chip;

[0019] Figure 2 To measure the minority carrier lifetime of solar cell coating monitoring wafers when different abnormal conditions occur during the coating process;

[0020] Figure 3 This refers to the open-circuit voltage of the solar cell coating monitoring chip when different abnormal conditions occur during the coating process.

[0021] The reference numerals and their meanings in the accompanying drawings are as follows:

[0022] 100, Semiconductor substrate; 110, First dielectric layer; 120, First doped layer; 130, Second dielectric layer; 140, Second doped layer. Detailed Implementation

[0023] To facilitate understanding of this utility model, a more comprehensive description of it will be provided below in conjunction with embodiments and effect diagrams. The embodiments provide preferred embodiments of this utility model. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.

[0024] It should be noted that when one component is referred to as being "fixed" to another component, it can be directly fixed to the other component or fixed to the other component through an intermediate component. When one component is referred to as being "connected" to another component, it can be directly connected to the other component, or there can be an intermediate component between the two components. Furthermore, in the description of this utility model, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "attached" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integrated connection. For example, it can be a mechanical connection or an electrical connection. For example, it can be a direct connection or an indirect connection through an intermediate component, or it can be a connection within two components. It should be understood that those skilled in the art can interpret the specific meaning of the above terms according to the specific circumstances without causing ambiguity.

[0025] Unless otherwise specified, in the description of this utility model, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," which indicate orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings of the utility model. They are only for the convenience and simplification of the description of the utility model and to help the reader understand it in conjunction with the accompanying drawings, and are not intended to limit or imply a specific orientation that the device or element referred to must have. Therefore, they should not be construed as limitations on this utility model.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the implementation of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. "More" herein includes combinations of two or more items.

[0027] This disclosure provides a solar cell coating monitoring chip, comprising: a semiconductor substrate, a first passivation contact structure, and a second passivation contact structure. The semiconductor substrate has a first surface and a second surface opposite to each other. The first passivation contact structure includes a first dielectric layer and a first doped layer sequentially stacked on the first surface. The second passivation contact structure includes a second dielectric layer and a second doped layer sequentially stacked on the second surface. The first doped layer and the second doped layer have the same doping type.

[0028] At least one embodiment of this disclosure includes a solar cell coating monitoring chip comprising a semiconductor substrate, a first passivation contact structure, and a second passivation contact structure. The first passivation contact structure includes a first dielectric layer and a first doped layer, and the second passivation contact structure includes a stacked second dielectric layer and a second doped layer. The first and second passivation contact structures can be fabricated in the same coating process and are used to passivate opposite surfaces of the semiconductor substrate, respectively, enabling more accurate measurement of the monitoring chip's performance. Furthermore, since the first and second doped layers have the same doping type, they have the same minority carrier type, which is beneficial for measuring parameters related to the passivation effect, such as minority carrier lifetime and open-circuit voltage. The passivation effect is directly related to the coating conditions, and parameters related to the passivation effect can directly reflect whether there are any abnormalities in the coating process. Therefore, this solar cell coating monitoring chip can be used to selectively control the coating process and indicate whether any abnormalities have occurred during the coating process.

[0029] For solar cells in practical use, two doped layers of different doping types are typically disposed on opposite surfaces of the semiconductor substrate to form a PN junction and provide passivation. Unlike practical solar cells, the solar cell coating monitoring chip in this disclosure has a first doped layer and a second doped layer of the same doping type disposed on opposite surfaces of the semiconductor substrate. Its main function is to provide measurements to reflect the passivation effect, thereby visually indicating whether there are any abnormalities in the coating process.

[0030] Figure 1 This is a schematic diagram of the cross-sectional structure of a solar cell coated monitoring chip. (Refer to...) Figure 1As shown, the solar cell coating monitoring chip includes a semiconductor substrate 100, a first passivation contact structure, and a second passivation contact structure. The semiconductor substrate 100 has opposing first surfaces (such as...). Figure 1 The upper surface shown) and the second surface (as shown) Figure 1 (See the lower surface shown). In this embodiment, the first passivation contact structure includes a first dielectric layer 110 and a first doped layer 120, which are sequentially stacked on the first surface. The second passivation contact structure includes a second dielectric layer 130 and a second doped layer 140, which are sequentially stacked on the second surface. Furthermore, the doping type of the first doped layer 120 and the doping type of the second doped layer 140 are the same.

[0031] As an example of this embodiment, the material of the semiconductor substrate 100 may be selected from one or more of silicon, germanium, gallium nitride, gallium arsenide, and silicon carbide. As a further example of this embodiment, the semiconductor substrate 100 contains doping elements, and the doping type of the semiconductor substrate 100 may be the same as or different from the doping type of the first doped layer 120.

[0032] In this embodiment, a silicon wafer can be used as the semiconductor substrate 100, for example, an N-type silicon wafer or a P-type silicon wafer can be used as the semiconductor substrate 100.

[0033] As an example of this embodiment, both the first and second surfaces of the semiconductor substrate 100 are flat surfaces. In this example, making the surface of the semiconductor substrate 100 flat helps to eliminate the influence of texturing processes on the coated monitoring sheet. In conventional solar cells, at least one surface of the semiconductor substrate 100 always has a textured structure. The textured structure can be prepared by etching the semiconductor substrate 100 with an alkaline solution. The surface with the textured structure is uneven, and the textured structure is used to enhance the light absorption capacity of the semiconductor substrate 100. In this embodiment, the solar cell coated monitoring sheet does not need to consider the light absorption capacity of the semiconductor substrate 100, so its surface does not need to have a textured structure.

[0034] As an example of this embodiment, the first doped layer 120 and the second doped layer 140 are made of the same material. This allows the first doped layer 120 and the second doped layer 140 to be prepared using the same raw materials and in the same coating chamber, simplifying the preparation process.

[0035] As an example of this embodiment, both the first doped layer 120 and the second doped layer 140 are doped polycrystalline silicon layers, and the doping elements in the first doped layer 120 and the second doped layer 140 are the same. In some examples, when both the first doped layer 120 and the second doped layer 140 are P-type doped, the doping element may be one or more of boron, aluminum, and gallium. In some examples, when both the first doped layer 120 and the second doped layer 140 are N-type doped, the doping element may be one or more of phosphorus and arsenic.

[0036] As a further example of this embodiment, both the first doped layer 120 and the second doped layer 140 can be boron-doped polycrystalline silicon layers, or both the first doped layer 120 and the second doped layer 140 can be phosphorus-doped polycrystalline silicon layers.

[0037] As an example of this embodiment, the first doped layer 120 and the second doped layer 140 can be prepared by chemical vapor deposition. Further, the first doped layer 120 and the second doped layer 140 can be prepared by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).

[0038] As an example of this embodiment, the thickness of the first doped layer 120 can be 80nm to 130nm. In some examples, the thickness of the first doped layer 120 is 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, or 130nm, or the thickness of the first doped layer 120 can be between any two of the above thicknesses.

[0039] As an example of this embodiment, the thickness of the second doped layer 140 can be 80nm to 130nm. In some examples, the thickness of the second doped layer 140 is 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, or 130nm, or the thickness of the second doped layer 140 can be between any two of the above thicknesses.

[0040] As an example of this embodiment, the first doped layer 120 and the second doped layer 140 have the same thickness. It is understood that the first doped layer 120 and the second doped layer 140 can be prepared using the same coating conditions, which allows the solar cell coating monitoring chip to be used for selective monitoring of the coating conditions.

[0041] As an example of this embodiment, the first dielectric layer 110 and the second dielectric layer 130 are made of the same material. This allows the first dielectric layer 110 and the second dielectric layer 130 to be prepared using the same raw materials and in the same coating chamber, simplifying the preparation process.

[0042] As an example of this embodiment, both the first dielectric layer 110 and the second dielectric layer 130 are silicon oxide layers.

[0043] As an example of this embodiment, the thickness of the first dielectric layer 110 is 1 nm to 3 nm. For example, the thickness of the first dielectric layer 110 can be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.2 nm, 2.5 nm, 2.8 nm, or 3 nm, or the thickness of the first dielectric layer 110 can be between any two of the above thicknesses.

[0044] As an example of this embodiment, the thickness of the second dielectric layer 130 is 1 nm to 3 nm. For example, the thickness of the second dielectric layer 130 can be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.2 nm, 2.5 nm, 2.8 nm, or 3 nm, or the thickness of the second dielectric layer 130 can be between any two of the above thicknesses.

[0045] As an example of this embodiment, the first dielectric layer 110 and the second dielectric layer 130 have the same thickness. It is understood that the first dielectric layer 110 and the second dielectric layer 130 can be prepared using the same coating conditions, which allows the solar cell coating monitoring sheet to be used for selective monitoring of the coating conditions.

[0046] As an example of this embodiment, the first dielectric layer 110 and the second dielectric layer 130 can be prepared by chemical vapor deposition. Further, the first dielectric layer 110 and the second dielectric layer 130 can be prepared by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition.

[0047] Furthermore, this disclosure also provides a method such as Figure 1 The method for preparing the solar cell coating monitoring film shown includes the following steps S1 to S3.

[0048] Step S1: Provide an intermediate sheet before coating.

[0049] In this embodiment, the pre-coating intermediate sheet includes a semiconductor substrate 100 and a doped material layer stacked on the semiconductor substrate 100.

[0050] As an example of this embodiment, the preparation process of the intermediate wafer before coating includes the following steps: texturing the semiconductor substrate 100 and forming a doped material layer on the surface of the texturized semiconductor substrate 100.

[0051] In this embodiment, the semiconductor substrate 100 is optionally an N-type silicon wafer. The doping type of the doped material layer is opposite to that of the semiconductor substrate 100, and the material of the doped material layer can be boron-doped polycrystalline silicon.

[0052] As a further example of this embodiment, the semiconductor substrate 100 can be texturized using a texturing agent containing an alkali, wherein the alkali can be sodium hydroxide or potassium hydroxide.

[0053] As a further example of this embodiment, the method of forming the doped material layer is boron diffusion, which includes: placing the semiconductor substrate 100 in a diffusion furnace, introducing a boron source into the diffusion furnace to form a borosilicate glass layer (BSG) on the semiconductor substrate 100, and then heating to perform a push-junction process so that boron atoms diffuse into the surface of the semiconductor substrate 100 and form boron-doped polysilicon as the doped material layer.

[0054] Step S2: Remove the doped material layer of the intermediate wafer before coating, leaving the semiconductor substrate 100.

[0055] As an example of this embodiment, before removing the doped material layer, the method further includes: using a cleaning agent containing hydrofluoric acid to remove the borosilicate glass layer formed in step S1.

[0056] As an example of this embodiment, the method for removing the doped material layer includes polishing the pre-deposition intermediate wafer with an alkaline polishing solution to remove the doped material layer. Further, when polishing the pre-deposition intermediate wafer, a polishing solution can be used to simultaneously polish both opposite surfaces of the pre-deposition intermediate wafer to obtain a clean semiconductor substrate 100.

[0057] Step S3: deposit a first dielectric layer 110 and a second dielectric layer 130 on opposite sides of the semiconductor substrate 100, and deposit a first doped layer 120 and a second doped layer 140 on opposite sides of the semiconductor substrate 100.

[0058] As an example of this embodiment, the first dielectric layer 110 and the second dielectric layer 130 are deposited by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition.

[0059] As an example of this embodiment, the first doped layer 120 and the second doped layer 140 are deposited by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition.

[0060] As an example of this embodiment, the first dielectric layer 110, the second dielectric layer 130, the first doped layer 120, and the second doped layer 140 can be deposited sequentially in the same deposition chamber. For example, the first dielectric layer 110 can be deposited first, followed by the second dielectric layer 130, then the first doped layer 120, and finally the second doped layer 140.

[0061] As a further example of this embodiment, the first dielectric layer 110 and the second dielectric layer 130 can be deposited using the exact same process.

[0062] As a further example of this embodiment, during the deposition of the first dielectric layer 110 and the second dielectric layer 130, a silicon source gas and an oxygen source gas can be introduced into the deposition chamber. The silicon source gas can be selected from hydrides, such as silane (SiH4). The oxygen source gas can be selected from oxides, such as nitrous oxide (N2O).

[0063] As a further example of this embodiment, the first doped layer 120 and the second doped layer 140 can be deposited using the exact same process.

[0064] As a further example of this embodiment, during the deposition of the first doped layer 120 and the second doped layer 140, a silicon source gas and a dopant source gas can be introduced into the deposition chamber. The silicon source gas can be selected from hydrides, such as silane (SiH4). The dopant source gas can be selected from phosphides or borides; the phosphide can be phosphine (PH3), and the boride can be, for example, boron trichloride (BCl3).

[0065] Through the above steps S1 to S3, the preparation of the solar cell coating monitoring sheet of this disclosure can be completed.

[0066] Traditional solar cell fabrication processes typically include step S1, which involves texturing a semiconductor substrate and preparing a doped material layer to serve as the emitter. Following step S1, alkaline polishing and coating processes are usually performed on the surface of the semiconductor substrate furthest from the doped material layer. The fabrication method disclosed herein utilizes a pre-coating intermediate wafer produced in the normal production process. Then, in the alkaline polishing step, both surfaces of the pre-coating intermediate wafer are simultaneously alkaline polished, and finally, both surfaces of the semiconductor substrate are coated in the coating process. This fabrication method has at least the following advantages: Firstly, the solar cell coated monitoring wafer directly uses intermediate products from the normal solar cell production process as raw materials and is fabricated using the normal production process, without the need for additional fabrication processes, thus requiring virtually no additional cost and being easy to implement. Secondly, the fabrication process of the solar cell coated monitoring wafer can be performed simultaneously with the normal solar cell production process, and the influence of processes such as texturing, boron diffusion, and polishing before the coating process can be eliminated, ensuring that the performance of the monitoring wafer is only affected by the coating process. On the other hand, the solar cell coating monitoring sheet is carried out simultaneously with the normal production process, which can significantly shorten the verification time of the coating process and thus improve production efficiency to a certain extent.

[0067] Furthermore, this disclosure also provides an approach such as Figure 1 The method for monitoring the quality of the solar cell coating process using the solar cell coating monitoring chip shown includes the following steps: testing at least one of the minority carrier lifetime and open-circuit voltage of the solar cell coating monitoring chip in the above embodiment, comparing the measured minority carrier lifetime with a reference minority carrier lifetime, and / or comparing the measured open-circuit voltage with a reference open-circuit voltage, and determining whether an abnormality has occurred in the coating process based on the comparison results.

[0068] It is understood that in this embodiment, the reference minority carrier lifetime refers to the minority carrier lifetime of the solar cell coating monitoring wafer prepared when the coating process is normal. This lifetime can be statistically determined from experimental results and preset manually. The reference minority carrier lifetime can be a range value; if the measured minority carrier lifetime is outside this range, it can be determined that the coating process is abnormal. The reference open-circuit voltage refers to the open-circuit voltage of the solar cell coating monitoring wafer prepared when the coating process is normal. This voltage can be statistically determined from experimental results and preset manually. The reference open-circuit voltage can also be a range value; if the measured open-circuit voltage is outside this range, it can be determined that the coating process is abnormal.

[0069] This is publicly available. Figure 2 This illustrates the minority carrier lifetime of solar cell coating monitoring wafers under different abnormal conditions during the coating process. For example... Figure 2As shown, it can be found that when the nitrous oxide flow rate, annealing temperature, phosphine flow rate, or radio frequency power is abnormal, the minority carrier lifetime of the solar cell coating monitoring chip is significantly lower than the baseline minority carrier lifetime. This indicates that the minority carrier lifetime of the solar cell coating monitoring chip can intuitively and accurately reflect whether there are any abnormalities in the coating process.

[0070] This is publicly available. Figure 3 This illustrates the changes in the open-circuit voltage of the solar cell coating monitoring wafer when different abnormal conditions occur during the coating process. For example... Figure 3 As shown, it can be found that when the nitrous oxide flow rate, annealing temperature, phosphine flow rate, or radio frequency power is abnormal, the open-circuit voltage of the solar cell coating monitoring chip is significantly lower than the reference open-circuit voltage. This indicates that the open-circuit voltage of the solar cell coating monitoring chip can also intuitively and accurately reflect whether there are any abnormalities in the coating process.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A solar cell coated monitoring sheet, characterized in that, include: Semiconductor substrate (100), first passivation contact structure and second passivation contact structure; The semiconductor substrate (100) has a first surface and a second surface opposite to each other. The first passivation contact structure includes a first dielectric layer (110) and a first doped layer (120) stacked sequentially on the first surface. The second passivation contact structure includes a second dielectric layer (130) and a second doped layer (140) stacked sequentially on the second surface. The first doped layer (120) and the second doped layer (140) have the same doping type.

2. The solar cell coating monitoring sheet according to claim 1, characterized in that, The first doped layer (120) and the second doped layer (140) are made of the same material.

3. The solar cell coating monitoring sheet according to claim 2, characterized in that, Both the first doped layer (120) and the second doped layer (140) are doped polysilicon layers, and the doping elements in the first doped layer (120) and the second doped layer (140) are the same.

4. The solar cell coating monitoring sheet according to claim 3, characterized in that, The first doped layer (120) and the second doped layer (140) have the same thickness.

5. The solar cell coating monitoring sheet according to any one of claims 1 to 4, characterized in that, The first dielectric layer (110) and the second dielectric layer (130) are made of the same material.

6. The solar cell coating monitoring sheet according to claim 5, characterized in that, Both the first dielectric layer (110) and the second dielectric layer (130) are silicon oxide layers.

7. The solar cell coating monitoring sheet according to claim 6, characterized in that, The first dielectric layer (110) and the second dielectric layer (130) have the same thickness.

8. The solar cell coating monitoring sheet according to any one of claims 1-4 and 6-7, characterized in that, Both the first surface and the second surface are flat surfaces.

9. The solar cell coating monitoring sheet according to any one of claims 1-4 and 6-7, characterized in that, The semiconductor substrate (100) is a silicon wafer.

10. The solar cell coating monitoring sheet according to any one of claims 1-4 and 6-7, characterized in that, The thickness of the first dielectric layer (110) is 1 nm to 3 nm, and the thickness of the second dielectric layer (130) is 1 nm to 3 nm; and / or, The thickness of the first doped layer (120) is 80nm~130nm, and the thickness of the second doped layer (140) is 80nm~130nm.

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