Pulse width and duty ratio detection device applied to pulse power amplifier

Abstract

The utility model relates to the technical field of radio frequency communication, and discloses a pulse width and duty ratio detection device applied to a pulse power amplifier, which comprises a voltage comparison module, an over-pulse width detection module and an over-duty ratio detection module, the second input end is connected with a reference voltage, and the output end is connected with the over-pulse width detection module and the over-duty ratio detection module respectively; the over-pulse width detection module comprises a first integrating circuit, a summing circuit, a first peak holding circuit and a first voltage comparison circuit which are connected in sequence; and the over-duty ratio detection module comprises a second integrating circuit, an inverting amplification circuit, a second peak holding circuit and a second voltage comparison circuit which are connected in sequence. The pulse width and duty ratio detection device is high in reliability, wide in application range and high in practicability, and can be widely applied to various pulse power amplifiers.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of radio frequency communication technology especially, a pulse width and duty cycle detection device for pulse power amplifier. BACKGROUND

[0002] Pulse amplifier is the most basic and widely used microwave circuit functional unit in radio frequency and microwave system, and the current pulse amplifier tends to develop from single pulse to repeated high-frequency switching power pulse. It is a very important research topic at home and abroad to safely, effectively and detectively output power for solid-state pulse amplifier.

[0003] At present, pulse amplifiers have been widely used in various fields of radio frequency and microwave, but so far, due to the limitation of output power and the risk of such products, the safety is reduced in the use of higher pulse width or higher duty cycle, the difficulty is increased in the product manufacturing process, and due to the characteristics of pulse output power, some solid-state pulse power amplifier devices do not have good detection of pulse width and duty cycle.

[0004] In instrument equipment, the reliability of the product is an important indicator of pulse amplifier, and there is still a lack of simple circuit, low cost and simple design of pulse power amplifier pulse width and duty cycle detection method in the prior art. INVENTION CONTENTS

[0005] In order to solve the above problems, the utility model provides a pulse width and duty cycle detection device for pulse power amplifier, which has high reliability, wide application range and strong practicability, and can be widely applied to various pulse power amplifiers.

[0006] The technical scheme adopted by the utility model is as follows:

[0007] A pulse width and duty cycle detection device for pulse power amplifier, comprising a voltage comparison module, an over-pulse width detection module and an over-duty cycle detection module, the first input end of the voltage comparison module is connected to the detection voltage to be detected, the second input end is connected to the reference voltage, and the output end is connected to the over-pulse width detection module and the over-duty cycle detection module respectively; the over-pulse width detection module comprises a first integration circuit, an addition circuit, a first peak holding circuit and a first voltage comparison circuit connected in sequence; the over-duty cycle detection module comprises a second integration circuit, an inverting amplification circuit, a second peak holding circuit and a second voltage comparison circuit connected in sequence.

[0008] Further, the voltage comparison module comprises a first operational amplifier, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, the non-inverting input terminal of the first operational amplifier is connected with the detection voltage to be detected through the fifth resistor; the inverting input terminal is connected with the second resistor and the third resistor respectively, the second resistor is grounded through the first resistor, and the third resistor is grounded through the first capacitor; the output terminal of the first operational amplifier is connected with the over pulse width detection module through the fourth resistor, and is connected with the over duty cycle detection module through the sixth resistor.

[0009] Further, the first integral circuit comprises a second operational amplifier, a fourteenth capacitor, a thirty-fifth resistor, a thirty-eighth resistor and a forty-third resistor, the non-inverting input terminal of the second operational amplifier is grounded, the inverting input terminal is connected with the voltage comparison module through the thirty-eighth resistor, and the output terminal is connected with the addition circuit through the thirty-fifth resistor, and the output terminal and the inverting input terminal are connected with the parallel connection of the fourteenth capacitor and the forty-third resistor.

[0010] Further, the addition circuit comprises a third operational amplifier, a fortieth resistor, a forty-second resistor and a forty-fourth resistor, the non-inverting input terminal of the third operational amplifier is connected with the first integral circuit, and is connected with the preset voltage through the fortieth resistor, the inverting input terminal is grounded through the forty-fourth resistor, the output terminal is connected with the first peak value holding circuit, and the output terminal and the inverting input terminal are connected with the forty-second resistor.

[0011] Further, the first peak value holding circuit comprises a fourth operational amplifier, a third diode, a fourth diode, a thirty-seventh resistor, a forty-fifth resistor and a fifteenth capacitor, the non-inverting input terminal of the fourth operational amplifier is connected with the addition circuit through the thirty-seventh resistor, the inverting input terminal is connected with the third diode and the forty-fifth resistor respectively, the output terminal is connected with the third diode, the fourth diode, the forty-fifth resistor and the fifteenth capacitor and the first voltage comparison circuit respectively, and the other end of the fifteenth capacitor is grounded.

[0012] Further, the first voltage comparison circuit comprises a fifth operational amplifier, a twelfth capacitor, a thirteenth capacitor, a thirty-second resistor, a thirty-third resistor, a thirty-fourth resistor, a thirty-sixth resistor, a thirty-ninth resistor and a forty-first resistor;

[0013] the non-inverting input terminal of the fifth operational amplifier is connected with the first peak value holding circuit through the forty-first resistor, and is grounded through the thirteenth capacitor;

[0014] the inverting input terminal of the fifth operational amplifier is connected with the thirty-third resistor and the thirty-sixth resistor respectively, the thirty-third resistor is grounded through the thirty-second resistor, and the thirty-sixth resistor is grounded through the twelfth capacitor;

[0015] The output end of the fifth operational amplifier outputs an inverted over pulse width output voltage through a thirty-fourth resistor and outputs a positive over pulse width output voltage through a thirty-ninth resistor.

[0016] Further, the second integration circuit comprises a sixth operational amplifier, a second capacitor, a twentieth resistor, a twenty-first resistor and a twenty-third resistor, the non-inverting input end of the sixth operational amplifier is grounded, the inverting input end is connected with the voltage comparison module through the twenty-first resistor, the output end is connected with the inverting amplification circuit through the twentieth resistor, and the output end and the inverting input end are connected with the second capacitor and the twenty-third resistor in parallel.

[0017] Further, the inverting amplification circuit comprises a seventh operational amplifier, a nineteenth resistor and a twenty-second resistor, the non-inverting input end of the seventh operational amplifier is grounded, the inverting input end is connected with the output end through the twenty-second resistor, and the output end is connected with the second peak value holding circuit through the nineteenth resistor.

[0018] Further, the second peak value holding circuit comprises an eighth operational amplifier, a first diode, a second diode, a twenty-eighth resistor, a thirty-first resistor and an eleventh capacitor, the non-inverting input end of the eighth operational amplifier is connected with the inverting amplification circuit through the twenty-eighth resistor, the inverting input end is connected with the first diode and the thirty-first resistor respectively, and the output end is connected with the first diode, the second diode, the thirty-first resistor, the eleventh capacitor and the second voltage comparison circuit respectively, and the other end of the eleventh capacitor is grounded.

[0019] Further, the second voltage comparison circuit comprises a ninth operational amplifier, a third capacitor, a tenth capacitor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-ninth resistor and a thirtieth resistor.

[0020] The non-inverting input end of the ninth operational amplifier is connected with the second peak value holding circuit through the thirtieth resistor and is grounded through the tenth capacitor.

[0021] The inverting input end of the ninth operational amplifier is connected with the twenty-fifth resistor and the twenty-seventh resistor respectively, the twenty-fifth resistor is grounded through the twenty-fourth resistor, and the twenty-seventh resistor is grounded through the third capacitor.

[0022] The output end of the ninth operational amplifier outputs an inverted over pulse width output voltage through the twenty-sixth resistor and outputs a positive over pulse width output voltage through the twenty-ninth resistor.

[0023] The utility model discloses the beneficial effect lies in:

[0024] The utility model provides a pulse width and duty cycle detection device for pulse power amplifier, including voltage comparison module, over pulse width detection module and over duty cycle detection module, wherein over pulse width detection module includes first integration circuit, adding circuit, first peak hold circuit and first voltage comparison circuit connected in proper order, can detect the pulse width of pulse power amplifier signal output, judges whether pulse power amplifier uses in normal pulse width range or not, over duty cycle detection module includes second integration circuit, inverting amplifier circuit, second peak hold circuit and second voltage comparison circuit connected in proper order, can detect the duty cycle of pulse power amplifier signal output, judges whether pulse power amplifier uses in normal duty cycle range or not, the pulse width and duty cycle detection device of the utility model has high reliability, wide application range, strong practicality, can be widely applied to various pulse power amplifiers. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a pulse width and duty cycle detection device principle view for pulse power amplifier of the utility model.

[0026] Figure 2 It is a voltage comparison module circuit principle view of the utility model.

[0027] Figure 3 It is a first integration and addition circuit principle view of the utility model.

[0028] Figure 4 It is a second integration and inverting amplifier circuit principle view of the utility model.

[0029] Figure 5 It is an over pulse width output principle view of the utility model.

[0030] Figure 6 It is an over duty cycle output principle view of the utility model. DETAILED DESCRIPTION

[0031] In order to have more clear understanding of the technical features, purposes and effects of the utility model, the specific implementation mode of the utility model is explained now, it should be understood that the specific implementation examples described here are only used to explain the utility model, and are not used to limit the utility model, namely the described implementation examples are only a part of implementation examples of the utility model, and are not all the implementation examples, based on the implementation examples of the utility model, all other implementation examples obtained by the skilled person in the field without making creative work belong to the scope of protection of the utility model.

[0032] As Figure 1As shown, the embodiment provides a pulse width and duty cycle detection device applied to a pulse power amplifier, comprising a voltage comparison module, an over pulse width detection module and an over duty cycle detection module, the first input end of the voltage comparison module is connected to the detection voltage to be detected, the second input end is connected to the reference voltage, and the output end is connected to the over pulse width detection module and the over duty cycle detection module; the over pulse width detection module comprises a first integration circuit, an addition circuit, a first peak holding circuit and a first voltage comparison circuit connected in sequence; the over duty cycle detection module comprises a second integration circuit, an inverting amplifier circuit, a second peak holding circuit and a second voltage comparison circuit connected in sequence, and the specific description is as follows.

[0033] The voltage comparison module mainly compares the detection voltage and the reference voltage through the operational amplifier and the logic gate, and outputs high level and inverted low level through the operational amplifier and the logic gate when the detection voltage is greater than the reference voltage.

[0034] The first integration circuit and the second integration circuit mainly integrate the output voltage of the voltage comparison module, so as to form a sawtooth waveform.

[0035] The addition circuit mainly applies a fixed value voltage to the sawtooth waveform voltage output by the first integration circuit, and the fixed value voltage can be adjusted according to actual conditions.

[0036] The inverting amplifier circuit mainly inverts the sawtooth waveform output by the second integration circuit, and then amplifies the voltage by a multiple.

[0037] The first peak holding circuit mainly holds the maximum voltage of the sawtooth waveform output by the addition circuit.

[0038] The second peak holding circuit mainly holds the maximum voltage of the sawtooth waveform output by the inverting amplifier circuit.

[0039] The working principle of the pulse width and duty cycle detection device of the embodiment is as follows:

[0040] Over pulse width detection: for the positive voltage output by the voltage comparison module, the sawtooth wave is formed by the first integration circuit, and then the sawtooth wave voltage output size is controlled by the addition circuit, and then the maximum voltage of the sawtooth wave is held by the first peak holding circuit, and finally the voltage is compared with the reference voltage (this reference voltage can be set according to the maximum pulse width output by the peak holding voltage), if it is greater than the reference voltage, it outputs high level, at this time, the detection is over pulse width, otherwise, it is low level.

[0041] Over-duty cycle detection: for the inverse voltage output by the voltage comparison module, the second integral circuit is used for integration to form a sawtooth wave, and then the inverse amplification circuit is used to control the sawtooth wave voltage to change to a positive voltage, and then the second peak holding circuit is used to hold the maximum voltage of the sawtooth wave, and finally the second voltage comparison circuit is used for comparison with the reference voltage (this reference voltage can be set according to the peak holding voltage output by the maximum duty cycle used in actual use), if it is greater than the reference voltage, a high level is output, at this time, the detection is over-duty cycle, otherwise, it is low level.

[0042] It should be noted that when the detection voltage is compared with the reference voltage, a set of positive voltage and a set of inverse voltage are output, and the reference voltage setting method can be set to the detection voltage that will not cause damage to the equipment under the maximum continuous wave power. The actual pulse width and duty cycle of the equipment can be understood by comparing the output positive voltage, and the peak holding output voltage can be controlled by the voltage output size of the adder circuit. The peak holding voltage and the reference voltage need to be controlled within the normal working range of the operational amplifier during the second comparison, and the scheme can be realized. When the peak holding voltage is greater than the reference voltage, it indicates that the pulse width of the equipment exceeds the normal working range, the comparison output voltage is high, and vice versa.

[0043] Correspondingly, the comparison output inverse voltage is compared twice after the second integral circuit, the inverse amplification circuit and the second peak holding circuit, and the reference voltage setting method can be set to the peak holding output voltage when the maximum over-duty cycle of the equipment is used. The peak holding output voltage can be controlled by the multiple of the inverse amplification to control the voltage output size. The peak holding voltage and the reference voltage need to be controlled within the normal working range of the operational amplifier during the second comparison, and the scheme can be realized. When the peak holding voltage is greater than the reference voltage, it indicates that the duty cycle of the equipment exceeds the normal working range, the comparison output voltage is high, and vice versa.

[0044] Preferably, the voltage comparison module comprises a first operational amplifier U1, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, the same phase input end of the first operational amplifier U1 is connected with the detection voltage to be detected through the fifth resistor R5; the inverse input end is connected with the second resistor R2 and the third resistor R3 respectively, the second resistor R2 is grounded through the first resistor R1, and the third resistor R3 is grounded through the first capacitor C1; the output end of the first operational amplifier U1 is connected with the over-pulse width detection module through the fourth resistor R4, and is connected with the over-duty cycle detection module through the sixth resistor R6.

[0045] As Figure 2As shown, resistor R5 buffers the voltage, C1 is the power supply filter capacitor, and resistors R1 and R2 are connected in series and divided by R3 to form a reference voltage. When the detector voltage is higher than the reference voltage, the output is high; otherwise, the output is low. The signal is converted into a square wave signal. The output terminal connected to resistor R4 is the positive phase voltage, and the output terminal connected to resistor R6 is the inverted phase voltage.

[0046] Preferably, the first integrating circuit includes a second operational amplifier U2, a fourteenth capacitor C14, a thirty-fifth resistor R35, a thirty-eighth resistor R38, and a forty-third resistor R43. The non-inverting input terminal of the second operational amplifier U2 is grounded, the inverting input terminal is connected to a voltage comparator module through the thirty-eighth resistor R38, and the output terminal is connected to an adder circuit through the thirty-fifth resistor R35. Furthermore, the fourteenth capacitor C14 and the forty-third resistor R43 are connected in parallel between the output terminal and the inverting input terminal.

[0047] Preferably, the adder circuit includes a third operational amplifier U3, a fortieth resistor R40, a forty-second resistor R42, and a forty-fourth resistor R44. The non-inverting input of the third operational amplifier U3 is connected to a first integrating circuit and is connected to a preset voltage through the fortieth resistor R40. The inverting input is grounded through the forty-fourth resistor R44. The output is connected to a first peak hold circuit, and the forty-second resistor R42 is connected between the output and the inverting input.

[0048] like Figure 3 As shown, the first integrating circuit integrates the positive-phase voltage from the inverting detector. Resistor R38 buffers the voltage, while resistor R43 and capacitor C14 perform the integration. Direct current flows through the resistors, and the energy stored in the capacitors converts the square wave signal into a sawtooth wave. Then, a 5V voltage is connected to resistor R40, which merges with the integrated output voltage and is connected to the positive terminal of the third operational amplifier U3. The negative terminal is connected to resistors R42 and R44, with R44 grounded. Resistor R42 is connected to the output terminal of the third operational amplifier U3, forming a voltage addition operation output. This embodiment changes the voltage output magnitude by adding voltages to the integrated voltage. Furthermore, the longer the high-level duration, the larger the integrated voltage, and thus the larger the voltage output after addition.

[0049] Preferably, the second integrating circuit includes a sixth operational amplifier U6, a second capacitor C2, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-third resistor R23. The non-inverting input terminal of the sixth operational amplifier U6 is grounded, the inverting input terminal is connected to a voltage comparator module through the twenty-first resistor R21, and the output terminal is connected to an inverting amplifier circuit through the twentieth resistor R20. A second capacitor C2 and a twenty-third resistor R23 are connected in parallel between the output terminal and the inverting input terminal.

[0050] Preferably, the inverting amplification circuit comprises a seventh operational amplifier U7, a nineteenth resistor R19 and a twenty-second resistor R22, the non-inverting input of the seventh operational amplifier U7 is grounded, the inverting input is connected to the output through the twenty-second resistor R22, and the output is connected to the second peak value holding circuit through the nineteenth resistor R19.

[0051] As shown in Figure 4 the second integration circuit integrates the inverted and rectified voltage, the resistors R19 and R21 buffer the voltage, the resistor R23 and the capacitor C2 integrate the voltage, and the resistor passes the direct current and the capacitor stores energy, thereby changing the square wave signal into a sawtooth wave. Then, the ratio of the resistor R22 to the resistor R20 multiplied by the negative integral output voltage is equal to the inverted and amplified voltage, the negative voltage is inverted to become a positive voltage, the longer the duration of the high level, the greater the voltage after integration, and the greater the voltage after the inverted and amplified output.

[0052] Preferably, the first peak value holding circuit comprises a fourth operational amplifier U4, a third diode V3, a fourth diode V4, a thirty-seventh resistor R37, a forty-fifth resistor R45 and a fifteenth capacitor C15, the non-inverting input of the fourth operational amplifier U4 is connected to the summing circuit through the thirty-seventh resistor R37, the inverting inputs are respectively connected to the third diode V3 and the forty-fifth resistor R45, the output is respectively connected to the third diode V3, the fourth diode V4, the forty-fifth resistor R45, the fifteenth capacitor C15 and the first voltage comparison circuit, and the other end of the fifteenth capacitor C15 is grounded.

[0053] Preferably, the first voltage comparison circuit comprises a fifth operational amplifier U5, a twelfth capacitor C12, a thirteenth capacitor C13, a thirty-second resistor R32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-sixth resistor R36, a thirty-ninth resistor R39 and a forty-first resistor R41; the non-inverting input of the fifth operational amplifier U5 is connected to the first peak value holding circuit through the forty-first resistor R41 and grounded through the thirteenth capacitor C13; the inverting inputs of the fifth operational amplifier U5 are respectively connected to the thirty-third resistor R33 and the thirty-sixth resistor R36, the thirty-third resistor R33 is grounded through the thirty-second resistor R32, and the thirty-sixth resistor R36 is grounded through the twelfth capacitor C12; the output of the fifth operational amplifier U5 outputs an inverted and over-pulse width output voltage through the thirty-fourth resistor R34 and a positive over-pulse width output voltage through the thirty-ninth resistor R39.

[0054] As shown in Figure 5As shown, the over pulse width protection output needs to peak hold the voltage output by the adding circuit and compare with the voltage. The R37 and R39 resistors buffer the voltage, and the V3 and V4 diodes conduct in one direction; the R45 resistor conducts DC; the C15 capacitor is connected to ground at one end and charges and discharges; the C13 capacitor is connected to ground at one end and filters the ripple signal in the circuit. By using the diode one-way conduction and the capacitor energy storage characteristics, the sawtooth wave output by the adding circuit is changed into a stable maximum voltage output; the C12 is a power filter capacitor, the R32 and R33 are connected in series and divide voltage with the R36 as a reference voltage, which can be set according to the peak hold voltage output by the maximum pulse width actually used. When the peak hold level is higher than the reference voltage, a high level is output, and vice versa, a low level is output, the signal is converted into a square wave signal, and the peak hold voltage here depends on the maximum peak voltage after the addition operation output, and the monitoring of the high and low levels is to monitor whether the device pulse width is out of the normal range, the high level is the over pulse width, and vice versa, the low level is not over pulse width.

[0055] Preferably, the second peak hold circuit comprises an eighth operational amplifier U8, a first diode V1, a second diode V2, a twenty-eighth resistor R28, a thirty-first resistor R31 and an eleventh capacitor C11, the non-inverting input terminal of the eighth operational amplifier U8 is connected to the inverting amplification circuit through the twenty-eighth resistor R28, the inverting input terminal is connected to the first diode V1 and the thirty-first resistor R31 respectively, the output terminal is connected to the first diode V1, the second diode V2, the thirty-first resistor R31 and the eleventh capacitor C11 and the second voltage comparison circuit respectively, and the other end of the eleventh capacitor C11 is connected to ground.

[0056] Preferably, the second voltage comparison circuit comprises a ninth operational amplifier U9, a third capacitor C3, a tenth capacitor C10, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-ninth resistor R29 and a thirtieth resistor R30; the non-inverting input terminal of the ninth operational amplifier U9 is connected to the second peak hold circuit through the thirtieth resistor R30 and connected to ground through the tenth capacitor C10; the inverting input terminal of the ninth operational amplifier U9 is connected to the twenty-fifth resistor R25 and the twenty-seventh resistor R27 respectively, the twenty-fifth resistor R25 is connected to ground through the twenty-fourth resistor R24, and the twenty-seventh resistor R27 is connected to ground through the third capacitor C3; the output terminal of the ninth operational amplifier U9 outputs an inverting over pulse width output voltage through the twenty-sixth resistor R26 and outputs a positive over pulse width output voltage through the twenty-ninth resistor R29.

[0057] As Figure 6As shown, the over-duty cycle protection output needs to perform peak holding and voltage comparison on the voltage output by the inverting amplification circuit. The resistors R28 and R29 serve to buffer the voltage, and the diodes V1 and V2 serve to conduct in one direction; the resistor R31 serves to pass DC, the capacitor C11 serves to charge and discharge, and the capacitor C10 serves to filter out ripple signals in the circuit. By using the one-way conduction of the diodes and the energy storage of the capacitors, the sawtooth wave output by the inverting amplification circuit is changed into a stable maximum voltage value. The capacitor C3 is a power filter capacitor, the resistors R24 and R25 are connected in series and divide a voltage with the resistor R27, serving as a reference voltage. The reference voltage can be set according to the peak holding voltage output by the maximum duty cycle in actual use. When the peak holding voltage is higher than the reference voltage, a high level is output, and vice versa, a low level is output, thereby converting the signal into a square wave signal. Here, the peak holding voltage depends on the maximum peak value of the voltage after the output of the inverting amplification operation, and the monitoring of the high and low levels serves to monitor whether the device duty cycle exceeds the normal range. A high level indicates an over-duty cycle, and vice versa, a low level indicates an under-duty cycle.

[0058] It should be noted that the over-pulse width and over-duty cycle output signals can only be output when the device exceeds the normal working range. The actual working condition of the device can be understood by detecting the voltage at the positive output end of the comparison voltage, and the abnormal feedback output can be used to determine whether the device abnormality is a pulse width abnormality or a duty cycle abnormality.

[0059] The pulse width and duty cycle detection device of the embodiment can be used in a pulse power amplifier. In implementation, the link is designed in the pulse power amplifier used, and the device can well detect the working condition of the pulse power amplifier. The device can be used to protectively interfere with the device according to the detection result, thereby reducing the risk of damage to the device.

[0060] The above only describes preferred embodiments of the present application, and it should be understood that the present application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein by using the above teachings or related technologies or knowledge. Any modification and change made by those skilled in the art without departing from the spirit and scope of the present application shall fall within the protection scope of the claims of the present application. In addition, the terms "first", "second", "third" and the like are only used for distinction and description, and cannot be understood as indicating or implying relative importance.

Claims

1. A pulse width and duty cycle detection device applied to a pulse power amplifier, characterized in that, The voltage comparison module, the over pulse width detection module and the over duty cycle detection module are included, the first input end of the voltage comparison module is connected with the detection voltage to be detected, the second input end is connected with the reference voltage, and the output end is connected with the over pulse width detection module and the over duty cycle detection module respectively; the over pulse width detection module includes the first integral circuit, the addition circuit, the first peak holding circuit and the first voltage comparison circuit connected in sequence; the over duty cycle detection module includes the second integral circuit, the inverting amplifier circuit, the second peak holding circuit and the second voltage comparison circuit connected in sequence.

2. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, characterized in that The voltage comparison module includes the first operational amplifier (U1), the first capacitor (C1), the first resistor (R1), the second resistor (R2), the third resistor (R3), the fourth resistor (R4), the fifth resistor (R5) and the sixth resistor (R6), the same-phase input end of the first operational amplifier (U1) is connected with the detection voltage to be detected through the fifth resistor (R5); the opposite-phase input end is connected with the second resistor (R2) and the third resistor (R3) respectively, the second resistor (R2) is grounded through the first resistor (R1), and the third resistor (R3) is grounded through the first capacitor (C1); the output end of the first operational amplifier (U1) is connected with the over pulse width detection module through the fourth resistor (R4) and connected with the over duty cycle detection module through the sixth resistor (R6).

3. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, characterized in that The first integral circuit includes the second operational amplifier (U2), the fourteenth capacitor (C14), the thirty-fifth resistor (R35), the thirty-eighth resistor (R38) and the forty-third resistor (R43), the same-phase input end of the second operational amplifier (U2) is grounded, the opposite-phase input end is connected with the voltage comparison module through the thirty-eighth resistor (R38), the output end is connected with the addition circuit through the thirty-fifth resistor (R35), and the output end and the opposite-phase input end are connected with the parallel connection of the fourteenth capacitor (C14) and the forty-third resistor (R43).

4. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, characterized in that, The addition circuit includes the third operational amplifier (U3), the fortieth resistor (R40), the forty-second resistor (R42) and the forty-fourth resistor (R44), the same-phase input end of the third operational amplifier (U3) is connected with the first integral circuit and connected with the preset voltage through the fortieth resistor (R40), the opposite-phase input end is grounded through the forty-fourth resistor (R44), the output end is connected with the first peak holding circuit, and the output end and the opposite-phase input end are connected with the forty-second resistor (R42).

5. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, wherein The first peak holding circuit comprises a fourth operational amplifier (U4), a third diode (V3), a fourth diode (V4), a thirty-seventh resistor (R37), a forty-fifth resistor (R45) and a fifteenth capacitor (C15), the non-inverting input terminal of the fourth operational amplifier (U4) is connected to the summing circuit through the thirty-seventh resistor (R37), the inverting input terminal is connected to the third diode (V3) and the forty-fifth resistor (R45) respectively, and the output terminal is connected to the third diode (V3), the fourth diode (V4), the forty-fifth resistor (R45), the fifteenth capacitor (C15) and the first voltage comparison circuit respectively, and the other end of the fifteenth capacitor (C15) is grounded.

6. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, characterized in that The first voltage comparison circuit comprises a fifth operational amplifier (U5), a twelfth capacitor (C12), a thirteenth capacitor (C13), a thirty-second resistor (R32), a thirty-third resistor (R33), a thirty-fourth resistor (R34), a thirty-sixth resistor (R36), a thirty-ninth resistor (R39) and a forty-first resistor (R41); The non-inverting input terminal of the fifth operational amplifier (U5) is connected to the first peak holding circuit through the forty-first resistor (R41) and grounded through the thirteenth capacitor (C13); The inverting input terminal of the fifth operational amplifier (U5) is connected to the thirty-third resistor (R33) and the thirty-sixth resistor (R36) respectively, the thirty-third resistor (R33) is grounded through the thirty-second resistor (R32), and the thirty-sixth resistor (R36) is grounded through the twelfth capacitor (C12); The output terminal of the fifth operational amplifier (U5) outputs the inverting over-pulse width output voltage through the thirty-fourth resistor (R34) and outputs the non-inverting over-pulse width output voltage through the thirty-ninth resistor (R39).

7. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, wherein The second integration circuit comprises a sixth operational amplifier (U6), a second capacitor (C2), a twentieth resistor (R20), a twenty-first resistor (R21) and a twenty-third resistor (R23), the non-inverting input terminal of the sixth operational amplifier (U6) is grounded, the inverting input terminal is connected to the voltage comparison module through the twenty-first resistor (R21), the output terminal is connected to the inverting amplification circuit through the twentieth resistor (R20), and the second capacitor (C2) and the twenty-third resistor (R23) are connected in parallel between the output terminal and the inverting input terminal.

8. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, wherein The inverting amplification circuit comprises a seventh operational amplifier (U7), a nineteenth resistor (R19) and a twenty-second resistor (R22), the non-inverting input terminal of the seventh operational amplifier (U7) is grounded, the inverting input terminal is connected to the output terminal through the twenty-second resistor (R22), and the output terminal is connected to the second peak holding circuit through the nineteenth resistor (R19).

9. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, wherein The second peak holding circuit comprises an eighth operational amplifier (U8), a first diode (V1), a second diode (V2), a twenty-eighth resistor (R28), a thirty-first resistor (R31) and an eleventh capacitor (C11), the non-inverting input terminal of the eighth operational amplifier (U8) is connected to the inverting amplification circuit through the twenty-eighth resistor (R28), the inverting input terminal is connected to the first diode (V1) and the thirty-first resistor (R31) respectively, and the output terminal is connected to the first diode (V1), the second diode (V2), the thirty-first resistor (R31), the eleventh capacitor (C11) and the second voltage comparison circuit respectively, and the other end of the eleventh capacitor (C11) is grounded.

10. The pulse width and duty cycle detection device for use in a pulsed power amplifier according to claim 1, wherein, The second voltage comparison circuit comprises a ninth operational amplifier (U9), a third capacitor (C3), a tenth capacitor (C10), a twenty-fourth resistor (R24), a twenty-fifth resistor (R25), a twenty-sixth resistor (R26), a twenty-seventh resistor (R27), a twenty-ninth resistor (R29) and a thirtieth resistor (R30); The non-inverting input terminal of the ninth operational amplifier (U9) is connected to the second peak holding circuit through the thirtieth resistor (R30) and grounded through the tenth capacitor (C10); The inverting input terminal of the ninth operational amplifier (U9) is connected to the twenty-fifth resistor (R25) and the twenty-seventh resistor (R27) respectively, the twenty-fifth resistor (R25) is grounded through the twenty-fourth resistor (R24), and the twenty-seventh resistor (R27) is grounded through the third capacitor (C3); The output terminal of the ninth operational amplifier (U9) outputs the inverting over-pulse width output voltage through the twenty-sixth resistor (R26) and outputs the non-inverting over-pulse width output voltage through the twenty-ninth resistor (R29).

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