Signal amplitude detection circuit
By combining voltage comparison, amplification, and level conversion modules, along with offset calibration and logic output, the problems of low efficiency and high power consumption in traditional signal amplitude detection circuits are solved, achieving efficient and low-power signal amplitude detection in high-speed data communication.
Patent Information
- Application Number
- CN202520565604.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-03-27
AI Technical Summary
Traditional signal amplitude detection circuits have low conversion efficiency, especially when the single-ended input amplitude is small, they cannot accurately detect it, and they also have high power consumption.
By combining a voltage comparison module, an amplifier circuit module, and a level conversion module, the signal amplitude is effectively detected by comparing the difference with a reference voltage difference. The offset calibration module and the logic output module are used for precise calibration and signal judgment.
It achieves efficient and low-power signal amplitude detection in high-speed data communication, reduces costs, and can accurately determine signal amplitude, thereby reducing the bit error rate.
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Figure CN223912488U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of electronic circuit, in particular to a signal amplitude detection circuit. BACKGROUND
[0002] In the serial communication technology, the higher the data transmission rate is, the greater the signal amplitude attenuation is under the same transmission distance, and thus the lower the signal amplitude received by the receiving end is. The lower the received signal amplitude is, the more likely the error code is caused, thereby causing a higher error code rate. In order to ensure that the error code rate of the received signal at the receiving end can be controlled within a suitable range, it is necessary to ensure the amplitude of the received signal. Therefore, a signal amplitude detection circuit needs to be set at the receiving end to detect the amplitude of the received signal.
[0003] The conventional signal amplitude detection circuit generally uses a diode or the diode characteristics of some devices to convert the differential signal into a single-ended non-polar signal, and then connects another comparator to determine whether the signal amplitude is greater than the set detection threshold. However, the conversion efficiency of this method is low, and correct detection results cannot be obtained when the amplitude of the single-ended input is very small. CONTENT OF THE INVENTION
[0004] The main purpose of the embodiment of the present application is to provide a signal amplitude detection circuit which can effectively detect the amplitude of the signal received by the receiving end, has low power consumption and low cost.
[0005] To achieve the above purpose, the first aspect of the embodiment of the present application provides a signal amplitude detection circuit applied to the receiving end of high-speed data communication for detecting the amplitude of the input signal, which comprises a voltage comparison module, an amplification circuit module and a level conversion module connected in sequence; wherein,
[0006] The voltage comparison module is used for connecting the positive input voltage, the negative input voltage, the positive reference voltage and the negative reference voltage, and is used for comparing the size between the first difference value and the second difference value and outputting the first positive output voltage and the first negative output voltage, wherein the first difference value is the difference between the positive input voltage and the negative input voltage, and the second difference value is the difference between the positive reference voltage and the negative reference voltage.
[0007] In one embodiment of the present application, the amplification circuit module is used for amplifying the first positive output voltage and the first negative output voltage output by the voltage comparison module and outputting the first target positive output voltage and the first target negative output voltage.
[0008] In an embodiment of the present application, the level conversion module is configured to convert the first target positive-phase output voltage and the first target negative-phase output voltage of the current-mode logic into a first CMOS voltage.
[0009] In an embodiment of the present application, the amplification circuit module comprises a plurality of amplification circuits connected in series.
[0010] In an embodiment of the present application, the detection circuit further comprises a mismatch calibration module, a first end of the mismatch calibration module being connected to an output end of a first amplification circuit in the amplification circuit module, and a second end of the mismatch calibration module being connected to an output end of a last amplification circuit in the amplification circuit module.
[0011] In an embodiment of the present application, the mismatch calibration module comprises a mismatch voltage detection and quantization unit and a compensation calibration unit, a first end of the compensation calibration unit being connected to the output end of the first amplification circuit in the amplification circuit module, a second end of the compensation calibration unit being connected to a first end of the mismatch voltage detection and quantization unit, and a second end of the mismatch voltage detection and quantization unit being connected to the output end of the last amplification circuit in the amplification circuit module.
[0012] The mismatch voltage detection and quantization unit is configured to detect a direct current voltage at the output end of the last amplification circuit in the amplification circuit module to determine a mismatch voltage, and to quantize the mismatch voltage.
[0013] The compensation calibration unit is configured to adjust a current source according to the quantized mismatch voltage to offset the mismatch.
[0014] In an embodiment of the present application, the detection circuit further comprises a logic output module, the logic output module being connected to an output end of the level conversion module, and the logic output module being configured to provide a detection time window, and output a first signal when the first CMOS voltage output by the level conversion module is detected to be continuously greater than or equal to a set threshold value in the detection time window.
[0015] In an embodiment of the present application, the logic output module is further configured to output a second signal when a voltage value less than the set threshold value is detected in the first CMOS voltage output by the level conversion module in the detection time window.
[0016] In an embodiment of the present application, the logic output module comprises a counter unit and a D flip-flop unit, a first input terminal of the counter unit is connected to an output terminal of the level conversion module, a second input terminal of the counter unit is used to access a clock signal, an output terminal of the counter unit is connected to a first input terminal of the D flip-flop unit, a second input terminal of the D flip-flop unit is connected to an output terminal of the level conversion module, and an output terminal of the D flip-flop unit is used to output the first signal or the second signal.
[0017] The present application provides a signal amplitude detection circuit, which is applied to a receiving end of high-speed data communication. The detection circuit comprises a voltage comparison module, an amplification circuit module and a level conversion module connected in sequence. The voltage comparison module is used to access a positive input voltage, a negative input voltage, a positive reference voltage and a negative reference voltage. The voltage comparison module is used to compare the size of a first difference value and a second difference value, and output a first positive output voltage and a first negative output voltage. The first difference value is the difference between the positive input voltage and the negative input voltage, and the second difference value is the difference between the positive reference voltage and the negative reference voltage. Thus, without setting a multi-path voltage comparison circuit, the amplitude of the signal received by the receiving end can be effectively and accurately detected. Compared with the scheme of setting a multi-path voltage comparison module to respectively compare the size of the first difference value of the positive input voltage minus the negative input voltage and the second difference value of the positive reference voltage minus the negative reference voltage, and the size of the first difference value of the positive input voltage minus the negative input voltage and the third difference value of the negative reference voltage minus the positive reference voltage, the power consumption is smaller and the cost is lower. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 is a signal transmission diagram in a high-speed circuit system.
[0019] Figure 2 is a first block diagram of a signal amplitude detection circuit provided by an embodiment of the present application.
[0020] Figure 3 is a circuit diagram of a voltage comparison module provided by an embodiment of the present application.
[0021] Figure 4 is a circuit diagram of an amplification circuit provided by an embodiment of the present application.
[0022] Figure 5 is a circuit diagram of a level conversion module provided by an embodiment of the present application.
[0023] Figure 6 is a second block diagram of a signal amplitude detection circuit provided by an embodiment of the present application.
[0024] Figure 7 is a circuit diagram of a mismatch calibration module provided by an embodiment of the present application.
[0025] Figure 8 Figure 3 is a third block diagram of a signal amplitude detection circuit according to an embodiment of the present application.
[0026] Figure 9 Figure 4 is a structural diagram of an output logic module according to an embodiment of the present application. DETAILED DESCRIPTION
[0027] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.
[0028] It should be noted that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a manner different from the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification and claims and the above-described drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.
[0030] In the application of high-speed circuit system, the transmission and reception of data are indispensable. Generally, the receiving end circuit has requirements for the amplitude and common mode point electrical characteristics of the input data / clock, in order to meet the normal operation of the receiving end circuit, otherwise it will lead to the receiving end identifying the wrong data / clock and generating the corresponding error code, which will affect the work of other modules. Among them, the common mode point is mostly generated internally by the receiving end, which will not become a design bottleneck. However, the signal amplitude is basically determined by the front-end transmitter, and since the channel has low-pass characteristics from the frequency domain (determined by the hardware wiring), which will lead to the data / clock amplitude of the receiving end being smaller than that of the transmitting end (as shown in FIG. 1). In order to ensure that the receiving end can obtain stable and electrical characteristic data / clock, the receiving end needs to set a detection circuit for detecting the amplitude of high-speed data / clock, which is used to detect the amplitude of the received signal. Figure 1
[0031] The traditional signal amplitude detection circuit generally uses a diode or the diode characteristics of some devices to convert the differential signal into a single-ended non-polar signal, and then connects another comparator to determine whether the signal amplitude is greater than the set detection threshold. However, the conversion efficiency of this method is relatively low, and at the same time, it cannot obtain correct detection results when the amplitude of the single-ended input is very small.
[0032] Based on this, this application proposes a signal amplitude detection circuit that can effectively detect the amplitude of the signal received by the receiver, and has low power consumption and low cost.
[0033] Reference Figure 2 , Figure 2 This is a first block diagram of a signal amplitude detection circuit according to an embodiment of this application. The detection circuit is located at the receiving end and is used to detect the amplitude of the signal received at the receiving end. Figure 2 As shown, the detection circuit includes a voltage comparison module 110, an amplifier circuit module 120, and a level conversion module 130 connected in sequence. The voltage comparison module 110 is used to receive a positive input voltage vimp, a reverse input voltage vinn, a positive reference voltage vrefp, and a negative reference voltage vrefn. The voltage comparison module 110 compares the magnitude of a first difference (vinp-vinn) and a second difference (vrefp-vrefn), and outputs a first positive-phase output voltage vop_1 and a first negative-phase output voltage von_1. The first difference is the difference between the positive input voltage vimp and the reverse input voltage vinn (i.e., vimp-vinn), and the second difference is the difference between the positive reference voltage vrefp and the negative reference voltage vrefn (i.e., vrefp-vrefn). The amplifier circuit module 120 includes multiple amplifier circuits connected in series.
[0034] In this embodiment, the voltage comparison module 110 compares the magnitude of the first difference (vinp-vinn), i.e., the differential signal and the second difference (vrefp-vrefn). Considering that if the negative portion of the differential signal is greater than the threshold (vrefp-vrefn), then the negative portion of the differential signal must also be greater than the threshold (vrefp-vrefn), this application effectively and accurately detects the amplitude of the input signal by setting the voltage comparison module 110 to only compare whether the first difference (vinp-vinn) is greater than the second difference (vrefp-vrefn). Compared to a scheme that requires setting multiple voltage comparison modules to separately compare the magnitudes of the first difference (positive input voltage minus reverse input voltage) and the second difference (positive reference voltage minus negative reference voltage), and the third difference (positive input voltage minus reverse input voltage minus the third reference voltage), this method consumes less power and has a lower cost.
[0035] Reference Figure 3 , Figure 3 This is a circuit diagram of a voltage comparison module provided in one embodiment of this application. Figure 3As shown, the voltage comparison module 110 includes a first differential pair transistor structure, a second differential pair transistor structure, a first resistor R1, a second resistor R2 and a current source I. The first differential pair transistor structure includes a first transistor Q1 and a second transistor Q2. The base of the first transistor Q1 is used to input a positive input voltage v in p. The emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, and then connected to the current source I, and the current source I is grounded. The collector of the first transistor Q1 is connected to the collector of the second transistor Q2, and then connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to input a power supply voltage VDD. The base of the second transistor Q2 is used to input a negative reference voltage v ref n. Similarly, the second differential pair transistor structure includes a third transistor Q3 and a fourth transistor Q4. The base of the third transistor Q3 is used to input a positive reference voltage v ref p, and the emitter of the third transistor Q3 is connected to the emitter of the fourth transistor Q4, and then connected to the current source I. The collector of the third transistor Q3 is connected to the collector of the fourth transistor Q4, and then connected to the first end of the second resistor R2, and the second end of the second resistor R2 is used to input the power supply voltage VDD. The base of the fourth transistor Q4 is used to input a reverse input voltage v in n. The second end of the first resistor R1 is also used to output a first negative phase output voltage v on _1, and the second end of the second resistor R2 is also used to output a first positive phase output voltage v op _1.
[0036] In the embodiment of the present application, the emitter of the first transistor Q1, the emitter of the second transistor Q2, the emitter of the third transistor Q3 and the emitter of the fourth transistor Q4 are connected, and share a current source I bias. The differential pair transistor structure is composed of two opposite working transistors. The differential pair transistor structure uses the common mode rejection capability of the two transistors, so that when the input signal has common mode interference, the output signal can still remain stable. That is, by using the differential pair transistor structure, the differential amplification and common mode rejection are realized at the same time, which can effectively resist the influence of noise and interference signals.
[0037] In the embodiment of the present application, the amplification circuit module 120 is used to amplify the first positive phase output voltage v op _1 and the first negative phase output voltage v on _1 outputted and output a first target positive phase output voltage v op _1 n and a first target negative phase output voltage v on _1 n. Specifically, the amplification circuit module 120 can be used to amplify the differential signal and suppress the common mode interference. Specifically, the amplification circuit module 120 can decompose two input signals into a differential mode component (effective signal) and a common mode component (noise or interference). The differential mode component can be amplified by the amplification circuit gain, and the common mode component can be weakened by the symmetry of the circuit and the negative feedback mechanism.
[0038] Referring to Figure 4 , Figure 4 is a circuit diagram of an amplification circuit provided by an embodiment of the present application.Figure 4 As shown, the amplification circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2 and a current source I. The base of the first transistor Q1 is used to access the first positive phase output voltage vop_1 output by the first voltage comparison module 110, and the base of the second transistor Q2 is used to access the first negative phase output voltage von_1 output by the first voltage comparison module. The emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, and the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected to the current source I, and the current source I is grounded. The collector of the first transistor Q1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is used to connect the power supply voltage VDD. The collector of the second transistor Q2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is used to connect the power supply voltage VDD. The second end of the first resistor R1 is also used to output the amplified negative phase output voltage von_12, and the second end of the second resistor R2 is also used to output the amplified positive phase output voltage vop_12.
[0039] In the embodiment of the present application, the level conversion module 130 is used to convert the first target positive phase output voltage vop_1n and the first target negative phase output voltage von_1n of the current mode logic into the first CMOS voltage. The level conversion module 130 can include an operational amplifier and a level shift circuit. The operational amplifier receives the differential signal (including the first target positive phase output voltage vop_1n and the first target negative phase output voltage von_1n) output by the amplification circuit module 120. Since the current mode logic (CML) output swing is small (usually a few hundred mV), it needs to be amplified to the CMOS logic level (such as 0V to 3.3V or 5V) by a high-gain operational amplifier. The gain of the operational amplifier needs to be adjusted according to the CMOS input threshold to ensure that the output covers the full swing. The unit gain bandwidth of the operational amplifier needs to be higher than the highest frequency of the signal to avoid distortion. For example, if the CML signal frequency is 100MHz, the operational amplifier bandwidth should be greater than this value, and the closed-loop stability needs to be considered to avoid oscillation due to insufficient phase margin. The CMOS level is usually referenced to ground, while the CML differential signal can contain a common-mode voltage. The common-mode voltage needs to be adjusted to the CMOS input range by the level shift circuit, and the common-mode noise needs to be suppressed. For example, a resistor divider or a dedicated level conversion IC can be used.
[0040] In some embodiments, a CMOS buffer (such as an inverter chain) can also be added after the operational amplifier to enhance the driving capability and shape the output waveform, and to ensure that the rise / fall time meets the requirements of the CMOS interface.
[0041] Reference Figure 5 , Figure 5 is a circuit diagram of a level conversion module provided by an embodiment of the present application. The level conversion module 130 includes an operational amplifier OP1 and a level shift circuit LS1. Figure 5As shown, the level conversion module 130 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8 and a current source I. The base of the first transistor Q1 is connected with the base of the second transistor Q2, and the base of the first transistor Q1 is also connected with the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected with the collector of the third transistor Q3, the base of the third transistor Q3 is connected with the base of the fourth transistor Q4, the base of the fourth transistor Q4 is connected with the collector of the fourth transistor Q4, and then the collector of the fifth transistor Q5, the base of the fifth transistor Q5 is used to input the first target positive phase output voltage vop_1n, the emitter of the fifth transistor Q5 is connected with the emitter of the sixth transistor Q6, and then connected to the current source I, and the current source I is grounded. The base of the sixth transistor Q6 is used to input the first target negative phase output voltage von_1n, the collector of the sixth transistor Q6 is connected with the collector of the seventh transistor Q7, the base of the seventh transistor Q7 is connected with the collector of the seventh transistor Q7, the base of the seventh transistor Q7 is also connected with the base of the eighth transistor Q8, the collector of the eighth transistor Q8 is connected with the collector of the second transistor Q2, and the emitter of the second transistor Q2 is grounded. The emitter of the third transistor Q3, the emitter of the fourth transistor Q4, the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8 are connected and input to the power supply voltage VDD. The first CMOS voltage is output between the collector of the second transistor Q2 and the collector of the eighth transistor Q8. The size of the first CMOS voltage output by the level conversion module 130 can determine the size of the signal amplitude received by the receiving end.
[0042] In some embodiments, with reference to Figure 6 , Figure 6 is a second block diagram of a signal amplitude detection circuit provided by an embodiment of the present application. The detection circuit is arranged at the receiving end, and is used to detect the amplitude of the signal received by the receiving end. As shown in Figure 6 , the detection circuit includes a voltage comparison module 110, an amplification circuit module 120, a level conversion module 130 and a offset calibration module 140 connected in sequence. The amplification circuit module 120 includes a plurality of amplification circuits connected in series. The first end of the offset calibration module 140 is connected with the output end of the first amplification circuit in the amplification circuit module 120, and the second end of the offset calibration module 140 is connected with the output end of the last amplification circuit in the amplification circuit module 120.
[0043] The voltage comparison module 110 is configured to access the forward input voltage vinp, the reverse input voltage vinn, the positive reference voltage vrefp and the negative reference voltage vrefn, compare the first difference (vinp-vinn) and the second difference (vrefp-vrefn) and output the first positive output voltage vop_1 and the first negative output voltage von_1. The first difference is the difference between the forward input voltage vinp and the reverse input voltage vinn, and the second difference is the difference between the positive reference voltage vrefp and the negative reference voltage vrefn.
[0044] The mismatch calibration module 140 can achieve signal accuracy optimization by detecting the mismatch error and dynamically compensating based on a closed-loop feedback adjustment mechanism. Specifically, referring to Figure 7 , Figure 7 is a circuit diagram of the mismatch calibration module provided in an embodiment of the present application. The mismatch calibration module 140 can include a mismatch voltage detection and quantization unit 141 and a compensation calibration unit 142. The first end of the compensation calibration unit 142 is connected to the output end of the first amplifier circuit in the amplifier circuit module 120. The second end of the compensation calibration unit 142 is connected to the first end of the mismatch voltage detection and quantization unit 141, and the second end of the mismatch voltage detection and quantization unit 141 is connected to the output end of the last amplifier circuit in the amplifier circuit module 120. The mismatch voltage detection and quantization unit 141 is configured to detect the DC voltage at the output end of the last amplifier circuit in the amplifier circuit module 120 to determine the mismatch voltage and quantize the mismatch voltage. The compensation calibration unit 142 is configured to adjust the current source according to the quantized mismatch voltage to offset the mismatch. Specifically, the mismatch voltage detection and quantization unit 141 can input a fixed common-mode voltage to the differential input end in the calibration mode to force the output end to present a theoretical balance state. The actual output and the ideal value are quantized by comparing the differential output end voltage difference in real time. The compensation calibration unit 142 can be configured to inject a compensation current into the differential branch through a calibration current generation module when the input mismatch voltage is detected, adjust the transistor operating point to offset the initial mismatch, and generate a digital control code according to the comparison result through a logic unit to drive the DAC to output a corresponding analog trimming signal, forming a closed-loop negative feedback. By adjusting the current ratio of the differential branch mirror current source, the transconductance parameter of the input pair transistor is changed to fine-tune the mismatch voltage. Thus, through continuous calibration of the mismatch calibration module, the influence of temperature drift on the mismatch change can be avoided.
[0045] In the embodiment of the present application, considering that the amplification circuit module 120 is composed of multiple amplification circuits in cascade, and the offset voltage of each amplification circuit will generate deviation at the output end, when cascaded, these deviations will be amplified by the subsequent amplifiers, resulting in cumulative effect. That is, the input offset voltage of each amplification circuit itself will be amplified with gain step by step, and superimposed at the output end. The offset voltage of the previous stage amplification circuit will be considered as the effective input signal by the subsequent amplifier for secondary amplification, resulting in significant increase of the overall system offset. At the same time, the transistor threshold voltage, transconductance and other parameters of the input stage of each amplification circuit will drift with temperature change. The temperature environment of each stage of the cascade system may be different, resulting in superposition of temperature drift error among multiple stages. For this, the embodiment of the present application proposes an offset calibration module 140, which can continuously calibrate the offset generated in the amplification circuit module 120, thereby effectively reducing the offset in the circuit.
[0046] In some embodiments, with reference to Figure 8 , Figure 8 is a third block diagram of a signal amplitude detection circuit provided by an embodiment of the present application. The detection circuit is arranged at the receiving end, and is used for detecting the amplitude of the signal received by the receiving end. As shown in Figure 8 , the detection circuit includes a voltage comparison module 110, an amplification circuit module 120, a level conversion module 130, an offset calibration module 140 and a logic output module 150 connected in sequence. The amplification circuit module 120 includes multiple amplification circuits connected in series. The first end of the offset calibration module 140 is connected to the output end of the first amplification circuit in the amplification circuit module 120, and the second end of the offset calibration module 140 is connected to the output end of the last amplification circuit in the amplification circuit module 120. The logic output module 150 is connected to the output end of the level conversion module 130. The logic output module 150 is used for providing a detection time window, and outputting a first signal SIG when it is detected that the first COMS voltage output by the level conversion module 130 is continuously greater than or equal to the set threshold value in the detection time window; and outputting a second signal SIG when it is detected that there is a voltage value less than the set threshold value in the first COMS voltage output by the level conversion module 130 in the detection time window.
[0047] Specifically, with reference to Figure 9 , Figure 9 is a structural schematic diagram of an output logic module provided by an embodiment of the present application. As shown in Figure 9As shown, the logic output module 150 includes a counter unit 151 and a D flip-flop unit 152. The first input terminal of the counter unit 151 is connected to the output terminal of the level conversion module 130, the second input terminal of the counter unit 151 is used to access the clock signal CKIN, the output terminal of the counter unit 151 is connected to the first input terminal of the D flip-flop unit 152, the second input terminal of the D flip-flop unit 152 is connected to the output terminal of the level conversion module 130, and the output terminal of the D flip-flop unit 152 is used to output the first signal or the second signal. In the embodiment of the present application, in the detection time window T, the overall circuit will output a signal present signal to the analog / digital circuit for the next operation only when the amplitude of the data / clock continuously exceeds the preset detection threshold in the detection time window T. In the detection time window T, as long as the amplitude of the data / clock is less than the detection threshold, the output signal will become signal lost. The output signal lost signal represents that the signal amplitude received at the receiving end is unqualified, which can cause the subsequent circuit to fail to normally identify the lower value of the signal and needs to guide the subsequent circuit to perform corresponding processing.
[0048] In the embodiment of the present application, by setting the logic output module 150, the signal amplitude continuously exceeding the threshold in the continuous detection time window T can filter the pulse type noise or short time interference, and avoid mis-triggering the subsequent circuit; at the same time, using continuous detection instead of single sampling can ensure that the signal state transition only occurs under stable conditions, and avoid logic errors caused by metastable state.
[0049] In the embodiment of the present application, by designing the voltage comparison module and comparing the size of the first difference (the positive input voltage minus the negative input voltage) and the second difference (the positive reference voltage minus the negative reference voltage), without setting a multi-voltage comparison circuit, the signal amplitude received at the receiving end can be effectively detected, and compared with the scheme of setting a multi-voltage comparison module to respectively compare the size of the first difference (the positive input voltage minus the negative input voltage) and the second difference (the positive reference voltage minus the negative reference voltage), and the size of the third difference (the positive input voltage minus the negative input voltage) and the negative reference voltage minus the positive reference voltage), the power consumption is smaller, and the cost is lower.
[0050] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the embodiments of the present application.
Claims
1. A signal amplitude detection circuit applied to a receiving end of high-speed data communication, for detecting the amplitude of an input signal, characterized in that, The detection circuit comprises a voltage comparison module, an amplification circuit module and a level conversion module connected in sequence. The voltage comparison module is configured to input a forward input voltage, a reverse input voltage, a positive reference voltage and a negative reference voltage, compare a first difference value with a second difference value, and output a first positive-phase output voltage and a first negative-phase output voltage, wherein the first difference value is a difference between the forward input voltage and the reverse input voltage, and the second difference value is a difference between the positive reference voltage and the negative reference voltage.
2. The detection circuit of claim 1, wherein, The amplification circuit module is configured to amplify the first positive-phase output voltage and the first negative-phase output voltage output by the voltage comparison module, and output a first target positive-phase output voltage and a first target negative-phase output voltage.
3. The detection circuit of claim 2, wherein, The level conversion module is configured to convert the first target positive-phase output voltage and the first target negative-phase output voltage of the current mode logic into a first CMOS voltage.
4. The detection circuit of claim 1, wherein, The amplification circuit module comprises a plurality of amplification circuits connected in sequence.
5. The detection circuit of claim 4, wherein, The detection circuit further comprises a first end of an offset calibration module connected to an output end of a first amplification circuit in the amplification circuit module, and a second end of the offset calibration module connected to an output end of a last amplification circuit in the amplification circuit module.
6. The detection circuit of claim 5, wherein, The offset calibration module comprises an offset voltage detection and quantization unit and a compensation calibration unit, a first end of the compensation calibration unit is connected to the output end of the first amplification circuit in the amplification circuit module, a second end of the compensation calibration unit is connected to a first end of the offset voltage detection and quantization unit, and a second end of the offset voltage detection and quantization unit is connected to the output end of the last amplification circuit in the amplification circuit module. The offset voltage detection and quantization unit is configured to detect a direct current voltage of the output end of the last amplification circuit in the amplification circuit module, determine an offset voltage, and quantize the offset voltage. The compensation calibration unit is configured to adjust a current source according to the quantized offset voltage to offset the offset.
7. The detection circuit of claim 1, wherein, The detection circuit further comprises a logic output module connected to an output end of the level conversion module, the logic output module is configured to provide a detection time window, and output a first signal when the first CMOS voltage output by the level conversion module is detected to be continuously greater than or equal to a set threshold value in the detection time window.
8. The detection circuit of claim 7, wherein, The logic output module is further configured to output a second signal when a voltage value less than the set threshold value is detected in the first CMOS voltage output by the level conversion module in the detection time window.
9. The detection circuit according to claim 7 or 8, characterized in that, The logic output module comprises a counter unit and a D flip-flop unit, a first input end of the counter unit is connected to the output end of the level conversion module, a second input end of the counter unit is configured to input a clock signal, an output end of the counter unit is connected to a first input end of the D flip-flop unit, a second input end of the D flip-flop unit is connected to the output end of the level conversion module, and an output end of the D flip-flop unit is configured to output the first signal or the second signal.