Trench MOS device

Abstract

The utility model discloses a groove MOS (Metal Oxide Semiconductor) device, which comprises a P-type base region positioned at the upper part of a silicon wafer and a heavily doped N-type drain region positioned at the lower part of the silicon wafer, and an N-type epitaxial region is arranged between the P-type base region and the heavily doped N-type drain region; a trench located in the P-type base region extends into the N-type epitaxial region from the upper surface of the P-type base region, and an insulating dielectric layer covers the upper surface of the trench and extends to the peripheral region of the trench; a heavily doped N-type source region is arranged in the upper part of the P-type base region and is positioned on the periphery of the groove; the middle part of the grid electrode part is provided with an outer convex part, the upper end surface of the outer convex part in the vertical direction is positioned between the lower surface of the heavily doped N-type source electrode region and the lower surface of the P-type base electrode region, and the lower end surface of the outer convex part is positioned below the P-type base electrode region. According to the trench MOS device, the electric field at the junction of the heavily doped N-type source region and the P-type base region is improved, and the resistance of the MOS device during forward conduction can be remarkably reduced, so that the loss of the device during normal operation is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to MOS device technical field especially relates to a trench MOS device. BACKGROUND

[0002] MOS device is indispensable electronic device of electronic system, and it is mainly applied to various power supply and drive load. With the replacement of power semiconductor device, new power semiconductor device gradually develops towards the realization of energy saving, material saving, environmental protection and miniaturization and other benefits. The existing MOS device has large loss when conducting in positive direction, and how to improve it becomes the direction of efforts of the technical personnel in the field. SUMMARY

[0003] The utility model discloses a kind of trench MOS devices, the electric field of the intersection of heavily doped N-type source region and P-type base region is improved, it is favorable to significantly reduce the resistance when MOS device conducts in positive direction, to reduce the loss when device works normally.

[0004] To achieve the above object, the utility model adopts the technical scheme of: a kind of trench MOS device, comprising: P-type base region located in the upper portion of silicon wafer and heavily doped N-type drain region located in the lower portion of silicon wafer, N-type epitaxial region is arranged between the P-type base region and heavily doped N-type drain region;

[0005] One located in P-type base region groove extends to N-type epitaxial region from P-type base region upper surface, an insulating dielectric layer covers on the upper surface of groove and extends to the peripheral region of groove;One upper metal layer covers on P-type base region and the upper surface of insulating dielectric layer, a lower metal layer is located on the surface opposite to N-type epitaxial region of heavily doped N-type drain region;

[0006] The upper portion of P-type base region and located in the periphery of groove has heavily doped N-type source region, the gate portion has in the groove, and the gate portion is filled with gate oxide layer between the gate portion and groove;

[0007] The middle part of the gate portion has an outer convex part, the upper end surface of the outer convex part is located between the lower surface of heavily doped N-type source region and the lower surface of P-type base region in vertical direction, and the lower end surface of the outer convex part is located below P-type base region.

[0008] The further improved scheme in the above technical solution is as follows:

[0009] 1、In the above scheme, the lower end of the groove extends to the lower portion of N-type epitaxial region.

[0010] 2、In the above scheme, the insulating dielectric layer covers above the inner side edge of heavily doped N-type source region.

[0011] 3. According to the scheme, the depth of the trench is 2-4 times the depth of the P-type base region.

[0012] 4. According to the scheme, the insulating medium layer is a silicon dioxide layer.

[0013] Compared with the prior art, the trench MOS device has the following advantages:

[0014] The trench MOS device has a gate portion in the trench, the gate portion and the trench are filled with a gate oxide layer, the middle portion of the gate portion has an outward protruding portion, the upper end surface of the outward protruding portion is located between the lower surface of the heavily doped N-type source region and the lower surface of the P-type base region in the vertical direction, and the lower end surface of the outward protruding portion is located below the P-type base region. The electric field at the junction of the heavily doped N-type source region and the P-type base region is improved, which is conducive to significantly reducing the resistance of the MOS device when it is turned on in the forward direction, thereby reducing the loss of the device when it is normally working. BRIEF DESCRIPTION OF DRAWINGS

[0015] ATTACHMENT Figure 1 The figure is a structural schematic diagram of the trench MOS device.

[0016] In the above drawings: 1, silicon wafer; 2, P-type base region; 3, heavily doped N-type drain region; 4, N-type epitaxial region; 5, trench; 6, insulating medium layer; 7, upper metal layer; 8, lower metal layer; 9, gate portion; 10, gate oxide layer; 11, outward protruding portion; 12, heavily doped N-type source region. DETAILED DESCRIPTION

[0017] The specific embodiments given below can further clearly understand the patent, but they are not a limitation of the patent.

[0018] Embodiment 1: A trench MOS device, comprising: a P-type base region 2 located on the upper part of a silicon wafer 1 and a heavily doped N-type drain region 3 located on the lower part of the silicon wafer 1, an N-type epitaxial region 4 is arranged between the P-type base region 2 and the heavily doped N-type drain region 3;

[0019] A trench 5 located in the P-type base region 2 extends from the upper surface of the P-type base region 2 to the N-type epitaxial region 4, an insulating medium layer 6 covers the upper surface of the trench 5 and extends to the peripheral region of the trench 5; an upper metal layer 7 covers the upper surface of the P-type base region 2 and the insulating medium layer 6, and a lower metal layer 8 is located on the surface opposite to the N-type epitaxial region 4 of the heavily doped N-type drain region 3;

[0020] The P-type base region 2 has a heavily doped N-type source region 12 in the upper part and located in the peripheral region of the trench 5, the trench 5 has a gate portion 9, and the gate portion 9 and the trench 5 are filled with a gate oxide layer 10;

[0021] The middle part of the gate part 9 has an outward protruding part 11, the upper end surface of which in the vertical direction is located between the lower surface of the heavily doped N-type source region 12 and the lower surface of the P-type base region 2, and the lower end surface of which is located below the P-type base region 2.

[0022] The lower end of the trench 5 extends to the lower part of the N-type epitaxial region 4.

[0023] The insulating medium layer 6 covers the upper side of the inner edge of the heavily doped N-type source region 12.

[0024] The depth of the trench is 2.5 times the depth of the P-type base region 2.

[0025] Embodiment 2: A trench MOS device, comprising: a P-type base region 2 located on the upper part of a silicon wafer 1 and a heavily doped N-type drain region 3 located on the lower part of the silicon wafer 1, with an N-type epitaxial region 4 arranged between the P-type base region 2 and the heavily doped N-type drain region 3;

[0026] A trench 5 located in the P-type base region 2 extends from the upper surface of the P-type base region 2 to the N-type epitaxial region 4, an insulating medium layer 6 covers the upper surface of the trench 5 and extends to the peripheral area of the trench 5, an upper metal layer 7 covers the upper surface of the P-type base region 2 and the insulating medium layer 6, and a lower metal layer 8 is located on the surface of the heavily doped N-type drain region 3 opposite to the N-type epitaxial region 4;

[0027] The P-type base region 2 has a heavily doped N-type source region 12 in the upper part thereof and located in the periphery of the trench 5, the trench 5 has a gate part 9, and the gate part 9 is filled with a gate oxide layer 10 between the trench 5.

[0028] The middle part of the gate part 9 has an outward protruding part 11, the upper end surface of which in the vertical direction is located between the lower surface of the heavily doped N-type source region 12 and the lower surface of the P-type base region 2, and the lower end surface of which is located below the P-type base region 2.

[0029] The lower end of the trench 5 extends to the lower part of the N-type epitaxial region 4, and the insulating medium layer 6 covers the upper side of the inner edge of the heavily doped N-type source region 12.

[0030] The depth of the trench is 3.2 times the depth of the P-type base region 2.

[0031] The insulating medium layer 6 is a silicon dioxide layer.

[0032] When the trench MOS device is used, the trench 5 has a gate portion 9 in the trench 5, a gate oxide layer 10 is filled between the gate portion 9 and the trench 5, the middle portion of the gate portion 9 has an outward protruding portion 11, the upper end surface of the outward protruding portion 11 is located between the lower surface of the heavily doped N-type source region 12 and the lower surface of the P-type base region 2 in the vertical direction, and the lower end surface of the outward protruding portion 11 is located below the P-type base region 2; the electric field at the junction of the heavily doped N-type source region and the P-type base region is improved, which is beneficial to significantly reduce the resistance of the MOS device when it is turned on in the forward direction, thereby reducing the loss of the device when it is normally working.

[0033] The above examples are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and essence of the present application shall be covered within the protection scope of the present application.

Claims

1. A trench MOS device, characterized by: The application relates to a silicon chip (1) comprising: a P-type base region (2) on the upper part of the silicon chip (1) and a heavily doped N-type drain region (3) on the lower part of the silicon chip (1), wherein an N-type epitaxial region (4) is arranged between the P-type base region (2) and the heavily doped N-type drain region (3); a trench (5) in the P-type base region (2) extending from the upper surface of the P-type base region (2) into the N-type epitaxial region (4), an insulating dielectric layer (6) covering the upper surface of the trench (5) and extending to the peripheral region of the trench (5), an upper metal layer (7) covering the upper surface of the P-type base region (2) and the insulating dielectric layer (6), and a lower metal layer (8) arranged on the surface of the heavily doped N-type drain region (3) opposite to the N-type epitaxial region (4); a heavily doped N-type source region (12) is arranged in the upper part of the P-type base region (2) and in the peripheral region of the trench (5), a gate portion (9) is arranged in the trench (5), and a gate oxide layer (10) is arranged between the gate portion (9) and the trench (5); the middle part of the gate portion (9) is provided with a convex portion (11), the upper end surface of the convex portion (11) is arranged between the lower surface of the heavily doped N-type source region (12) and the lower surface of the P-type base region (2) in the vertical direction, and the lower end surface of the convex portion (11) is arranged below the P-type base region (2).

2. The trench MOS device of claim 1, wherein: the lower end of the trench (5) extends to the lower part of the N-type epitaxial region (4).

3. The trench MOS device of claim 1, wherein: the insulating dielectric layer (6) covers the upper part of the inner side edge of the heavily doped N-type source region (12).

4. The trench MOS device of claim 1, wherein: the depth of the trench is 2-4 times the depth of the P-type base region (2).

5. The trench MOS device of claim 1, wherein: the insulating dielectric layer (6) is a silicon dioxide layer.

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