Chip electrostatic protection structure
By designing a two-level protection chip electrostatic protection structure, using a combination of resistors and MOS transistors, and utilizing six-terminal devices and shallow trench isolation technology, the contradiction between the electrostatic protection effect and chip area occupancy in existing technologies has been resolved, achieving a combination of high-voltage ESD protection reliability and low footprint.
Patent Information
- Application Number
- CN202423253333.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-28
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2034-12-28
AI Technical Summary
Existing technologies struggle to effectively reduce chip area while ensuring electrostatic protection, and the reliability of high-voltage ESD structures is insufficient.
A chip electrostatic discharge (ESD) protection structure was designed, which adopts a two-level protection mode, including a combination of resistors and MOS transistors. The isolation effect is increased by using the MOS transistors of six-terminal devices, and the layout is optimized by shallow trench isolation technology to ensure high voltage ESD protection capability.
It achieves reduced chip area while ensuring electrostatic protection effectiveness, and can achieve reliability of over 2KV in high-voltage ESD protection mode.
Smart Images
Figure CN223912802U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit technical field, concretely relates to a chip static protection structure. BACKGROUND
[0002] Electrostatic discharge (ESD: Electrostatic Discharge) is the main culprit of the excessive electric stress damage of all electronic components or integrated circuit systems. In nature, static electricity is usually very high (at least several thousand volts or more) instantaneous voltage, and the damage of static electricity to integrated circuits, especially deep submicron electronic components, is devastating and permanent, and severe can cause direct damage to the circuit, so preventing static damage is the top priority and the top problem for all chip manufacturers and IC design companies.
[0003] In the process, as the device size becomes smaller and smaller, the junction depth becomes shallower and shallower, and the gate oxide layer becomes thinner and thinner, so the electrostatic breakdown becomes easier and easier, and almost all chip electrostatic breakdown problems need to rely on chip design to complete.
[0004] Therefore, a high-voltage ESD structure with high reliability is needed. SUMMARY
[0005] The utility model discloses to solve the reliability problem of ESD structure, provide a chip static protection structure, both based on the process of wafer foundry, and can meet the actual size needs of chip and the need of static protection, on the basis of guaranteeing the static protection effect, reduce the occupation of chip area, can realize HBM static protection mode 2KV above.
[0006] The utility model provides a chip static protection structure, including the resistance R1 that one end is connected with PAD layer, the other end is connected with the protected device, the MOS transistor I2 that drain electrode is connected between resistance R1 and protected device, the gate electrode is connected with the source electrode and then ground, the MOS transistor I1 that drain electrode is connected between resistance R1 and PAD layer, the source electrode is connected with the source electrode of pipe I1 and then ground and the resistance R2 that one end is connected with the gate electrode of pipe I1, the other end is connected with the source electrode of pipe I1 and then ground,
[0007] The size of pipe I2 is less than pipe I1, and the drain electrode width of pipe I1 and pipe I2 is all 8um or more, and the resistance value of resistance R1 and resistance R2 is same.
[0008] As a preferred mode, the utility model discloses a chip static protection structure, pipe I1 and pipe I2 structure are same, and all are six-terminal devices, and pipe I1 and pipe I2 all include gate electrode, source electrode, drain electrode, substrate, deep N well and P well.
[0009] The P well of pipe I1 is connected with the source electrode and then grounded, the deep N well is connected with power voltage VDD, and the substrate is connected with the source electrode and the gate electrode and then grounded.
[0010] The P well of the pipe I2 is connected with the source electrode and grounded, the deep N well is connected with the deep N well of the pipe I1 and connected with the power voltage VDD, and the substrate is connected with the source electrode and the gate electrode and grounded.
[0011] As the preferred mode, the P well of the pipe I1 and the substrate have the same potential and are P-type semiconductors, the deep N well is N-type semiconductor, and the deep N well and the P well and the substrate form two reverse PN junction diodes.
[0012] As the preferred mode, the both sides of the P well, the both sides of the deep N well and the both sides of the substrate are subjected to shallow trench isolation, the shallow trench isolation is performed between the P well and the source electrode, the shallow trench isolation is performed between the deep N well and the drain electrode, and the shallow trench isolation is performed between the substrate and the deep N well.
[0013] As the preferred mode, the resistance R1 and the resistance R2 have the resistance value of 1500 ohms.
[0014] As the preferred mode, the number of the channels of the pipe I1 is 8 times the number of the channels of the pipe I2.
[0015] As the preferred mode, the resistance R1 and the pipe I2 can be connected inside the protected device.
[0016] The chip static protection structure has the following advantages:
[0017] The chip high-reliability high-voltage static protection circuit layout structure is based on the process of the flow sheet manufacturing plant, can meet the actual size needs of the chip and the static protection needs, reduces the occupation of the chip area on the basis of ensuring the static protection effect, and can realize the HBM static protection mode of more than 2KV. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 It is a circuit diagram of a chip static protection structure;
[0019] Figure 2 It is a layout of a chip static protection structure;
[0020] Figure 3 It is a lower half layout of a chip static protection structure;
[0021] Figure 4 It is an upper layout of a chip static protection structure;
[0022] Figure 5 It is a MOS pipe I1, I2 structure schematic diagram of a chip static protection structure. Detailed Implementation
[0023] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.
[0024] Example 1
[0025] A chip electrostatic discharge protection structure, such as Figure 1 As shown, R2 and I1 constitute the first level of protection, and R1 and I2 constitute the second level of protection. The structures of I1 and I2 are as follows: Figure 5 As shown, the six terminals of the transistor are GATE, Source, Drain, Bulk, NWELL, and substrate. Among them, NWELL and PWELL2, and NWELL and P-epi respectively form two reverse-biased PN junctions, which puts the transistor in an independent isolation island. Even if there is a large current or voltage at the Drain terminal, it is difficult to impact other devices on the chip, thus providing double protection.
[0026] The electrostatic protection circuit of this invention is divided into two levels of protection. The MOSFET in the circuit is a six-terminal device with additional SB and NW terminals, thus achieving multi-level isolation of the device.
[0027] This utility model provides a layout design for a chip electrostatic protection circuit, such as... Figure 1 The diagram shown illustrates the electrostatic discharge (ESD) protection circuit. It consists of two levels of protection. The first level comprises resistors R2 and I1. The MOS transistor I1 has a width and length of 40µm / 0.7µm, and there are 16 transistors in total. Together with resistor R2, they provide the primary ESD protection. The second level consists of resistors R1 and I2. These two components are for the second level of protection and are relatively small. They can be placed internally within the circuit or near the pad. Figure 2 As shown, the drains of I1 and I2 need to have a width of at least 8µm to increase their voltage withstand capability. Figure 3 , Figure 4 As shown. I1 and R2 on the left should be placed as close as possible to the input / output points PAD in the overall layout, while I2 and R1 on the right should be placed as close as possible to the gate of the transistor that needs to be protected.
[0028] STI (shallow trench isolation) is typically used in processes below 0.25µm. It involves depositing, patterning, and etching a silicon nitride mask to create trenches, which are then filled with deposited oxide to isolate the silicon. You can think of it as an oxide barrier; it's an insulating material.
[0029] Six-terminal MOS transistor is high voltage resistant transistor, which adds a layer of PWELL and a layer of NWELL (or DNWELL) in normal four-terminal MOS transistor; six terminals are GATE (gate), Source (source), Drain (drain), Bulk (P well, such as Figure 5 PWELL2 in the following figure), NWELL (deep N well) and substrate (substrate, such as PWELL1 in the following figure), gate, source and drain are the same as prior art; the Bulk (P well) here is equivalent to the substrate potential in four-terminal MOS transistor, the Bulk (P well) here and the substrate (substrate) are the same potential, which is GND, and they are both P type injection; the NWELL (deep N well) is N type injection, which must be connected to stable high potential, so that the NWELL can form two reverse PN junction diodes with the Bulk (P well) and the substrate (substrate) respectively, to achieve isolation effect, such as Figure 5 . Figure 5 The N or P marked in the following figure are N type or P type semiconductor
[0030] The above is only the preferred specific implementation of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.
Claims
1. A chip electrostatic discharge protection structure, characterized in that: It includes a resistor R1 with one end connected to the PAD layer and the other end connected to the protected device; a MOS transistor I2 with its drain connected between the resistor R1 and the protected device, and its gate and source connected to ground; a MOS transistor I1 with its drain connected between the resistor R1 and the PAD layer, and its source connected to the source of transistor I1 and grounded; and a resistor R2 with one end connected to the gate of transistor I1 and the other end connected to the source of transistor I1 and grounded. The size of tube I2 is smaller than that of tube I1. The drain width of both tube I1 and tube I2 is greater than 8um. The resistance values of resistors R1 and R2 are the same.
2. The chip electrostatic protection structure according to claim 1, characterized in that: Transistors I1 and I2 have the same structure and are both six-terminal devices. Both transistors I1 and I2 include a gate, a source, a drain, a substrate, a deep N-well, and a P-well. The P-well of transistor I1 is connected to the source and then grounded, the deep N-well is connected to the power supply voltage VDD, and the substrate is connected to the source and gate and then grounded. The P-well of transistor I2 is connected to the source and then grounded. The deep N-well is connected to the deep N-well of transistor I1 and then connected to the power supply voltage VDD. The substrate is connected to the source and gate and then grounded.
3. The chip electrostatic protection structure according to claim 2, characterized in that: The P-well and substrate of transistor I1 have the same potential and are both P-type semiconductors. The deep N-well is an N-type semiconductor, and the deep N-well, together with the P-well and the substrate, form two reverse PN junction diodes.
4. The chip electrostatic protection structure according to claim 2, characterized in that: Shallow trench isolation is performed on both sides of the P-well, both sides of the deep N-well, and both sides of the substrate. Shallow trench isolation is performed between the P-well and the source, between the deep N-well and the drain, and between the substrate and the deep N-well.
5. The chip electrostatic protection structure according to claim 1, characterized in that: The resistance values of resistors R1 and R2 are both 1500 ohms.
6. The chip electrostatic protection structure according to claim 1, characterized in that: The number of channels in tube I1 is 8 times the number of channels in tube I2.
7. The chip electrostatic protection structure according to claim 1, characterized in that: Resistor R1 and tube I2 can be connected inside the protected device.