High-density transverse interconnection packaging structure
By using a high-density lateral interconnect packaging structure and existing 2D packaging equipment and processes, high-density interconnection between chips is achieved, solving the problem of high cost of 2.5D and 3D packaging, reducing manufacturing difficulty and maintaining good heat dissipation performance.
Patent Information
- Application Number
- CN202520141143.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-01-21
AI Technical Summary
Existing 2.5D and 3D packaging processes are complex and costly, making them difficult to apply on a large scale in high-density chip packaging. Furthermore, existing technologies increase the difficulty and cost of substrate manufacturing.
Employing a high-density lateral interconnect packaging structure, the design of the substrate, chip, and interconnect bridges utilizes existing 2D packaging equipment and processes to achieve high-density lateral interconnects between chips. Interconnect bridges and micro-bonding pillars made of silicon or glass are used for welding and bonding, and the chips are filled with adhesive for protection.
It reduces packaging costs, simplifies the manufacturing process, ensures high-density communication between chips, and does not affect the chip's heat dissipation performance.
Smart Images
Figure CN223912863U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to microelectronic packaging technical field, especially a kind of high-density lateral interconnection packaging structure. BACKGROUND
[0002] Shortening the interconnection pitch between chips is one of the key targets of modern integrated circuit development, the core is through process, design and equipment iteration, constantly reducing the interconnection pitch between chips and chips, increasing the interconnection bandwidth between chips to improve performance. With the industry's unlimited pursuit of computing power and performance, driving chip packaging develops from 2D to 2.xD and 3D integration, its typical feature is multi-chip high-density interconnection, such as 2.5D packaging through interlayer interconnection, compared with conventional substrate level interconnection, the interconnection pitch between GPU / CPU and I / O, HBM chip is shortened, and 3D packaging further adopts through silicon via to realize chip vertical stacking, the shortest interconnection pitch between chips and the optimal product performance are obtained, which can effectively improve performance and reduce power consumption while improving chip integration, so that the system has more excellent electrical and thermal characteristics.
[0003] However, the current 2.5D and 3D packaging process is complex, the design cycle is long and difficult, the equipment requirement is high, the cost is high, only HPC, GPU, Al and other high-value products are adopted, Intel's 2.3D EMIB packaging technology embeds silicon interconnection bridge in the substrate, although the packaging difficulty is reduced, but the manufacturing difficulty of the substrate is increased, the cost improvement is not obvious, and IBM's technology also has similar problems in large-area hole opening on the substrate, which limits its larger-scale application. For large-scale, low-cost application scenarios of high-density chip packaging, it is urgent to propose a lower-cost multi-chip high-density interconnection scheme based on existing mature processes. UTILITY MODEL CONTENT
[0004] The utility model aims at the deficiency in the above background art, provides a kind of high-density lateral interconnection packaging scheme to solve the cost problem of interconnection packaging between chip and chip.
[0005] In order to achieve the above purpose, the utility model provides a kind of high-density lateral interconnection packaging structure, at least including substrate, first chip, second chip and interconnection bridge, the substrate is provided with a plurality of solder balls, the interconnection bridge is provided with a plurality of micro solder columns, the solder joint on the first chip and the second chip includes conventional solder joint and micro solder joint, the conventional solder joint corresponds to the solder ball on the substrate, the first chip and the second chip are welded and bonded with the substrate through the corresponding solder ball, the first chip and the second chip are welded and bonded with the interconnection bridge through the corresponding micro solder column, so that the first chip and the second chip are laterally and high-density interconnected, the micro solder joint is located on the upper surface of the first chip and the second chip after flip-chip, and the micro solder column is located on the lower surface of the interconnection bridge.
[0006] Further, the material of the interconnection bridge is silicon or glass.
[0007] Further, the material of the interconnection bridge is an organic film.
[0008] Further, the first chip, the second chip and the substrate are filled with filling glue, and the interconnection bridge and the welding position of the first chip and the second chip are also filled with filling glue.
[0009] Further, the upper surface of the interconnection bridge is also provided with the micro welding column, which is used for welding and bonding with the chip in the upper layer.
[0010] The above scheme of the utility model has the following beneficial effects:
[0011] The high-density transverse interconnection packaging structure provided by the utility model realizes transverse high-density interconnection of the first chip and the second chip through the interconnection bridge, and compared with 2.5D and 3D packaging, the process is simpler and the technical difficulty is lower, the existing 2D packaging equipment and process can be used, and on the basis of certain improvement and optimization, the manufacturing cost is reduced, the transverse high-density communication demand between chips is ensured, and in addition, the heat dissipation of the upper surface of the chip is not obviously damaged.
[0012] Other beneficial effects of the utility model will be described in detail in the subsequent specific embodiment part. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 It is a whole structure schematic view of the utility model;
[0014] Figure 2 It is a four-chip same layer packaging plan view of the utility model;
[0015] Figure 3 It is a four-chip two-layer packaging front view of the utility model.
[0016] EXPLANATION OF REFERENCE NUMERALS
[0017] 1-base plate; 2-first chip; 3-second chip; 4-interconnection bridge; 5-welding ball; 6-micro welding column; 7-filling glue. DETAILED DESCRIPTION
[0018] In order to make the technical problems, technical schemes and advantages to be solved by the utility model more clear, the following will be described in detail in combination with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the ordinary skilled in the art without making creative labor belong to the protection scope of the utility model. In addition, the technical features involved in different embodiments of the utility model described below can be combined with each other as long as they do not conflict with each other.
[0019] In the description of the utility model, it needs to be explained that the orientation or position relation indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is the orientation or position relation based on the drawing shown, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as the restriction on the utility model. In addition, the terms "first", "second", "third" are only for the description purpose, and cannot be understood as indicating or implying the relative importance.
[0020] In the description of the utility model, it needs to be explained that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, it can be locking connection, or detachable connection, or integrally connected, it can be mechanical connection, or electrical connection, it can be directly connected, or indirectly connected through intermediate medium, or the communication inside two elements. For the ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0021] As Figure 1 As shown in the utility model embodiment provides a kind of high-density lateral interconnection package structure, including substrate 1, first chip 2, second chip 3 and interconnection bridge 4. Wherein, interconnection circuit is integrated in substrate 1, while multiple solder balls 5 are provided on substrate 1. First chip 2, second chip 3 are all welded and bonded with substrate 1 by solder ball 5. Interconnection bridge 4 is used to connect adjacent first chip 2 and second chip 3, or connect multiple chips adjacent. Wherein, the solder point on first chip 2, second chip 3 includes conventional solder point and micro solder point, conventional solder point corresponds the solder ball 5 on substrate 1, and micro solder point corresponds with micro solder column 6 on interconnection bridge 4.
[0022] Among them, multiple micro-solder pillars 6 are densely arranged on the interconnect bridge 4. The size and spacing of the micro-solder pillars 6 are relatively small. At the same time, the interconnect bridge 4 integrates high-density fine-pitch lines for lateral interconnection. The line width / pitch is usually smaller than the line width / pitch of the substrate 1 (e.g., 10 / 10μm). Therefore, compared with the interconnection between chips in the substrate 1, the first chip 2 and the second chip 3 can be laterally interconnected with high density through the arrangement of the interconnect bridge 4. The high-density fine-pitch lines enable the entire package to achieve a higher degree of integration.
[0023] In this embodiment, the micro-solder joints are arranged on the back side of the chip (the upper surface after flip-chip bonding). The interconnect bridge 4 is located above the first chip 2 and the second chip 3, and is bonded to the first chip 2 and the second chip 3 via micro-solder pillars 6 on the lower surface of the interconnect bridge 4. The interconnect bridge 4 can be made of silicon, glass, or an organic film (such as polyimide, ABF, etc.). After the interconnect bridge 4 is bonded to the first chip 2 and the second chip 3, not only do the first chip 2 and the second chip 3 need to be protected with filler adhesive 7 from the substrate 1, but the bonding positions between the interconnect bridge 4 and the first chip 2 and the second chip 3 also need to be protected with filler adhesive 7.
[0024] It should be noted that this embodiment is not limited to packaging the two chips mentioned above with interconnect bridge 4. More chips can be packaged, such as four or six, based on different sizes of interconnect bridge 4. These chips can be located at the same height or at different heights. The chips in this embodiment are any chips suitable for packaging; they can be multiple chips of the same type or multiple chips of different types, such as I / O or HBM chips. There are no limitations here; however, based on requirements such as packaging efficiency and package size, multiple chips are generally packaged.
[0025] When these chips are located at the same height, taking four chips as an example, such as Figure 2 As shown, micro-bonding pillars 6 at the four diagonal positions of an interconnect bridge 4 are bonded to the micro-bonding points of the four chips respectively. That is, the four chips are located at the four diagonal positions in a square area, and the interconnect bridge 4 is located at the center of the square area. Therefore, the lateral interconnection between the four chips is completed through an interconnect bridge 4, further improving the packaging density and bandwidth.
[0026] When these chips are located at different heights, taking four chips as an example, such as... Figure 2 As shown, the chip is distributed in two layers. The interconnect bridge 4 is located at the height between the upper and lower layers of the chip. Micro-solder pillars 6 are provided on both the upper and lower surfaces of the interconnect bridge 4, which are soldered to the micro-solder points on the lower surface of the upper chip and the upper surface of the lower chip, respectively, to achieve the purpose of lateral high-density interconnection of both layers of chips through the same interconnect bridge 4. Of course, the upper and lower chips are also vertically interconnected through solder balls 5.
[0027] When the high-density lateral interconnection packaging structure is packaged, the substrate 1 is prepared, the first chip 2 and the second chip 3 are inverted and soldered and bonded with the substrate 1, vertical interconnection of the first chip 2 and the second chip 3 with the substrate 1 is realized, then the interconnection bridge 4 is soldered and bonded with the first chip 2 and the second chip 3 above the first chip 2 and the second chip 3, lateral high-density interconnection of the first chip 2 and the second chip 3 is realized, finally, the soldering position is filled with filling glue 7 and solidified. Of course, if it is necessary to continue to package chips on the upper layer, the chips on the upper layer are bonded with the first chip 2 or the second chip 3 on the lower layer, and the micro soldering column 6 on the upper surface of the interconnection bridge 4 is bonded, and the high-density lateral interconnection between the chips on the upper layer is completed.
[0028] In summary, the high-density lateral interconnection packaging structure provided by the embodiment is simpler in process and lower in technical difficulty compared with 2.5D and 3D packaging, can utilize the existing 2D packaging equipment and process, and is improved and optimized to a certain extent, thereby reducing manufacturing cost and ensuring lateral high-density communication demand between chips, and in addition, heat dissipation on the upper surface of the chip is not obviously damaged.
[0029] The technical features of the above embodiments can be combined arbitrarily, and to make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.
[0030] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A high-density, lateral interconnect package structure, characterized by, At least including a substrate, a first chip, a second chip and an interconnection bridge, the substrate is provided with a plurality of solder balls, the interconnection bridge is provided with a plurality of micro solder columns, the solder points on the first chip and the second chip include conventional solder points and micro solder points, the conventional solder points correspond to the solder balls on the substrate, the first chip and the second chip are welded and bonded with the substrate through the corresponding solder balls, the first chip and the second chip are welded and bonded with the interconnection bridge through the corresponding micro solder columns, so as to realize the transverse high-density interconnection between the first chip and the second chip, the micro solder points are located on the upper surface of the first chip and the second chip after being flipped, and the micro solder columns are located on the lower surface of the interconnection bridge.
2. The high-density, area-interleaved package structure of claim 1, wherein, The material of the interconnection bridge is silicon or glass.
3. The high density, lateral interconnection package structure of claim 1 wherein, The material of the interconnection bridge is an organic film.
4. The high density, lateral interconnection package structure of claim 1 wherein, The first chip, the second chip and the substrate are filled through filling glue, and the welding position of the interconnection bridge and the first chip and the second chip is also filled through filling glue.
5. The high density, lateral interconnection package structure of claim 1 wherein, The upper surface of the interconnection bridge is also provided with the micro solder column, and the micro solder column is used for welding and bonding with the chip on the upper layer.