Chip packaging structure, radio frequency front-end module and electronic equipment

Abstract

The utility model belongs to the technical field of packaging, and particularly relates to a chip packaging structure, which is characterized in that in a first region, a first connection point extends in a 45-degree direction and intersects with two points of a contour line of a first region of an isolation layer to form a relation between the length D of a first line segment and the height Hg1 of a first gap; compared with the prior art, the influence effect of the isolation layer on the cavity formation can be reflected more directly, and the reliability, miniaturization and cost of the whole packaging structure can be optimized and adjusted more accurately relative to the thickness parameter of the isolation layer.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of packaging, and particularly relates to a chip packaging structure, a radio frequency front-end module and electronic equipment. BACKGROUND

[0002] With the rapid development of information technology, the technical requirements of the semiconductor industry are increasingly improved. As the core technology, the importance of chips is increasingly highlighted. In the packaging process of some special function chips, a cavity structure needs to be formed between the chip and the substrate to meet the functional, performance or special requirements. For example, surface acoustic wave (SAW) filter chips and bulk acoustic wave (BAW) filter chips. These filter chips play a crucial role in the radio frequency field. For users, the demand for integration and miniaturization is constantly challenging the design and layout of products, especially in the mobile terminal field. In particular, in the 5G era, the demand for filter chips by mobile terminal radio frequency front-ends is increasing sharply. Therefore, how to ensure the reliability of these growing chips in the packaging design has become a problem to be solved. CONTENT OF THE UTILITY MODEL

[0003] The application solves the technical problem of low chip reliability in the prior art and provides a chip packaging structure and method.

[0004] In a first aspect, an embodiment of the application provides a chip packaging structure, comprising:

[0005] a substrate, provided with a first pad on a first surface;

[0006] a protective layer, provided on the first surface of the substrate;

[0007] a first packaging chip, provided on the first surface of the substrate, a bottom surface of the first packaging chip and the protective layer forming a first gap, and the bottom surface of the first packaging chip being opposite to the first surface;

[0008] a first interconnection bump, provided on the bottom surface of the first packaging chip, and connected with the first pad;

[0009] an isolation layer, covering the first packaging chip and the protective layer, wherein the isolation layer comprises a first area adjacent to the first gap, a first connection point is present in the first area, a first line segment is formed by extending in a 45-degree direction of the first connection point and intersecting two points of a first area contour line of the isolation layer, a length D of the first line segment and a height H of the first gap g1 satisfy the following relationship:

[0010] D≥H g1 .

[0011] In a second aspect, the embodiments of the present application provide a chip packaging structure, comprising:

[0012] a substrate, provided with a first pad on a first surface;

[0013] a protective layer, provided on the first surface of the substrate;

[0014] a first packaging chip, provided on the first surface of the substrate, a bottom surface of the first packaging chip and the protective layer forming a first gap, the bottom surface of the first packaging chip being opposite to the first surface;

[0015] a first interconnection bump, provided on the bottom surface of the first packaging chip, the first interconnection bump being connected with the first pad, the first interconnection bump forming a first projection pattern on the substrate along a longitudinal direction, in the first projection pattern, a longest line segment extending from a center point of the first projection pattern to both sides of the first projection pattern being greater than a height of the first interconnection bump;

[0016] an isolation layer, covering the first packaging chip and the protective layer.

[0017] In a third aspect, the embodiments of the present application provide a radio frequency front-end module, comprising:

[0018] a substrate, provided with a first pad on a first surface;

[0019] a protective layer, provided on the first surface of the substrate;

[0020] a first packaging chip, provided on the first surface of the substrate, a bottom surface of the first packaging chip and the protective layer forming a first gap, the bottom surface of the first packaging chip being opposite to the first surface;

[0021] a first interconnection bump, provided on the bottom surface of the first packaging chip, the first interconnection bump being connected with the first pad;

[0022] an isolation layer, covering the first packaging chip and the protective layer, the isolation layer comprising a first part provided on the protective layer, a first point and a second point being present on a side bottom of the first packaging chip, a thickness of the first part corresponding to the first point being less than a height of the first gap, a thickness of the first part corresponding to the second point being greater than the height of the first gap.

[0023] In a fourth aspect, the embodiments of the present application provide a radio frequency front-end module, comprising:

[0024] a substrate, provided with a first pad and a second pad on a first surface;

[0025] a protective layer disposed on the first surface of the substrate;

[0026] a first package chip disposed on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and the bottom surface of the first package chip and the protective layer form a first gap, and the bottom surface of the first package chip is opposite to the first surface;

[0027] a second package chip disposed on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and the bottom surface of the second package chip and the first surface of the substrate form a second gap, and the bottom surface of the second package chip is opposite to the first surface;

[0028] an isolation layer covering the first package chip, the protective layer and part of the second package chip;

[0029] the first interconnection bump forms a first projection pattern on the substrate along a longitudinal direction, and in the first projection pattern, a longest line segment extending through a center point of the first projection pattern to both sides of the first projection pattern is greater than a height of the first interconnection bump, and the height of the first interconnection bump is less than a height of the second interconnection bump;

[0030] a sealing layer covering the protective layer, the first package chip and the second package chip, and at least partially filling the second gap.

[0031] In a fifth aspect, an embodiment of the present application provides a radio frequency front-end module, comprising:

[0032] a substrate provided with a first pad and a second pad on a first surface;

[0033] a protective layer disposed on the first surface of the substrate;

[0034] a first package chip disposed on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and the bottom surface of the package chip and the protective layer form a first gap, and the bottom surface of the package chip is opposite to the first surface;

[0035] a second package chip disposed on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and the bottom surface of the package chip and the first surface of the substrate form a second gap, and the bottom surface of the second package chip is opposite to the first surface;

[0036] The first interconnection bump forms a first projection pattern on the substrate along the longitudinal direction, the second interconnection bump forms a second projection pattern on the substrate along the longitudinal direction, the area of the first projection pattern is greater than the area of the second projection pattern, and the height of the first interconnection bump is less than the height of the second interconnection bump;

[0037] An isolation layer covers the first packaging chip, the first surface of the substrate, and part of the second packaging chip;

[0038] A sealing layer covers the protective layer, the first packaging chip, and the second packaging chip, and at least partially fills the space between the second packaging chip and the substrate.

[0039] In a sixth aspect, an embodiment of the present application provides a radio frequency front-end module, comprising:

[0040] A substrate is provided with a first pad and a second pad on a first surface;

[0041] A protective layer is arranged on the first surface of the substrate;

[0042] A first packaging chip is arranged on the first surface of the substrate, and a bottom surface of the first packaging chip is provided with a first interconnection bump, the first interconnection bump is connected with the first pad, a bottom surface of the packaging chip and the first surface of the protective layer form a first gap, and the bottom surface of the packaging chip is opposite to the first surface;

[0043] A second packaging chip is arranged on the first surface of the substrate, and a bottom surface of the second packaging chip is provided with a second interconnection bump, the second interconnection bump is connected with the second pad, a bottom surface of the packaging chip and the first surface of the substrate form a second gap, and the bottom surface of the second packaging chip is opposite to the first surface;

[0044] An isolation layer covers the first packaging chip and the first surface of the substrate;

[0045] A sealing layer covers the protective layer, the first packaging chip, and the second packaging chip;

[0046] The isolation layer also covers the second packaging chip, and openings are formed on at least two sides and at most three sides of the second packaging chip, so that the sealing layer at least partially fills the space between the second packaging chip and the substrate.

[0047] In a seventh aspect, an embodiment of the present application provides a radio frequency front-end module, comprising:

[0048] A substrate is provided with a first pad, a second pad, and a third pad on a first surface;

[0049] a protective layer disposed on the first surface of the substrate;

[0050] a first package chip disposed on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and a first gap is formed between the bottom surface of the package chip and the first surface of the substrate;

[0051] a second package chip disposed on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the package chip and the first surface of the substrate;

[0052] a third package chip disposed on the first surface of the substrate, and a bottom surface of the third package chip is provided with a third interconnection bump connected with the third pad, and a third gap is formed between the bottom surface of the package chip and the protective layer;

[0053] an isolation layer covering the first package chip, the third package chip and part of the second package chip, the isolation layer comprising a first part disposed on the protective layer near the first package chip, and a fourth part disposed on the protective layer near the third package chip, a thickness of the first part being less than a height of the first gap, and a thickness of the fourth part being greater than a height of the third gap.

[0054] In an eighth aspect, an embodiment of the present application provides an electronic device comprising the chip packaging structure or the radio frequency front-end module.

[0055] In the chip packaging structure, the radio frequency front-end module and the electronic device provided in the embodiment of the present application, by setting the first area, the first connection point extends in the 45-degree direction to intersect with two points of the first area contour line of the isolation layer to form a first line segment with a length D, and the height H of the first gap g1 is in a relationship, which more directly reflects the influence of the isolation layer on the cavity, and relative to the thickness parameter of the isolation layer, the reliability, miniaturization and cost of the overall packaging structure can be more accurately optimized and adjusted. BRIEF DESCRIPTION OF DRAWINGS

[0056] The present application will be further described below in conjunction with the drawings and embodiments.

[0057] Figure 1Structure diagram of a chip packaging structure or a radio frequency front end module in an embodiment of the present application;

[0058] Figure 2 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0059] Figure 3 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0060] Figure 4 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0061] Figure 5 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0062] Figure 6 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0063] Figure 7 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0064] Figure 8 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0065] Figure 9 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0066] Figure 10 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0067] Figure 11 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0068] Figure 12 Structure diagram of a chip packaging structure or a radio frequency front end module in another embodiment of the present application;

[0069] The reference signs in the specification are as follows:

[0070] 10, substrate; 11, first surface; 12, first pad; 13, second pad; 14, third pad;

[0071] 20, protective layer;

[0072] 30, first packaging chip; 31, first connecting bump; 32, first functional area;

[0073] 40, isolation layer;

[0074] 50, sealing layer;

[0075] 60, second packaged chip; 61, second interconnect bump;

[0076] 70, third packaged chip; 71, third interconnect bump. DETAILED DESCRIPTION

[0077] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0078] It should be understood that the present application can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, the embodiments are provided so that the disclosure will be thorough and complete and will fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. The same reference numbers in different drawings represent the same elements.

[0079] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" or "connected" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0080] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0082] For a thorough understanding of the present application, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0083] An embodiment of the present application provides a chip packaging structure, comprising:

[0084] a substrate, provided with a first pad on a first surface;

[0085] a protective layer, provided on the first surface of the substrate;

[0086] a first packaging chip, provided on the first surface of the substrate, a bottom surface of the first packaging chip being provided with a first gap with the protective layer, the bottom surface of the first packaging chip being opposite to the first surface;

[0087] a first interconnection bump, provided on the bottom surface of the first packaging chip, the first interconnection bump being connected with the first pad;

[0088] An isolation layer covers the first package chip and the protective layer, wherein the isolation layer comprises a first region adjacent to the first gap, and a first connection point is present in the first region, a first line segment is formed by extending the first connection point in a 45-degree direction and intersecting two points of a contour line of the first region of the isolation layer, a length D of the first line segment is greater than a height H of the first gap g1 satisfies the following relationship:

[0089] D > H g1 .

[0090] In the present embodiment, as shown in Figure 1 and Figure 2 , the first surface 11 of the substrate 10 is provided with the first pads 12. Among them, the first pads 12 provided on the first surface 11 can be provided on the first surface 11 of the substrate (that is, protruding from the first surface 11), or the first pads 12 can be embedded in the first surface (as shown in Figure 1 ), or the first pads 12 can be partially embedded in the first surface and the other part protruding from the first surface 11 (as shown in Figure 2 ), or other feasible pad arrangement, which is not specifically limited here, Figure 1 Taking the first pads 12 embedded in the first surface 11 as an example.

[0091] In at least one embodiment, the number of the first pads 12 is more than 2. Optionally, the number of the first pads 12 is consistent with the number of the first interconnection bumps 31. Exemplarily, the bottom surface of the first package chip 30 comprises a plurality of first interconnection bumps 31, wherein each first interconnection bump 31 is connected with one first pad 12 on the first surface of the substrate 10.

[0092] The protective layer 20 is formed on the first surface of the substrate 10. In at least one embodiment, the protective layer 20 is formed by using a dielectric material. In one embodiment, the protective layer 20 can also be a solder mask layer, and the protective layer 20 can be formed by using a solder mask material. In this embodiment, the protective layer 20 is a solder mask layer formed on the first surface 11 of the substrate 10. By using the solder mask layer on the substrate as the protective layer, the formation of additional layers is reduced, and the consumption of additional materials and processes is reduced.

[0093] It can be understood that the protective layer 20 is provided with an opening, and exemplarily, an opening is provided at a position corresponding to the first pad 12 for interconnection of the first interconnection bump 31 of the first package chip 30 and the first pad 12.

[0094] In at least one embodiment, the protective layer 20 is provided with a first opening, the first package chip 30 forms a third projection figure on the substrate in a longitudinal direction, a main body of the third projection figure is located in the first opening, and a periphery of the third projection figure and a longitudinal projection of the protective layer 20 overlap. Understandably, in this embodiment, the first interconnection bump 31 also forms a first projection figure on the substrate in a longitudinal direction, which is also located in the first opening. Understandably, the longitudinal direction in the embodiments of the present application is a relative concept, and the longitudinal direction does not mean that it must be absolutely vertical or overhanging, and a slightly inclined direction is also allowed. For example, the longitudinal direction here can refer to the thickness direction (for example, the thickness direction of the substrate) in the chip package structure. Figure 1 For example, the longitudinal direction here can refer to the thickness direction (for example, the thickness direction of the substrate) in the chip package structure.

[0095] In at least one embodiment, the protective layer 20 is provided with a second opening, the first interconnection bump 31 forms a first projection figure on the substrate in a longitudinal direction, and the first projection figure is located in the second opening. Understandably, the number of second openings can be consistent with the number of first interconnection bumps, so that the first projection figure formed by each first interconnection bump is located in a second opening.

[0096] The first package chip 30 is arranged on the first surface 11 of the substrate 10, and a bottom surface of the first package chip 30 forms a first gap with the protective layer 20, and the bottom surface of the first package chip 30 is opposite to the first surface 11.

[0097] The first interconnection bump 31 is arranged on the bottom surface of the first package chip 30, and the first interconnection bump 31 is connected with the first pad 12. Understandably, the bottom surface of the first package chip 30 includes at least two first interconnection bumps 31. In at least one embodiment, each first interconnection bump 31 can be connected with a first pad 12 on the first surface of the substrate.

[0098] In at least one embodiment, the first package chip further includes a first functional area, as shown in Figure 1 and Figure 2 As shown in the figure, the first package chip 30 includes a first functional area 32, and the first functional area is provided with a wiring pattern, a device, etc. of the first package chip. For example, if the first package chip is a SAW filter chip, the first functional area is provided with an electrode finger pattern, a wiring pattern, etc. of the SAW filter. The first functional area forms a fifth projection figure on the substrate in a longitudinal direction. Optionally, the fifth projection figure is located in the first opening. Optionally, the fifth projection figure at least partially overlaps with the protective layer.

[0099] The isolation layer 40 covers the first encapsulation chip 30 and the protective layer 20. The isolation layer is a dielectric material. Optionally, the material of the isolation layer 40 can be an epoxy film, or other polymer film or other resin material such as a dry film. In at least one embodiment, the isolation layer 40 can be a material that has a certain ductility at high temperature, but has poor fluidity and does not present a liquid state at high temperature, so that the isolation layer 40 can better cover surfaces of various shapes and can play a better blocking role.

[0100] The thickness of the isolation layer 40 can be greater than 20 microns, for example, the thickness of the isolation layer 40 can be 40 microns, 70 microns, 80 microns, 100 microns, etc., or the thickness of the isolation layer can be greater than or equal to 40 microns, 70 microns, 80 microns, 100 microns, etc.; or can be less than or equal to 20 microns, for example, the thickness of the isolation layer 40 can be 18 microns, 15 microns, 10 microns, etc., or the thickness of the isolation layer can be less than or equal to 18 microns, 15 microns, 10 microns, etc.

[0101] In at least one embodiment, the isolation layer includes a first region adjacent to the first gap, and a first connection point is present in the first region, a first line segment is formed by extending in a 45-degree direction from the first connection point and intersecting two points of a contour line of the first region of the isolation layer, and the first connection point makes a trajectory line on a side of the isolation layer away from the first gap have only one intersection point with the first line segment.

[0102] In the formula, D is the length of the first line segment, and H is the height of the first gap. g1 The following relationship is satisfied:

[0103] D≥H g1 .

[0104] In the formula, the first region is a region of the isolation layer adjacent to the first gap. For example, the first region can be a part of the isolation layer in a rectangular pattern formed by extending a bottom edge of the first gap in a horizontal direction away from the first gap by a certain distance and extending the bottom edge of the first gap in a vertical direction away from the first gap by a certain distance. Optionally, the first distance can be 10 microns, 20 microns, 30 microns, 40 microns, etc. Figure 3 As shown, in the first region adjacent to the first gap of the isolation layer, a first connection point is present, and a first line segment L x It can be understood that in nodes other than the first connection point in the first region, the intersection points extending in a 45-degree direction from the contour line of the first region of the isolation layer will be greater than or less than 2.

[0105] In the related art, an isolation layer is provided to block the subsequent sealing layer from entering the space / gap between the first surface of the first packaging chip and the substrate, so as to form a cavity in the first packaging chip. However, in the actual process, due to improper control of the thickness of the isolation layer, if the isolation layer is too thin, it may cause the isolation layer to break and fail to block the subsequent sealing layer from entering the space / gap between the first surface of the first packaging chip and the substrate. If the isolation layer is too thick, it will affect the miniaturization of the overall packaging structure and increase the cost.

[0106] The inventors have found that the related art only adjusts the thickness of the isolation layer, but in the actual process, the thickness of the isolation layer will change due to extrusion in the process, and the thickness of different parts of the isolation layer will also be different. Therefore, by setting the thickness parameter of the isolation layer, it is not possible to directly affect the better formation of the cavity. Therefore, in the embodiments of the present application, the related parameters of the first region of the isolation layer adjacent to the first gap are limited, and the length D of the first line segment formed by the intersection of the two points of the first region of the isolation layer profile line extending in the 45-degree direction of the first connection point and the height H of the first gap g1 are related, which more directly reflects the influence of the isolation layer on the formation of the cavity, and can more accurately optimize and adjust the reliability, miniaturization and cost of the overall packaging structure relative to the thickness parameter of the isolation layer.

[0107] In at least one embodiment, the isolation layer includes a first part provided on the protective layer, and there are a first point and a second point on the side bottom of the first packaging chip, the thickness of the corresponding first part at the position of the first point is less than the height of the first gap, and the thickness of the corresponding first part at the position of the second point is greater than the height of the first gap. By limiting the different thicknesses of the first point and the second point on the side bottom of the first packaging chip, the reliability of the chip packaging structure is better ensured.

[0108] In this embodiment, the isolation layer includes a first part provided on the protective layer. There are a first point and a second point on the side bottom of the first packaging chip 30, for example, as shown in Figure 4 It can be understood that the first point A and the second point B on the side bottom of the first packaging chip 30 can be on the same side of the first packaging chip 30 or on different sides of the first packaging chip 30. In at least one embodiment, the first point and the second point are provided on two adjacent sides of the first packaging chip, for example, as shown in Figure 4As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip.

[0109] As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. Figure 5 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. Figure 5 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. p1 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. g1 The isolation layer includes a first part disposed on the protective layer. Understandably, the first part can be a part of the isolation layer extending along the horizontal direction on the protective layer. Optionally, the horizontal direction can be perpendicular to the longitudinal direction. Optionally, the thickness of the first part at the position A can be the average thickness of the first part at different positions of the first part at the position A, i.e., the thickness of the first part is the average thickness. Optionally, the thickness of the first part can be the average thickness of the first part extending a certain distance from the first point in the horizontal direction away from the first package chip. The certain distance can be 20 um, 30 um, 40 um, 50 um, or 60 um, etc. Specifically, the cross-sectional view at the position A can be taken, and then the average thickness of the first part extending a certain distance from the first point A in the horizontal direction away from the first package chip can be taken.

[0110] As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. Figure 6 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. Figure 6 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. p2 As shown, the first point A and the second point B are disposed on two sides adjacent to the first package chip. In at least one embodiment, the first point and the second point are disposed on two opposite sides of the first package chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first package chip. g1 The isolation layer includes a first part disposed on the protective layer. Understandably, the first part can be a part of the isolation layer extending along the horizontal direction on the protective layer. Optionally, the horizontal direction can be perpendicular to the longitudinal direction. Optionally, the thickness of the first part can be the average thickness of the first part at different positions of the first part at the position A, i.e., the thickness of the first part is the average thickness. Optionally, the thickness of the first part can be the average thickness of the first part extending a certain distance from the first point in the horizontal direction away from the first package chip. The certain distance can be 20 um, 30 um, 40 um, 50 um, or 60 um, etc. Specifically, the cross-sectional view at the position A can be taken, and then the average thickness of the first part extending a certain distance from the first point A in the horizontal direction away from the first package chip can be taken.

[0111] In at least one embodiment, a first device is disposed adjacent to a side on which the first point is located, and a second device is disposed adjacent to a side on which the second point is located, and a spacing between the first device and the first package chip is less than a spacing between the second device and the first package chip, and the first point and the second point are disposed on a bottom of different sides of the first package chip.

[0112] The first device can be a chip or a component, for example, the first device can be a filter chip, a radio frequency low noise amplifier chip, a radio frequency switch chip, a radio frequency power amplifier chip, or an analog control chip, or the first device can be a capacitor, an inductor, or a resistor, etc. The second device can be a chip or a component, for example, the second device can be a filter chip, a radio frequency low noise amplifier chip, a radio frequency switch chip, a radio frequency power amplifier chip, or an analog control chip, or the second device can be a capacitor, an inductor, or a resistor, etc. By adjusting the distance between the first device, the second device and the first package chip, the thickness of the corresponding first part at the first point position is less than the height of the first gap, and the thickness of the corresponding first part at the second point position is greater than the height of the first gap, thereby avoiding additional complex processes.

[0113] In at least one embodiment, the present application provides a radio frequency front-end module, comprising:

[0114] a substrate, a first pad is disposed on a first surface of the substrate;

[0115] a protective layer, disposed on the first surface of the substrate;

[0116] a first package chip, disposed on the first surface of the substrate, a bottom surface of the first package chip forms a first gap with the protective layer, and the bottom surface of the first package chip is opposite to the first surface;

[0117] a first interconnection bump, disposed on the bottom surface of the first package chip, and the first interconnection bump is connected to the first pad;

[0118] an isolation layer, covering the first package chip and the protective layer, the isolation layer includes a first part disposed on the protective layer, and a first point and a second point are present on a side bottom of the first package chip, the first point and the second point are disposed on the bottom of different sides of the first package chip, and a thickness of the corresponding first part at the first point position is less than a thickness of the corresponding first part at the second point position;

[0119] a first device, disposed adjacent to a side on which the first point is located;

[0120] The second device is disposed adjacent to the side surface where the second point is located, and the distance between the first device and the first packaging chip is less than the distance between the second device and the first packaging chip.

[0121] In the embodiment, by adjusting the distances of the first device, the second device and the first packaging chip, the thickness of the corresponding first part at the first point position is less than the thickness of the corresponding first part at the second point position, so that the overall reliability is ensured without additional complex processes.

[0122] In at least one embodiment, in the first packaging chip, the number of first points where the thickness of the corresponding first part is less than the height of the first gap is at least 3. Further, the distance between each of the at least 3 first points is greater than 5 um.

[0123] In at least one embodiment, in the first packaging chip, the thickness of the corresponding first part at the side surface where the first point is located is less than the height of the first gap. In at least one embodiment, in the first packaging chip, the thickness of the corresponding first part at the side surface where the second point is located is greater than the height of the first gap.

[0124] In at least one embodiment, in the first packaging chip, the number of second points where the thickness of the corresponding first part is greater than the height of the first gap is at least 3. Further, the distance between each of the at least 3 second points is greater than 5 um.

[0125] In at least one embodiment, the first interconnection bump forms a first projection pattern on the substrate along the longitudinal direction, and in the first projection pattern, the longest line segment extending through the center point of the first projection pattern to both sides of the first projection pattern is greater than the height of the first interconnection bump.

[0126] As shown in Figure 1 , the longest line segment L1 extending through the center point of the first projection pattern to both sides of the first projection pattern is greater than the height H of the first interconnection bump. e .

[0127] It can be understood that the first projection pattern formed by the first interconnection bump on the substrate can be of any form. It can be a regular pattern or an irregular pattern.

[0128] Exemplarily, as shown in Figure 7 , the first interconnection bump 31 forms an elliptical first projection pattern on the substrate. In the first projection pattern, the longest line segment L1 extending through the center point of the first projection pattern to both sides of the first projection pattern is greater than the height H of the first interconnection bump.e .

[0129] For example, such as Figure 8 As shown, the first interconnect bump 31 forms a first projected pattern on the substrate. Figure 8 In the first projected pattern shown, the longest line segment L1 that passes through the center point of the first projected pattern and extends to both sides of the first projected pattern is greater than the height H of the first interconnecting bump. e .

[0130] The height H of the first interconnect bump e H is the height of the first interconnect bump itself. The longitudinal distance between the top surface of the first pad and the first surface of the substrate is H. f Understandably, if the first pad 12 is disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11, such as...), Figure 2 As shown), then H f If the first pad is embedded in the first surface and its top surface is flush with the first surface, then H is a positive value. f It is 0.

[0131] In at least one implementation, such as Figure 2 As shown, the distance H between the bottom surface of the first packaged chip and the first surface of the substrate is... c equals H e With H f The sum of, i.e., H c =H e +H f .

[0132] In this embodiment, by limiting the longest line segment in the first projection pattern that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern to be greater than the height of the first interconnecting bump, the reliability of the first interconnecting bump can be guaranteed, and the possibility of cracking of the first interconnecting bump due to the presence of cavities can be reduced.

[0133] In at least one embodiment, the longest line segment is greater than 1.5 times the height of the first interconnect bump. In at least one embodiment, the longest line segment is greater than 1.8 times the height of the first interconnect bump. In at least one embodiment, the longest line segment is greater than 2 times the height of the first interconnect bump.

[0134] In at least one embodiment, the longest line segment is less than four times the height of the first interconnect bump.

[0135] In at least one embodiment, the first interconnection bump forms a first projected pattern on the substrate, in which the first projected pattern, a longest line segment LI formed by extending through a center point of the first projected pattern to both sides of the first projected pattern, and a shortest line segment L2 formed by extending through the center point of the first projected pattern to both sides of the first projected pattern, wherein an average of the longest line segment LI and the shortest line segment L2 is greater than a height of the first interconnection bump.

[0136] In at least one embodiment, the first interconnection bump forms a first projected pattern on the substrate, in which the first projected pattern, a longest line segment LI formed by extending through a center point of the first projected pattern to both sides of the first projected pattern, and a shortest line segment L2 formed by extending through the center point of the first projected pattern to both sides of the first projected pattern, wherein an average of the longest line segment LI and the shortest line segment L2 is greater than a height of the first interconnection bump. By limiting the average of the longest line segment LI and the shortest line segment L2, the possibility of cracking of the first interconnection bump due to the presence of a cavity can be better reduced.

[0137] In at least one embodiment, the average of the longest line segment LI and the shortest line segment L2 is greater than 1.3 times the height of the first interconnection bump. In at least one embodiment, the average of the longest line segment LI and the shortest line segment L2 is greater than 1.5 times the height of the first interconnection bump. In at least one embodiment, the average of the longest line segment LI and the shortest line segment L2 is greater than 1.8 times the height of the first interconnection bump. In at least one embodiment, the average of the longest line segment LI and the shortest line segment L2 is greater than 2 times the height of the first interconnection bump.

[0138] In at least one embodiment, the average of the longest line segment LI and the shortest line segment L2 is less than 4 times the height of the first interconnection bump.

[0139] In at least one embodiment, the length D of the first line segment and the height H of the first gap satisfy the following relationship: g1 The following relationship is satisfied:

[0140] D≤2H g1 .

[0141] In at least one embodiment, the length D of the first line segment and the height H of the first gap satisfy the following relationship: g1 The following relationship is satisfied:

[0142] D≤1.5H g1 .

[0143] By limiting the upper limit value of the length of the first line segment, the reliability and miniaturization of the overall package structure, and the cost can be considered.

[0144] In at least one embodiment, in the first region, a first set of line segments is formed by two points extending from the first connection point in a [40, 50] degree direction and intersecting with the outline of the first region of the isolation layer. The length of each line segment in the first set of line segments is greater than the height H of the first gap. g1 .

[0145] A first set of line segments is formed by intersecting two points extending from the first connection point at an angle of [40, 50] degrees with the outline of the first region of the isolation layer. The length of each line segment in the first set of line segments is greater than the height H of the first gap. g1 This can better ensure the formation of the cavity.

[0146] In at least one embodiment, the first pad protrudes from the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s satisfy:

[0147] 2H g1 <H s .

[0148] In this embodiment, as Figure 2 As shown, the first pad 12 protrudes from the substrate, that is, the longitudinal distance H between the top surface of the first pad and the first surface of the substrate is... f It is a positive value. In this embodiment, the height H of the first gap is set. g1 and the thickness H of the protective layer s Satisfy: 2H g1 <H s The thickness of the protective layer is set to be thicker than that of the first gap to avoid the height H of the first gap. g1 Too high a height is not conducive to the formation of cavities.

[0149] In at least one embodiment, the first pad is embedded in the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s satisfy:

[0150] 1.5H g1 <H s ≤2H g1 .

[0151] In this embodiment, the first pad is embedded in the substrate. Figure 1 For example, the top surface of the first pad is flush with the first surface. In this embodiment, the height H of the first gap is set... g1 and the thickness H of the protective layer s Satisfy: 1.5H g1 <Hs ≤ 2H g1 , which better ensures the stability of the cavity formation.

[0152] In at least one embodiment, the first pad is embedded in the substrate arrangement, the height H g1 of the first gap and the thickness H s of the protective layer satisfy: 1.5H g1 < H s < 2H g1 .

[0153] In at least one embodiment, the thickness H p of the isolation layer and the height H g1 of the first gap satisfy the following relationship:

[0154] 1 um < H g1 < H p ≤ 10 um.

[0155] In at least one embodiment, in the first projected pattern, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than 80 um. Optionally, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is less than 150 um.

[0156] In at least one embodiment, in the first projected pattern, the shortest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than 70 um. Optionally, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is less than 150 um.

[0157] In at least one embodiment, the area of the first projected pattern is greater than 900π um 2 By limiting the area of the overall projected pattern, it is ensured that the first interconnection bump can have stronger reliability, reducing the possibility of cracking of the first interconnection bump due to the presence of the cavity.

[0158] In at least one embodiment, the chip package structure further comprises a sealing layer, the sealing layer covering at least the protective layer and the isolation layer. As Figure 1 shown, the chip package structure further comprises a sealing layer 50. The sealing layer 50 covers the protective layer 20 and the isolation layer 40. In at least one embodiment, the sealing layer also covers part of the first surface of the substrate.

[0159] The sealing layer can be made of insulating resin material or other plastic sealing material. Alternatively, the sealing layer is made of resin material containing particles. The particles can be SiO2 particles or Al2O3 particles, and the application is not limited in this regard. It can be understood that other materials that can achieve the sealing function can also be used, and will not be described here.

[0160] In at least one embodiment, the thickness of the isolation layer is less than the height of the first gap.

[0161] In this embodiment, the thickness of the isolation layer is less than the height of the first gap. It can be understood that the thickness of different parts of the isolation layer may

[0162] In at least one embodiment, the isolation layer includes a first portion disposed on the protective layer, and the thickness of the first portion is less than the height of the first gap.

[0163] As shown in Figure 1 The isolation layer includes a first portion disposed on the protective layer, and it can be understood that the first portion can be the portion of the isolation layer extending in the horizontal direction on the protective layer. The horizontal direction can be perpendicular to the longitudinal direction. The thickness of the first portion can be obtained by averaging the thickness values of different positions in the first portion.

[0164] By setting the thickness of the first portion to be less than the height of the first gap, the isolation layer can be more conveniently set, and the formation of the cavity can be better ensured.

[0165] In at least one embodiment, the isolation layer further includes a second portion disposed on the side of the first package chip and a third portion disposed on the top surface of the package chip.

[0166] The thickness of the second portion is less than the thickness of the third portion, and / or the thickness of the second portion is less than the thickness of the first portion.

[0167] In this embodiment, as shown in Figures 1-2As shown, the isolation layer further includes a second portion disposed on a side of the first package chip and a third portion disposed on a top surface of the package chip. It can be appreciated that the second portion extends in a longitudinal direction along the first package chip, and the third portion extends in a horizontal direction on the top surface of the package chip. The thickness of the second portion can be obtained by averaging thickness values at different positions in the second portion. The thickness of the third portion can be obtained by averaging thickness values at different positions in the third portion.

[0168] In at least one embodiment, the thickness of the second portion is less than the height of the first gap. In some embodiments, the thickness of the second portion is set to be less than the height of the first gap, so that the formation of the cavity can be better ensured.

[0169] In at least one embodiment, the thickness of the third portion is less than the height of the first gap. In some embodiments, the thickness of the third portion is set to be less than the height of the first gap, so that the formation of the cavity can be better ensured.

[0170] In at least one embodiment, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 3 MPa. Alternatively, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 4 MPa. Exemplarily, the isolation layer can be selected from materials such as epoxy resin, silicone grease, PI film, etc. that satisfy the above condition (storage modulus at 150 degrees Celsius is greater than or equal to 3 MPa), and the condition can be met by adjusting the specific parameters, materials, etc.

[0171] In at least one embodiment, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 4 MPa, and the thickness of the isolation layer is less than or equal to 20 microns. Further, the thickness of the isolation layer 40 can be less than or equal to 18 microns, less than or equal to 15 microns, or less than or equal to 10 microns, etc.

[0172] In at least one embodiment, the first package chip is a surface acoustic wave filter chip.

[0173] In at least one embodiment, the isolation layer at least partially fills the first gap. The partial filling of the isolation layer into the first gap better prevents the isolation layer from being broken by a subsequent sealing layer, thereby improving the reliability of the overall package structure.

[0174] At least one embodiment of the present application provides a chip package structure, comprising:

[0175] a substrate, provided with a first pad on a first surface;

[0176] a protective layer disposed on the first surface of the substrate;

[0177] a first package chip disposed on the first surface of the substrate, a bottom surface of the first package chip forming a first gap with the protective layer, the bottom surface of the first package chip opposite the first surface;

[0178] a first interconnection bump disposed on the bottom surface of the first package chip, the first interconnection bump connected with the first pad, the first interconnection bump forming a first projection pattern on the substrate along a longitudinal direction, in the first projection pattern, a longest line segment extending through a center point of the first projection pattern to both sides of the first projection pattern being greater than a height of the first interconnection bump;

[0179] a separation layer covering the first package chip and the protective layer.

[0180] In the embodiment, by limiting the longest line segment extending through the center point of the first projection pattern to both sides of the first projection pattern to be greater than the height of the first interconnection bump, it can be ensured that the first interconnection bump has stronger reliability, and the possibility of cracking of the first interconnection bump caused by the existence of the cavity is reduced.

[0181] At least one embodiment of the present application provides a chip package structure, comprising:

[0182] a substrate provided with a first pad on a first surface;

[0183] a protective layer disposed on the first surface of the substrate;

[0184] a first package chip disposed on the first surface of the substrate, a bottom surface of the first package chip forming a first gap with the protective layer, the bottom surface of the first package chip opposite the first surface;

[0185] a first interconnection bump disposed on the bottom surface of the first package chip, the first interconnection bump connected with the first pad;

[0186] a separation layer covering the first package chip and the protective layer, the separation layer comprising a first part disposed on the protective layer, a first point and a second point existing on a side bottom of the first package chip, a thickness of the first part corresponding to the first point being less than a height of the first gap, a thickness of the first part corresponding to the second point being greater than the height of the first gap.

[0187] In the embodiment, by limiting the different thicknesses of the first point and the second point on the side bottom of the first package chip, the reliability of the chip package structure is better ensured.

[0188] At least one embodiment of this application provides a radio frequency front-end module, including:

[0189] The substrate has a first pad and a second pad on its first surface.

[0190] A protective layer is disposed on the first surface of the substrate;

[0191] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0192] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0193] An isolation layer covers the first packaged chip, the protective layer, and part of the second packaged chip;

[0194] The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump. The height of the first interconnect bump is less than the height of the second interconnect bump.

[0195] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the second gap.

[0196] In this embodiment, with Figure 9 For example, the first surface 11 of the substrate 10 is provided with a first pad 12 and a second pad 13. The first pad 12 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the first pad 12 can be embedded in the first surface (e.g.,...). Figure 9 (As shown), or, the first pad 12 may be partially embedded in the first surface and another part may protrude from the first surface 11, or other feasible pad configurations may be used, which are not specifically limited here. Figure 4 Taking the first pad 12 disposed on the first surface 11 as an example. The second pad 13 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the second pad 13 can be embedded in the first surface (e.g., Figure 9Alternatively, the second pad 13 can also be partially embedded in the first surface and partially protrude above the first surface 11, or other possible pad arrangement, which is not limited herein, Figure 9 For example, the second pad 13 is arranged on the first surface 11.

[0197] In at least one embodiment, the number of the first pads 12 is more than two. Optionally, the number of the first pads 12 is consistent with the number of the first interconnection bumps 31. For example, the bottom surface of the first package chip 30 includes a plurality of first interconnection bumps 31, wherein each of the first interconnection bumps 31 is connected to one of the first pads 12 on the first surface of the substrate 10.

[0198] In at least one embodiment, the number of the second pads 13 is more than two. Optionally, the number of the second pads 13 is consistent with the number of the second interconnection bumps 61. For example, the bottom surface of the first package chip 30 includes a plurality of second interconnection bumps 61, wherein each of the second interconnection bumps 61 is connected to one of the second pads 13 on the first surface of the substrate 10.

[0199] A protective layer 20 is formed on the first surface of the substrate 10. In at least one embodiment, the protective layer 20 is formed of a dielectric material. In one embodiment, the protective layer 20 can also be a solder mask layer, which can be formed of a solder mask material. In this embodiment, the protective layer 20 is a solder mask layer formed on the first surface 11 of the substrate 10. By using the solder mask layer on the substrate as the protective layer, the formation of an additional layer is reduced, and the consumption of additional material and process is reduced.

[0200] It is understood that the protective layer 20 is provided with openings, for example, provided with openings at the corresponding positions of the first pads 12 for the interconnection of the first interconnection bumps 31 of the first package chip 30 and the first pads 12.

[0201] In at least one embodiment, the protective layer 20 is provided with a first opening, and the first package chip 30 forms a third projection pattern on the substrate in the longitudinal direction, the main body of the third projection pattern is located in the first opening, and the outer periphery of the third projection pattern overlaps the protective layer 20. It is understood that in this embodiment, the first interconnection bump also forms a first projection pattern on the substrate in the longitudinal direction, which is also located in the first opening.

[0202] In at least one embodiment, the protective layer 20 is provided with a second opening, and the first interconnect bump forms a first projected pattern on the substrate along the longitudinal direction, the first projected pattern being located in the second opening. It is understood that the number of second openings can be the same as the number of first interconnect bumps, so that the first projected pattern formed by each first interconnect bump is located in one second opening.

[0203] In at least one embodiment, the protective layer 20 is provided with a third opening, and the second package chip 60 forms a fourth projected pattern on the substrate along the longitudinal direction, the fourth projected pattern being located within the first opening. It can be understood that in this embodiment, the second interconnect bump forming a second projected pattern on the substrate along the longitudinal direction is also located within the three openings.

[0204] In at least one embodiment, the protective layer 20 is provided with a fourth opening, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction, the second projection pattern being located in the fourth opening. It is understood that the number of fourth openings can be the same as the number of second interconnect bumps, so that the first projection pattern formed by each second interconnect bump is located in one fourth opening.

[0205] In at least one embodiment, the protective layer has a first opening and a third opening. In at least one embodiment, the protective layer has a first opening and a fourth opening. In at least one embodiment, the protective layer has a second opening and a third opening. In at least one embodiment, the protective layer has a second opening and a fourth opening.

[0206] like Figure 9 As shown, a first packaged chip 30 is disposed on a first surface 11 of the substrate 10, and a first interconnect bump 31 is disposed on the bottom surface of the first packaged chip. The first interconnect bump 31 is connected to the first pad 12. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0207] In at least one embodiment, the first packaged chip 30 is a chip that requires a cavity to exist between itself and the first surface of the substrate. Exemplarily, the first packaged chip is a filter chip. Optionally, the first packaged chip is a SAW filter chip, or the first packaged chip is a BAW filter chip.

[0208] A second packaged chip is disposed on the first surface of the substrate, and a second interconnect bump is disposed on the bottom surface of the second packaged chip. The second interconnect bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0209] like Figure 9 As shown, a second pad 13 is provided on the first surface 11 of the substrate 10. The second pad 13 on the first surface 11 can be disposed on the first surface 11 (i.e., protruding from the first surface 11), or the second pad 13 can be embedded in the first surface (e.g.,...). Figure 4 (As shown), or, the second pad 13 may be partially embedded in the first surface and another part protrudes above the first surface 11, or other feasible pad configurations may be used, which are not specifically limited here. Figure 4 Taking the second pad 13 embedded in the first surface as an example.

[0210] In at least one embodiment, the number of the second pads 13 is two or more. Optionally, the number of the second pads 13 is the same as the number of the second interconnect bumps 61. Exemplarily, the bottom surface of the second package chip 60 includes a plurality of second interconnect bumps 61, wherein each second interconnect bump 61 is connected to a second pad 13 on the first surface of the substrate 10.

[0211] A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate, such as... Figure 9 As shown, the second gap H g2 It is the straight-line distance between the bottom surface of the second packaged chip and the first surface of the substrate.

[0212] In at least one embodiment, the second packaged chip is a chip that does not require a cavity between itself and the first surface of the substrate. Exemplarily, the second packaged chip is a non-filter chip. Optionally, the second packaged chip may include at least one of a radio frequency low-noise amplifier, a radio frequency switch, a radio frequency power amplifier, or an analog control circuit. Optionally, the second packaged chip may be a radio frequency low-noise amplifier chip, a radio frequency switch chip, a radio frequency power amplifier chip, or an analog control chip.

[0213] In at least one embodiment, the height of the second interconnect bump is less than three times the height of the first interconnect bump. In at least one embodiment, the height of the second interconnect bump is less than 2.5 times the height of the first interconnect bump. In at least one embodiment, the height of the second interconnect bump is less than twice the height of the first interconnect bump.

[0214] The RF front-end module also includes an isolation layer, such as Figure 9 As shown, the isolation layer 40 covers the first packaged chip 30, the protective layer 20, and a portion of the second packaged chip 60. The isolation layer 40 covering a portion of the second packaged chip 60 means that the isolation layer 40 does not completely cover the second packaged chip 60 (exemplarily, it has an opening), allowing the subsequent sealing layer 50 or other materials to at least partially fill the space between the second packaged chip 60 and the first surface of the substrate.

[0215] Specifically, the isolation layer 40 may cover the top surface of the second packaged chip 60 (opposite to the bottom surface of the second packaged chip 60), and it is understood that the isolation layer 40 may cover at least a portion of the top surface of the second packaged chip 60. In at least one embodiment, the isolation layer 40 also covers at least a portion of the side surfaces of the second packaged chip 60.

[0216] In at least one embodiment, the isolation layer 40 may initially completely cover the second packaged chip 60, but in subsequent processes / flows, the sealing layer 50 may penetrate the isolation layer in some areas and at least partially fill the space / gap between the second packaged chip 60 and the first surface of the substrate. It is understood that additional processes / flows may also be used to create openings in some areas for the sealing layer 50 to at least partially fill the space / gap between the second packaged chip 60 and the first surface of the substrate.

[0217] The RF front-end module also includes a sealing layer 50, such as Figure 9 As shown, the sealing layer 50 covers the protective layer 20, the first packaged chip 30 and the second packaged chip 60, and at least partially fills the second gap.

[0218] like Figure 9 As shown, it can be understood that the sealing layer 50 can enter through a pre-drilled opening in the isolation layer near the second packaged chip and at least partially fill the second gap, or the sealing layer 50 can break through a portion of the isolation layer area near the second packaged chip during the process and enter through this broken area and at least partially fill the second gap.

[0219] In at least one embodiment, the first interconnect bump forms a first projected pattern on the substrate along the longitudinal direction. In the first projected pattern, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than the height of the first interconnect bump, and the height of the first interconnect bump is less than the height of the second interconnect bump. In this embodiment, by setting the longest line segment in the first projected pattern to pass through the center point of the first projected pattern and extending to both sides of the first projected pattern to be greater than the height of the first interconnect bump, the first interconnect bump can have stronger reliability when there is a cavity in the first packaged chip, reducing the possibility of cracking of the first interconnect bump due to the presence of a cavity. Furthermore, setting the height of the first interconnect bump to be less than the height of the second interconnect bump further ensures that the sealing layer can better fill the space between the second packaged chip and the substrate, reducing the obstruction of the subsequent sealing layer by the second interconnect bump, and better filling the space between the second packaged chip and the substrate, reducing the presence of gaps.

[0220] In at least one embodiment, the first interconnect bump forms a first projected pattern on the substrate along a longitudinal direction, and the second interconnect bump forms a second projected pattern on the substrate along a longitudinal direction. The area of ​​the first projected pattern is larger than the area of ​​the second projected pattern, and the height of the first interconnect bump is smaller than the height of the second interconnect bump. Figure 10 The image shown is an example of a first projected pattern of a first interconnect bump 31 and a second projected pattern of a second interconnect bump 61. The area of ​​the first projected pattern is larger than the area of ​​the second projected pattern, as shown below. Figure 9 As shown, the height H of the first interconnect bump h1 The height H of the second interconnect bump is less than h2 In this embodiment, by setting the area of ​​the first projected pattern to be larger than the area of ​​the second projected pattern, the reliability of the first packaged chip is further ensured and the possibility of subsequent cracking is reduced, especially when cavities exist in the first packaged chip. Furthermore, setting the height of the first interconnect bump to be smaller than the height of the second interconnect bump further ensures that the sealing layer can better fill the space between the second packaged chip and the substrate. Therefore, setting the area of ​​the second projected pattern to be smaller than the area of ​​the first projected pattern reduces the obstruction of the subsequent sealing layer by the second interconnect bump, allowing the sealing layer to better fill the space between the second packaged chip and the substrate, reducing the presence of gaps.

[0221] In at least one embodiment, the thickness of the isolation layer is less than the height of the first gap, and the height of the first gap is less than the height of the second gap.

[0222] In this embodiment, by limiting the thickness of the isolation layer to be less than the height of the first gap, and the height of the first gap to be less than the height of the second gap, the smaller thickness of the isolation layer can take into account both reliability and miniaturization.

[0223] In at least one embodiment, the vertical distance between the second packaging chip and the protective layer is H a , the lateral distance between at least one side of the second packaging chip and the protective layer is H b , and satisfies: H a > H b . Through this setting, the subsequent sealing layer can be more easily broken through the isolation layer near the second packaging chip to fill the space between the second packaging chip and the substrate.

[0224] In at least one embodiment, the vertical distance between the second packaging chip and the protective layer is H a , the lateral distance between at least one side of the second packaging chip and the protective layer is H b , and satisfies: By setting , the appropriate distance between the second packaging chip and the protective layer, including the longitudinal and lateral dimensions, can be achieved, so that the subsequent sealing layer can more easily break through the isolation layer near the second packaging chip to better fill the second gap between the bottom surface of the second packaging chip and the first surface of the substrate.

[0225] In at least one embodiment, the straight-line distance between any point on the bottom of the side of the second packaging chip and the protective layer is H d , and at least 20% of H d on the bottom of the side of the second packaging chip is greater than the height of the first gap. By limiting at least 20% of H d to be greater than the height of the first gap, better filling of the space between the second packaging chip and the substrate can be ensured, and voids are less likely to be left.

[0226] In at least one embodiment, the straight-line distance between any point on the bottom of the side of the second packaging chip and the protective layer is H d , and at least 50% of H d on the bottom of the side of the second packaging chip is greater than the height of the first gap.

[0227] In at least one embodiment, the first interconnection bumps form a first projected pattern on the substrate along the longitudinal direction, the second interconnection bumps form a second projected pattern on the substrate along the longitudinal direction, and a longest line segment extending through a center point of the first projected pattern to both sides of the first projected pattern is longer than a longest line segment extending through a center point of the second projected pattern to both sides of the second projected pattern.

[0228] In the present embodiment, by setting the longest line segment extending through the center point of the first projected pattern to both sides of the first projected pattern to be longer than the longest line segment extending through the center point of the second projected pattern to both sides of the second projected pattern, the reliability and miniaturization of the overall packaging structure are taken into account in the case where the first packaging chip has a cavity and the space between the second packaging chip and the substrate is filled by the sealing layer.

[0229] In at least one embodiment, the first interconnection bumps form a first projected pattern on the substrate along the longitudinal direction, the second interconnection bumps form a second projected pattern on the substrate along the longitudinal direction, and a shortest line segment extending through a center point of the first projected pattern to both sides of the first projected pattern is longer than a shortest line segment extending through a center point of the second projected pattern to both sides of the second projected pattern.

[0230] In the present embodiment, by setting the shortest line segment extending through the center point of the first projected pattern to both sides of the first projected pattern to be longer than the shortest line segment extending through the center point of the second projected pattern to both sides of the second projected pattern, the reliability and miniaturization of the overall packaging structure are taken into account in the case where the first packaging chip has a cavity and the space between the second packaging chip and the substrate is filled by the sealing layer.

[0231] In at least one embodiment, the first packaging chip is a filter chip, and the second packaging chip is a non-filter chip.

[0232] In at least one embodiment, the isolation layer covers the second packaging chip, and openings are formed on at least two sides of the second packaging chip, so that the sealing layer at least partially fills the space between the second packaging chip and the substrate. By limiting the openings to be formed on at least two sides, the filling of the space between the second packaging chip and the substrate is better ensured, and voids are less likely to be left.

[0233] In at least one embodiment, the isolation layer covers the second packaging chip, and openings are formed on at most three sides of the second packaging chip, so that the sealing layer at least partially fills the space between the second packaging chip and the substrate. By limiting the openings to be formed on at most three sides, the filling of the space between the second packaging chip and the substrate is better ensured, voids are less likely to be left, and the risk of excessive filling and additional stress is also avoided.

[0234] In at least one embodiment, a distance between a bottom surface of the second package chip and the substrate is greater than a distance between a bottom surface of the first package chip and the substrate, and a longitudinal distance between the bottom surface of the second package chip and the bottom surface of the first package chip is greater than 10 um.

[0235] At least one embodiment of the present application provides a radio frequency front-end module, comprising:

[0236] A substrate is provided with a first pad and a second pad on a first surface;

[0237] A protective layer is arranged on the first surface of the substrate;

[0238] A first package chip is arranged on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and the bottom surface of the package chip and the protective layer form a first gap, and the bottom surface of the package chip is opposite to the first surface;

[0239] A second package chip is arranged on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the package chip and the first surface of the substrate, and the bottom surface of the second package chip is opposite to the first surface;

[0240] The first interconnection bump forms a first projection pattern on the substrate, the second interconnection bump forms a second projection pattern on the substrate, an area of the first projection pattern is greater than an area of the second projection pattern, and a height of the first interconnection bump is less than a height of the second interconnection bump;

[0241] An isolation layer covers the first package chip, the first surface of the substrate and part of the second package chip;

[0242] A sealing layer covers the protective layer, the first package chip and the second package chip, and at least partially fills a space between the second package chip and the substrate.

[0243] At least one embodiment of the present application provides a radio frequency front-end module, comprising:

[0244] A substrate is provided with a first pad and a second pad on a first surface;

[0245] A protective layer is arranged on the first surface of the substrate;

[0246] a first encapsulation chip disposed on the first surface of the substrate, and a bottom surface of the first encapsulation chip is provided with a first interconnection bump connected with the first pad, and a first gap is formed between the bottom surface of the encapsulation chip and the first surface of the substrate, and the bottom surface of the first encapsulation chip is opposite to the first surface;

[0247] a second encapsulation chip disposed on the first surface of the substrate, and a bottom surface of the second encapsulation chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the encapsulation chip and the first surface of the substrate, and the bottom surface of the second encapsulation chip is opposite to the first surface;

[0248] an isolation layer covering the first encapsulation chip and the first surface of the substrate;

[0249] a sealing layer covering the protective layer, the first encapsulation chip and the second encapsulation chip;

[0250] the isolation layer also covers the second encapsulation chip, and openings are formed on at least two sides and at most three sides of the second encapsulation chip, so that the sealing layer at least partially fills the space between the second encapsulation chip and the substrate.

[0251] At least one embodiment of the present application provides a radio frequency front end module, comprising:

[0252] a substrate provided with a first pad, a second pad and a third pad on a first surface;

[0253] a protective layer disposed on the first surface of the substrate;

[0254] a first encapsulation chip disposed on the first surface of the substrate, and a bottom surface of the first encapsulation chip is provided with a first interconnection bump connected with the first pad, and a first gap is formed between the bottom surface of the encapsulation chip and the protective layer, and the bottom surface of the first encapsulation chip is opposite to the first surface;

[0255] a second encapsulation chip disposed on the first surface of the substrate, and a bottom surface of the second encapsulation chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the encapsulation chip and the first surface of the substrate, and the bottom surface of the second encapsulation chip is opposite to the first surface;

[0256] a third encapsulation chip disposed on the first surface of the substrate, and a bottom surface of the third encapsulation chip is provided with a third interconnection bump connected with the third pad, and a third gap is formed between the bottom surface of the encapsulation chip and the protective layer, and the bottom surface of the third encapsulation chip is opposite to the first surface;

[0257] an isolation layer covering the first encapsulation chip, the third encapsulation chip and part of the second encapsulation chip, the isolation layer comprising a first part disposed on the protective layer near the first encapsulation chip, and a fourth part disposed on the protective layer near the third encapsulation chip, the thickness of the first part being less than the height of the first gap, and the thickness of the fourth part being greater than the height of the third gap.

[0258] In the embodiment, the first surface 11 of the substrate 10 is provided with the first pad 12, the second pad 13 and the third pad 14. Figure 11 For example, the first surface 11 of the substrate 10 is provided with the first pad 12, the second pad 13 and the third pad 14. Among them, the third pad 14 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e. protruding from the first surface 11), or the third pad 14 can be embedded in the first surface (as shown in Figure 11 ), or the third pad 14 can be partially embedded in the first surface and protrude from the first surface 11, or other possible pad arrangement, which is not limited here, Figure 11 For example, the third pad 14 is embedded in the first surface 11.

[0259] In at least one embodiment, the number of the third pad 14 is more than 2. Optionally, the number of the third pad 14 is consistent with the number of the third interconnection bump 71. For example, the bottom surface of the first encapsulation chip 30 comprises a plurality of third interconnection bumps 71, and each third interconnection bump 71 is connected with one third pad 14 on the first surface of the substrate 10.

[0260] It can be understood that the protective layer 20 is provided with an opening, for example, an opening is provided at the corresponding position of the third pad 14 for interconnection of the third interconnection bump 71 of the first encapsulation chip 30 and the third pad 14.

[0261] In at least one embodiment, the protective layer 20 is provided with a fifth opening, the third encapsulation chip 70 forms a sixth projected figure on the substrate in the longitudinal direction, a main body of the sixth projected figure is located in the fifth opening, and a periphery of the sixth projected figure and a longitudinal projection of the protective layer 20 overlap. Understandably, in this embodiment, the first interconnection bump 31 also forms a sixth projected figure on the substrate in the longitudinal direction, which is also located in the fifth opening. Understandably, the longitudinal direction in the embodiments of the present application is a relative concept, and the longitudinal direction does not mean that it must be absolutely vertical or overhanging, and a slightly inclined direction is also allowed. For example, the longitudinal direction here can refer to the thickness direction (for example, the thickness direction of the substrate) in the chip packaging structure. Figure 1 For example, the longitudinal direction here can refer to the thickness direction (for example, the thickness direction of the substrate) in the chip packaging structure.

[0262] In at least one embodiment, the protective layer 20 is provided with a sixth opening, the third interconnection bump 71 forms a first projected figure on the substrate in the longitudinal direction, and the first projected figure is located in the sixth opening. Understandably, the number of sixth openings can be consistent with the number of first interconnection bumps, so that the seventh projected figure formed by each third interconnection bump is located in a sixth opening.

[0263] The third encapsulation chip 70 is arranged on the first surface 11 of the substrate 10, and a bottom surface of the third encapsulation chip 70 forms a third gap with the protective layer 20, and the bottom surface of the third encapsulation chip 70 is opposite to the first surface 11. In at least one embodiment, the third encapsulation chip 70 is a chip that needs to have a cavity between the first surface of the substrate. Exemplarily, the third encapsulation chip 70 is a filter chip. Alternatively, the third encapsulation chip 70 is a SAW filter chip, or the third encapsulation chip 70 is a BAW filter chip.

[0264] The third interconnection bump 71 is arranged on the bottom surface of the first encapsulation chip 30, and the third interconnection bump 71 is connected with the third pad 14. Understandably, the bottom surface of the third encapsulation chip 70 includes at least two third interconnection bumps 71. In at least one embodiment, each third interconnection bump 71 can be connected with one third pad 14 on the first surface of the substrate.

[0265] In at least one embodiment, the third encapsulation chip further includes a second functional area, such as Figure 11As shown, the third packaged chip 70 includes a second functional area, in which wiring patterns, components, etc., of the third packaged chip are disposed. For example, if the third packaged chip is a SAW filter chip, the second functional area is provided with electrode finger patterns, wiring patterns, etc., of the SAW filter. A fifth projection pattern is formed on the substrate along the longitudinal direction of the second functional area. Optionally, the fifth projection pattern is located in the fifth opening. Optionally, the fifth projection pattern at least partially overlaps with the protective layer.

[0266] In this embodiment, the isolation layer covers the first packaged chip, the third packaged chip, and a portion of the second packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

[0267] like Figure 11 As shown, the isolation layer covers the first packaged chip 30, the third packaged chip 70, and a portion of the second packaged chip 60. It can be understood that... Figure 11 The relative positions of the first packaged chip 30, the second packaged chip 60, and the third packaged chip 70 are merely an example and should not be construed as limiting their relative positions. Optionally, the first packaged chip and the third packaged chip are disposed adjacent to each other. Alternatively, the first packaged chip and the third packaged chip are disposed on different sides of the second packaged chip. In at least one embodiment, the first packaged chip is disposed adjacent to the second packaged chip relative to the third packaged chip. In at least one embodiment, the third packaged chip is disposed adjacent to the second packaged chip relative to the first packaged chip.

[0268] The thickness of the fourth part can be obtained by averaging the thickness values ​​taken at different locations in the fourth part as the overall thickness of the fourth part.

[0269] At least one embodiment of this application provides a radio frequency front-end module, including:

[0270] The substrate has a first pad and a third pad disposed on its first surface;

[0271] A protective layer is disposed on the first surface of the substrate;

[0272] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0273] a third package chip disposed on the first surface of the substrate, and a bottom surface of the third package chip is provided with a third interconnection bump connected with the third pad, and a third gap is formed between the bottom surface of the package chip and the protective layer, and the bottom surface of the third package chip is opposite to the first surface;

[0274] an isolation layer covering the first package chip and the third package chip, the isolation layer comprising a first part disposed on the protective layer near the first package chip, and a fourth part disposed on the protective layer near the third package chip, a thickness of the first part being less than a height of the first gap, and a thickness of the fourth part being greater than a height of the third gap.

[0275] At least one embodiment of the present application provides an electronic device comprising the chip package structure according to any one of the above embodiments / implementation manners, or comprising the radio frequency front-end module according to any one of the above embodiments / implementation manners.

[0276] It can be understood that, for the purpose of avoiding redundancy, some details of the same or similar technical features in the above description are not described in some embodiments or implementation manners, but these details are also applicable to different embodiments or implementation manners in essence.

[0277] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip package structure, characterized by, The application relates to a substrate provided with a first pad on a first surface; a protective layer provided on the first surface of the substrate; a first packaged chip provided on the first surface of the substrate, a bottom surface of the first packaged chip being provided with a first gap from the protective layer, the bottom surface of the first packaged chip being opposite to the first surface; a first interconnection bump provided on the bottom surface of the first packaged chip, the first interconnection bump being connected with the first pad; the first interconnection bump forms a first projection pattern on the substrate along a longitudinal direction, the first projection pattern satisfying at least one of the following conditions: in the first projection pattern, a longest line segment extending from a center point of the first projection pattern to both sides of the first projection pattern is greater than 80 microns; in the first projection pattern, a shortest line segment extending from the center point of the first projection pattern to both sides of the first projection pattern is greater than 60 microns; and the application further comprises a sealing layer covering at least the protective layer and the first packaged chip. The thickness of the isolation layer is less than the height of the first gap. The isolation layer comprises a first part provided on the protective layer, the thickness of the first part being less than the height of the first gap. The isolation layer further comprises a second part provided on the side of the first packaged chip and a third part provided on the top surface of the packaged chip. The thickness of the second part is less than the thickness of the third part, and / or the thickness of the second part is less than the thickness of the first part. An isolation layer covers the first packaging chip and the protection layer, wherein the isolation layer comprises a first region adjacent to the first gap, and a first connection point exists in the first region, a first line segment is formed by extending in a 45-degree direction of the first connection point to intersect two points of a contour line of the first region of the isolation layer, a length D of the first line segment and a height H of the first gap satisfy the following relationship: g1 satisfy the following relationship: 。 2. The chip package structure of claim 1, wherein, a length D of the first line segment and a height H of the first gap g1 satisfies the following relationship: 。 3. The chip package structure of claim 1, wherein, In the first region, a first set of line segments is formed by extending from the first connection point in a [40, 50] degree direction to intersect two points of the first region profile line of the isolation layer, and the length of each line segment in the first set of line segments is greater than the height H of the first gap g1 .

4. The chip package structure of claim 1, wherein, said first pad is arranged protruding from said substrate, a height H of said first gap g1 and a thickness H of said protective layer s satisfies: 。 5. The chip package structure of claim 1, wherein, The first pad is embedded in the substrate arrangement, the height H of the first gap g1 and the thickness H of the protective layer s satisfies: 。 6. The chip package structure of claim 1, wherein, a thickness H of the isolation layer p a height H of the first gap g1 satisfies the following relationship: 。 7. The chip package structure of claim 1, wherein, The storage modulus of the isolation layer at 150 degrees Celsius is greater than 3 MPa. The first packaged chip is a surface acoustic wave filter chip. The isolation layer at least partially fills the first gap. the area of the first projected pattern is greater than 900πum2 2 .

8. The chip package structure of claim 1, wherein, The application relates to a substrate provided with a first pad on a first surface; a protective layer provided on the first surface of the substrate; a first packaged chip provided on the first surface of the substrate, a bottom surface of the first packaged chip being provided with a first gap from the protective layer, the bottom surface of the first packaged chip being opposite to the first surface; a first interconnection bump provided on the bottom surface of the first packaged chip, the first interconnection bump being connected with the first pad, the first interconnection bump forming a first projection pattern on the substrate along a longitudinal direction, in the first projection pattern, a longest line segment extending from a center point of the first projection pattern to both sides of the first projection pattern being greater than the height of the first interconnection bump; and an isolation layer covering the first packaged chip and the protective layer.

9. The chip package structure of claim 1, wherein, The application relates to a substrate provided with a first pad on a first surface; a protective layer provided on the first surface of the substrate; a first packaged chip provided on the first surface of the substrate, a bottom surface of the first packaged chip being provided with a first gap from the protective layer, the bottom surface of the first packaged chip being opposite to the first surface; a first interconnection bump provided on the bottom surface of the first packaged chip, the first interconnection bump being connected with the first pad; 10. The chip package structure of claim 1, wherein, ​ 11. The chip package structure of claim 10, wherein, ​ ​ 12. The chip package structure of claim 1 or 9, wherein, ​ 13. The chip package structure of claim 1, wherein, ​ 14. The chip package structure of claim 1, wherein, ​ 15. A chip package structure, comprising: ​ ​ ​ ​ ​ ​ 16. A radio frequency front end module, comprising: ​ ​ ​ ​ ​ An isolation layer covers the first package chip and the protection layer, the isolation layer includes a first part disposed on the protection layer, there is a first point and a second point on the bottom of the side surface of the first package chip, the thickness of the corresponding first part at the position of the first point is less than the height of the first gap, and the thickness of the corresponding first part at the position of the second point is greater than the height of the first gap.

17. The radio frequency front end module of claim 16, wherein, Further comprising a first device and a second device, the first device is disposed adjacent to the side surface where the first point is located, the second device is disposed adjacent to the side surface where the second point is located, and the distance between the first device and the first package chip is less than the distance between the second device and the first package chip, the first point and the second point are disposed on the bottom of different side surfaces of the first package chip.

18. A radio frequency front end module, comprising: Comprise: A substrate, a first pad and a second pad are disposed on a first surface; A protection layer is disposed on the first surface of the substrate; A first package chip is disposed on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and a first gap is formed between the bottom surface of the first package chip and the first surface of the protection layer; A second package chip is disposed on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the second package chip and the first surface of the substrate; An isolation layer covers the first package chip, the protection layer and part of the second package chip; The first interconnection bump forms a first projection pattern on the substrate along the longitudinal direction, in the first projection pattern, the longest line segment extending through the center point of the first projection pattern to both sides of the first projection pattern is greater than the height of the first interconnection bump, and the height of the first interconnection bump is less than the height of the second interconnection bump; A sealing layer covers the protection layer, the first package chip and the second package chip, and at least partially fills the second gap.

19. The radio frequency front end module of claim 18, wherein, The thickness of the isolation layer is less than the height of the first gap, and the height of the first gap is less than the height of the second gap.

20. The radio frequency front end module of claim 18, wherein, The vertical distance between the second packaging chip and the protective layer is H a The lateral distance between at least one side of the second packaging chip and the protective layer is H b , and H a > H b .

21. The radio frequency front end module of claim 18, wherein, The vertical distance between the second packaging chip and the protective layer is H a The lateral distance between at least one side of the second packaging chip and the protective layer is H b , and satisfies: 20%.

22. The radio frequency front end module of claim 18, wherein, The straight-line distance between any point on the side bottom of the second packaging chip and the protective layer is H d Among the side bottom of the second packaging chip, at least 20% of H d is greater than the height of the first gap.

23. The radio frequency front end module of claim 18, wherein, The first package chip is a filter chip, and the second package chip is a non-filter chip.

24. The radio frequency front end module of claim 18, wherein, The isolation layer covers the second package chip, and openings are formed on at least two sides of the second package chip, so that the sealing layer at least partially fills the second gap formed between the bottom surface of the second package chip and the first surface of the substrate.

25. The radio frequency front end module of claim 18, wherein, The isolation layer covers the second package chip, and openings are formed on at most three sides of the second package chip, so that the sealing layer at least partially fills the second gap formed between the bottom surface of the second package chip and the first surface of the substrate.

26. The radio frequency front end module of claim 18, wherein, The distance between the bottom surface of the second packaging chip and the substrate is greater than the distance between the bottom surface of the first packaging chip and the substrate, and the longitudinal distance between the bottom surface of the second packaging chip and the bottom surface of the first packaging chip is greater than 10 um.

27. The radio frequency front end module of claim 18, wherein, The height of the second interconnection bump is less than 3 times the height of the first interconnection bump.

28. A radio frequency front end module, comprising: The application comprises: a substrate provided with a first pad and a second pad on a first surface; a protective layer provided on the first surface of the substrate; a first packaging chip provided on the first surface of the substrate, and the bottom surface of the first packaging chip is provided with a first interconnection bump connected with the first pad, and the bottom surface of the packaging chip and the protective layer form a first gap opposite to the first surface; a second packaging chip provided on the first surface of the substrate, and the bottom surface of the second packaging chip is provided with a second interconnection bump connected with the second pad, and the bottom surface of the packaging chip and the first surface of the substrate form a second gap opposite to the first surface; the first interconnection bump forms a first projection pattern on the substrate in the longitudinal direction, the second interconnection bump forms a second projection pattern on the substrate in the longitudinal direction, the area of the first projection pattern is greater than the area of the second projection pattern, and the height of the first interconnection bump is less than the height of the second interconnection bump; an isolation layer covering the first packaging chip, the first surface of the substrate and part of the second packaging chip; a sealing layer covering the protective layer, the first packaging chip and the second packaging chip, and at least partially filling the space between the second packaging chip and the substrate.

29. A radio frequency front end module, comprising: The application comprises: a substrate provided with a first pad and a second pad on a first surface; a protective layer provided on the first surface of the substrate; a first packaging chip provided on the first surface of the substrate, and the bottom surface of the first packaging chip is provided with a first interconnection bump connected with the first pad, and the bottom surface of the packaging chip and the protective layer form a first gap opposite to the first surface; a second packaging chip provided on the first surface of the substrate, and the bottom surface of the second packaging chip is provided with a second interconnection bump connected with the second pad, and the bottom surface of the packaging chip and the first surface of the substrate form a second gap opposite to the first surface; an isolation layer covering the first packaging chip and the first surface of the substrate; a sealing layer covering the protective layer, the first packaging chip and the second packaging chip; the isolation layer also covers the second packaging chip, and openings are formed on at least two sides and at most three sides of the second packaging chip, so that the sealing layer at least partially fills the space between the second packaging chip and the substrate.

30. A radio frequency front end module, comprising: The application comprises: a substrate provided with a first pad, a second pad and a third pad on a first surface; a protective layer disposed on the first surface of the substrate; a first package chip disposed on the first surface of the substrate, and a bottom surface of the first package chip is provided with a first interconnection bump connected with the first pad, and a first gap is formed between the bottom surface of the package chip and the first surface of the substrate; a second package chip disposed on the first surface of the substrate, and a bottom surface of the second package chip is provided with a second interconnection bump connected with the second pad, and a second gap is formed between the bottom surface of the package chip and the first surface of the substrate; a third package chip disposed on the first surface of the substrate, and a bottom surface of the third package chip is provided with a third interconnection bump connected with the third pad, and a third gap is formed between the bottom surface of the package chip and the protective layer; an isolation layer covering the first package chip, the third package chip and part of the second package chip, the isolation layer comprising a first part disposed on the protective layer near the first package chip, and a fourth part disposed on the protective layer near the third package chip, a thickness of the first part being less than a height of the first gap, and a thickness of the fourth part being greater than a height of the third gap.

31. An electronic device, comprising: The chip package structure according to any one of claims 1-15, or the radio frequency front-end module according to any one of claims 16-30.

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