Chip testing device

Abstract

The utility model discloses a chip testing device, which comprises a main control module, a testing platform, an environment control device, a testing adapter plate and a plurality of testing instruments, the test adapter plate comprises a plurality of first interfaces and a plurality of second interfaces; the environment control device is used for controlling the environment of the test platform; the test connection control end is electrically connected with the control end of the test adapter plate; each test signal interaction end is electrically connected with each test instrument; one of the first interface and the second interface is correspondingly and electrically connected with each test output interface, and the other one is correspondingly and electrically connected with each test instrument; the test adapter plate is used for switching the connection state between each test output interface and each test instrument, and different test instruments are used for testing different parameters of the chip to be tested. According to the technical scheme of the utility model, multiple electrical characteristics can be automatically tested at each test temperature, so that repeated switching of the test temperatures is avoided, and the efficiency of testing the electrical characteristics of the chip is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip testing technical field especially relates to a chip testing device. BACKGROUND

[0002] The electrical test of the chip can evaluate the electrical parameters such as current, voltage and power consumption of the chip, and the performance indexes such as response time and stability of the chip, and has important significance for the design optimization, quality control and troubleshooting of the chip. For the highly integrated complex chip, when the electrical test is carried out, multiple electrical characteristics need to be tested at multiple temperatures respectively, so that the potential reliability problems of the chip can be found in time to ensure the stability and reliability of the chip in the actual application process.

[0003] However, the test instrument in the prior art can only test a certain electrical characteristic of the chip, and when the electrical characteristic test is completed, the test instrument needs to be manually replaced to test other electrical characteristics of the chip. The test oven can accurately simulate various temperature environments from low temperature to high temperature, but the temperature adjustment of the test oven needs to spend a lot of time.

[0004] When multiple electrical characteristics of the chip at multiple temperatures need to be tested, the test instrument needs to be replaced multiple times at each temperature until the electrical characteristics at each temperature are measured, or a certain electrical characteristic of the chip is tested at multiple temperatures in turn until the electrical characteristics at each temperature are measured. The former needs to replace the test instrument multiple times at each temperature, but the replacement, connection, power-on and loading process of the test instrument needs to spend a lot of time, resulting in low efficiency of the electrical characteristic test of the chip. The latter needs to repeat the temperature switching of the test oven multiple times when testing multiple electrical characteristics of the chip, resulting in low efficiency of the electrical characteristic test of the chip. UTILITY MODEL CONTENTS

[0005] The utility model provides a kind of chip testing device to solve the defects existing in prior art, realize the automatic test of multiple electrical characteristics at each test temperature, to avoid test temperature repeated switching, it is beneficial to improve the efficiency of the electrical characteristic test of chip.

[0006] According to an aspect of the utility model, a kind of chip testing device is provided, comprising: main control module, test platform, environmental control device, test adapter plate and multiple test instruments;

[0007] The main control module includes test connection control end, multiple test signal interaction end, test environment control end and test start control end;The test platform includes test input end, multiple test input interface and multiple test output interface;The test adapter plate includes multiple first interface and multiple second interface;

[0008] The test environment control end is electrically connected with the control end of the environment control device; the test start control end is electrically connected with the test input end; a plurality of test input interfaces are electrically connected with the chip to be tested; the test connection control end is electrically connected with the control end of the test adapter plate; each test signal interaction end is electrically connected with the signal interaction end of each test instrument; each first interface is correspondingly electrically connected with each test output interface, and each second interface is correspondingly electrically connected with each test instrument.

[0009] The test adapter plate is used for switching the connection state between each test output interface and each test instrument.

[0010] The environment control device is used for controlling the environmental parameters of the test platform.

[0011] Optionally, the test adapter plate further comprises an adapter plate controller and a plurality of switches; the adapter plate controller comprises a connection instruction receiving end and a gate signal output end.

[0012] The connection instruction receiving end is electrically connected with the control end of the test adapter plate, and the gate signal output end is electrically connected with the control end of each switch.

[0013] At least one switch is arranged in the connection path between one first interface and one second interface.

[0014] Optionally, the plurality of switches form a plurality of switch groups; each switch group comprises at least one switch.

[0015] The first end of each switch is correspondingly electrically connected with each first interface.

[0016] In the same switch group, the second end of each switch is electrically connected with the same second interface.

[0017] Optionally, the plurality of switches comprise a plurality of first switches and a plurality of second switches.

[0018] The first end of the first switch is electrically connected with one first interface; the second end of the first switch is electrically connected with the first end of at least one second switch; and the second end of the second switch is electrically connected with one second interface.

[0019] Optionally, the first end of each first switch is correspondingly electrically connected with each first interface; the second end of each first switch is electrically connected with a first node; the first end of each second switch is electrically connected with the first node; and the second end of each second switch is correspondingly electrically connected with each second interface.

[0020] Optionally, the plurality of first switches form M first switch groups, and the plurality of second switches form M second switch groups; the first end of each first switch is electrically connected to each first interface in one-to-one correspondence; the second end of each first switch in the ith first switch group is electrically connected to the first end of each second switch in the jth second switch group; the second end of each second switch is electrically connected to each second interface in one-to-one correspondence; wherein M is an integer greater than or equal to 2, and i and j are integers from 1 to M.

[0021] Optionally, the main control module comprises an upper computer.

[0022] Optionally, the test adapter board further comprises a circuit board.

[0023] The adapter board controller, the switches, the first interfaces, and the second interfaces are respectively arranged on the circuit board and electrically connected through the circuit board.

[0024] Optionally, the environment control device comprises a heating device, a refrigeration device, and a temperature sensor; the heating device, the refrigeration device, and the temperature sensor are electrically connected to the main control module.

[0025] Optionally, the environment control device further comprises a test box; the heating device, the refrigeration device, the temperature sensor, and the test platform are located in the test box.

[0026] The technical scheme of the utility model, through the test environment control end of main control module and the control end of environment control device are connected, so that the chip test device can control and collect the environment parameter of environment control device, and then control the environment where the test platform is located; the test input end of test platform and the test start control end of main control module are connected, the test input interface and the chip to be measured are connected, so that the main control module can control the working state of the test platform, and then control the state of each module in the chip to be measured through the test platform; at the same time, the control end of test adapter board and the test connection control end of main control module are connected, each test signal interaction end is connected with the signal interaction end of each test instrument, each first interface is connected with each test output interface in correspondence, and each second interface is connected with each test instrument in correspondence, so that the test adapter board can switch the connection state between each test output interface and each test instrument according to the test connection instruction provided by the test connection control end, and then each test instrument can test different parameters of the chip to be measured on the test platform. In this way, based on the control of the main control module on the environment control device, the test platform, the test adapter board, and each test instrument, multiple test instruments can be automatically switched and loaded, the electrical performance test of the chip to be measured under multiple temperature points is realized automatically, so that it is not necessary to manually replace the test instrument, and the efficiency of the electrical performance test of the chip is improved.

[0027] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the utility model, nor is it used to limit the scope of the utility model. Other features of the utility model will become easy to understand through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to make the technical scheme in the utility model embodiments clearer, the following will briefly introduce the drawings needed to be used in the embodiment description, obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creative labor.

[0029] Figure 1 The structural schematic diagram of a chip testing device provided by the utility model embodiment is shown in the figure;

[0030] Figure 2 The structural schematic diagram of a test adapter plate provided by the utility model embodiment is shown in the figure;

[0031] Figure 3 The structural schematic diagram of another test adapter plate provided by the utility model embodiment is shown in the figure;

[0032] Figure 4 The structural schematic diagram of still another test adapter plate provided by the utility model embodiment is shown in the figure;

[0033] Figure 5 The structural schematic diagram of still another test adapter plate provided by the utility model embodiment is shown in the figure;

[0034] Figure 6 The structural schematic diagram of still another test adapter plate provided by the utility model embodiment is shown in the figure. DETAILED DESCRIPTION

[0035] In order to make the technical scheme in the utility model embodiments clearer, the following will briefly introduce the drawings needed to be used in the embodiment description, obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creative labor.

[0036] It should be noted that the terms "first", "second", and the like in the description and claims of the utility model and the above drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0037] Figure 1 A structural schematic diagram of a chip testing device provided by the embodiments of the utility model is provided. Figure 1 As shown in the figure, the chip testing device 01 provided by the embodiments includes a main control module 300, a test platform 200, an environment control device 500, a test adapter board 100 and a plurality of test instruments 400. The main control module 300 includes a test connection control end 301, a plurality of test signal interaction ends 302, a test environment control end 303 and a test start control end 304. The test platform 200 includes a test input end 201, a test input interface (not shown in the figure) and a plurality of test output interfaces 202. The test adapter board 100 includes a plurality of first interfaces 31 and a plurality of second interfaces 32. The test environment control end 303 is electrically connected with the control end of the environment control device 500. The test start control end 304 is electrically connected with the test input end 201. A plurality of test input interfaces are electrically connected with the chip to be tested. The test connection control end 301 is electrically connected with the control end of the test adapter board 100. Each test signal interaction end 302 is electrically connected with the signal interaction end of each test instrument 400. Each first interface 31 is correspondingly electrically connected with each test output interface 202, and each second interface 32 is correspondingly electrically connected with each test instrument 400. The test adapter board 100 is used to control the connection state between each test output interface 202 and each test instrument 400.

[0038] The test platform 200 is used to carry and connect the chip to be tested. When the test platform 200 receives the test instruction provided by the test start control end 304 of the main control module 300, the chip is powered on according to the test instruction, so as to start each functional module of the chip to be tested. It should be noted that the chip to be tested can be a single-function chip such as a communication chip, a storage chip, a sensor chip and a processor chip, or a composite chip integrated with multiple functional modules, for example, an event camera chip including a software communication module, a storage module, a bandgap reference voltage module, a low-dropout linear voltage stabilizing module and the like, and the embodiments are not limited in this regard.

[0039] The environment control device 500 is used to control the environment where the test platform 200 is located, which can include, but is not limited to, the temperature environment where the test platform 200 is located. The environment control device 500 is electrically connected with the test environment control end 303 of the main control module 300, so as to be able to respond to the environment control and collection instructions provided by the test environment control end 303 to control the environment where the test platform 200 is located.

[0040] In an optional embodiment, the environment control device 500 can further include a heating device, a refrigeration device and a temperature sensor, all of which are connected with the main control module 300, so that the heating device and the refrigeration device can heat or cool the environment where the test platform 200 is located according to the environment control and collection instructions provided by the main control module 300 to adjust the environment where the test platform 200 is located, and the temperature sensor can collect the temperature of the environment where the test platform 200 is located according to the environment control and collection instructions provided by the main control module 300, so as to realize the control of the environment where the test platform 200 is located.

[0041] In an optional embodiment, the environment control device 500 includes a test box, and the test platform 200, the heating device, the refrigeration device and the temperature collection device are located in the test box, so that the test box can respond to the environment control and collection instructions provided by the test environment control end 303 of the main control module 300 to adjust the environmental temperature of the test platform 200 and collect the environmental temperature of the test platform 200, so that the environmental temperature of the test platform 200 can be accurately controlled without manual adjustment.

[0042] The test adapter 100 includes a plurality of first interfaces 31 and a plurality of second interfaces 32, wherein the first interface 31 and / or the second interface 32 can include, but are not limited to, a coaxial radio frequency connector; for example, the first interface 31 and / or the second interface 32 can be an MMCX interface.

[0043] It should be noted that, Figure 1 Only the case that the test adapter 100 includes four first interfaces 31 and four second interfaces 32 is shown, which does not limit the number of the first interfaces 31 and the second interfaces 32, and the core invention point of the utility model can be realized. In this embodiment, the number of the first interfaces 31 and the number of the second interfaces 32 can be the same or different, which can be set according to actual needs.

[0044] The control end of the test adapter 100 is electrically connected with the test connection control end 301 of the main control module 300, the test connection control end 301 is used to provide test connection instruction to the control end of the test adapter 100, the test adapter 100 is used to switch the connection path between the first interface 31 and the second interface 32 according to the test connection instruction, and then switch the connection state between each test output interface 202 and each test instrument 400, so that at least one test instrument 400 is electrically connected with the test platform 200.

[0045] The plurality of test instruments 400 can include a plurality of test instruments with different functions to test different parameters of the to-be-tested chip. For example, the plurality of test instruments 400 can include, but are not limited to, at least one of a six-and-a-half digit multimeter, an array source table, an oscilloscope, a signal generator, and an electronic load. In an exemplary embodiment, when the output voltage needs to be tested, the size of the output voltage can be tested by the digital source table or the six-and-a-half digit multimeter, and the real-time waveform amplitude change of the output voltage can be monitored by the oscilloscope, wherein the feedback of the oscilloscope can take the average value of the statistical results.

[0046] The test signal interaction end 302 of the main control module 300 is electrically connected with each test instrument 400, so that the test instrument 400 can test the start output condition of each functional module of the to-be-tested chip.

[0047] In an optional embodiment, the main control module 300 further includes a register and a host computer, the register is used to save the test results, the user can select the test items through the host computer, and the host computer can display and output the test results.

[0048] The process of the chip testing device provided in this embodiment is summarized as follows: after the chip testing device 01 is started, a test item is selected by the upper computer automatically or manually, and the host control module 300 generates or calls corresponding test script instructions according to the selected test item, wherein the test script instructions include but are not limited to environment control and collection instructions, test connection instructions, test control and collection instructions, and test instructions. The host control module 300 first provides the environment control and collection instructions to the environment control device 500, and the environment control device 500 adjusts the environment in which the test platform 200 is located according to the environment control and collection instructions, and feeds back the actual environment parameters in which the test platform 200 is located to the host control module 300. After the actual environment parameters in which the test platform 200 is located reach the target value, the host control module 300 provides the test connection instructions to the test adapter 100, the test instructions to the test platform 200, and the test control and collection instructions to the corresponding test instrument 400. The test adapter 100 switches the connection state between the test output interface 202 and the test instrument 400 in response to the test connection instructions, so as to complete the connection between the test instrument 400 and the test platform 200; the test platform 200 provides corresponding test power supply and loads test configuration in response to the test instructions, enables and starts the corresponding functional module of the chip under test; the test instrument 400 tests and monitors the working state or output state of the chip under test in response to the test control and collection instructions, and feeds back the test result to the host control module 300, so that the host control module 300 saves and displays the test result of the chip under test. After one test item is tested, other test items are replaced, and all test items are completed under the temperature. The test environment is adjusted again, and different tests of each test item are performed under each test environment. Finally, the environment control and collection instructions for adjusting the parameters of the environment control device 500 to the initial environment parameters (such as normal temperature) are provided, and after the parameters of the environment control device 500 are adjusted to the initial environment parameters, the environment control device 500 is turned off.

[0049] It should be noted that the test order of testing each test item under each test environment is not specifically limited in this embodiment, and the chip testing device 01 can first test each test item under the same test environment, and then adjust the test environment, and traverse each test environment until all test items are tested under all test environments.

[0050] It should be further noted that the test environment and test item of different chips under test can be different, and this embodiment does not make specific limitation.

[0051] In the embodiment, the test environment control end of the main control module is electrically connected with the control end of the environment control device, so that the chip test device can control and collect the environment parameters of the environment control device, and further control the environment in which the test platform is located; the test start control end of the main control module is electrically connected with the test input end of the test platform, and the plurality of test input interfaces are electrically connected with the chip to be tested, so that the main control module can control the working state of the test platform, and further the test platform can control the state of each module in the chip to be tested; meanwhile, the test connection control end of the main control module is electrically connected with the control end of the test adapter plate, each test signal interaction end is electrically connected with the signal interaction end of each test instrument, each first interface is correspondingly electrically connected with each test output interface, and each second interface is correspondingly electrically connected with each test instrument, so that the test adapter plate can switch the connection state between each test output interface and each test instrument according to the test connection instruction provided by the test connection control end, and further each test instrument can test different parameters of the chip to be tested located on the test platform. In this way, based on the control of the main control module on the environment control device, the test platform, the test adapter plate and each test instrument, a plurality of test instruments can be automatically switched and loaded, the chip to be tested can be automatically tested at multiple temperature points, and manual replacement of the test instrument 400 is not required, which is beneficial to improve the efficiency of the electrical performance test of the chip.

[0052] It should be noted that the communication relationship between the first interface 31 and the second interface 32 of the test adapter plate 100 provided in the embodiment can control the connection state between each test output interface 202 and each test instrument 400. The communication relationship between the first interface 31 and the second interface 32 can be designed according to actual needs, and the embodiment does not make specific limitation thereto.

[0053] Optionally, Figure 2 For the structure diagram of the test adapter plate provided in the embodiment of the utility model, as shown in the figure, Figure 2 The test adapter plate 100 further comprises an adapter plate controller 1 and a plurality of switches 21; the adapter plate controller 1 comprises a connection instruction receiving end and a gate signal output end 101; the connection instruction receiving end is electrically connected with the control end of the test adapter plate 100, and the gate signal output end 101 is electrically connected with the control end of each switch 21; at least one switch 21 is arranged in the connection path between one first interface 31 and one second interface 32.

[0054] The adapter plate controller 1 can include but is not limited to a single-chip microcomputer; for example, the adapter plate controller 1 can be an STM32 series single-chip microcomputer. The adapter plate controller 1 can generate a gate signal according to the test connection instruction provided by the test connection control end 301, and provide the gate signal to the control end of each switch 21 through the gate signal output end 101.

[0055] The plurality of switches 21 can include, but are not limited to, a relay switch or a semiconductor switch, etc. The strobe signal output end 101 is electrically connected to the control end of each switch 21, so that the strobe signal output by the adapter plate controller 1 can control the state of each switch 21, wherein the state of the switch 21 includes a conduction state and a disconnection state.

[0056] It can be understood that at least one switch 21 is arranged in the connection path between one first interface 31 and one second interface 32, or a plurality of switches 21 are arranged in the connection path between one first interface 31 and one second interface 32. By controlling the state of each switch 21 in the connection path between each first interface 31 and each second interface 32, a plurality of connection modes between each first interface 31 and each second interface 32 are realized.

[0057] Specifically, the strobe signal output end 101 of the adapter plate controller 1 is electrically connected to the control end of each switch 21, so that the strobe signal provided by the adapter plate controller 1 can control the state of each switch 21, for example, a part of the switches 21 can be controlled to be in a conduction state, and another part of the switches 21 can be controlled to be in a disconnection state, so that when each switch 21 in the connection path between the first interface 31 and the second interface 32 is in a conduction state, a conduction path can be formed between the first interface 31 and the second interface 32, and when there is a switch 21 in a disconnection state in the connection path between the first interface 31 and the second interface 32, a conduction path cannot be formed between the first interface 31 and the second interface 32. In this way, by changing the conduction or disconnection state of each switch 21, the connection path between each first interface 31 and each second interface 32 can be switched.

[0058] In an exemplary embodiment, the adapter plate controller 1 is connected to the switches 21 in the connection path between the first interface 31 and the second interface 32. Figure 2As shown, a switch 21 is arranged in the connection path between a first interface 31 and a second interface 32, so that the first interface 31 and the second interface 32 electrically connected with the same switch 21 can form a conduction path between the corresponding first interface 31 and the second interface 32 when the switch 21 is turned on, and conversely, the first interface 31 and the second interface 32 electrically connected with the same switch 21 cannot form a conduction path between the corresponding first interface 31 and the second interface 32 when the switch 21 is turned off. In this way, by changing the on or off state of the switch 21 electrically connected between the first interface 31 and the second interface 32, the connection path between the corresponding first interface 31 and the second interface 32 can be controlled to switch. For example, the plurality of first interfaces 31 includes a first first interface 311, a second first interface 312, a third first interface 313 and a fourth first interface 314, and the plurality of second interfaces 32 includes a first second interface 321, a second second interface 322, a third second interface 323 and a fourth second interface 324. When the switch 21 electrically connected with the first first interface 311 and the first second interface 321 is in an on state, the connection path between the first first interface 311 and the first second interface 321 is opened, and the connection paths between the other first interfaces 31 and the other second interfaces 32 (such as the connection path between the second first interface 312 and the second second interface 322) cannot be opened.

[0059] It should be noted that, Figure 2 Only the arrangement of a switch 21 in the connection path between a first interface 31 and a second interface 32 is taken as an example to exemplarily describe the manner in which the test adapter 100 controls the connection state between each test output interface 202 and each test instrument 400, and in the embodiment, the connection manner of each switch 21 with the first interface 31 and the second interface 32 is not limited thereto, and can be designed according to actual needs.

[0060] Optionally, Figure 3 Another structure of a test adapter provided by the embodiment of the utility model is shown in the figure, Figure 3 As shown, a plurality of switches 21 form a plurality of switch groups 2101, and each switch group 2101 includes at least one switch 21; the first end of each switch 21 is respectively electrically connected with a corresponding first interface 31, and in the same switch group 2101, the second end of each switch 21 is electrically connected with the same second interface 32, so that a switch 21 is connected in series in the connection path between each second interface 32 and the corresponding electrically connected first interface 31, and based on the gating signal output by the adapter controller 1, each second interface 32 can be electrically connected to part of the first interfaces 31, so that the connection manner between each first interface 31 and each second interface 32 is more flexible.

[0061] In an exemplary embodiment,Figure 3 For example, 4 switches 21 constitute 2 switch groups 2101, the 2 switch groups 2101 are respectively a first switch group 2102 and a second switch group 2103, when the switch in the first switch group 2102 and the first first interface 311 are in an electrically connected state, the first first interface 311 and the first second interface 321 form a conductive path; when the switch in the first switch group 2102 and the second first interface 312 are in an electrically connected state, the second first interface 312 and the first second interface 321 form a conductive path. In this way, by controlling the on and off state of each switch in the first switch group 2102, the connection path between the first first interface 311 and the first second interface 321, and the second first interface 312 and the first second interface 321 can be switched.

[0062] It should be noted that, Figure 3 Only the case that 4 switches constitute 2 switch groups 2101, and each switch group 2101 includes two switches 21 is exemplarily shown, and this is not limited. In the embodiment, the number of switch groups 2101 constituted by a plurality of switches 21 and the number of switches 21 included in each switch group 2101 can be limited according to actual needs.

[0063] Optionally, Figure 4 Another structure diagram of the test adapter plate provided by the embodiment of the utility model is shown in Figure 4 The plurality of switches 21 include a plurality of first switches 211 and a plurality of second switches 212; the first end of the first switch 211 is electrically connected with a first interface 31; the second end of the first switch 211 is electrically connected with the first end of a second switch 212; the second end of the second switch 212 is electrically connected with a second interface 32.

[0064] It should be noted that, Figure 4 Only the case that the first end of the first switch 211 is electrically connected with a first interface 31, the second end of the first switch 211 is electrically connected with the first end of a second switch 212, and the second end of the second switch 212 is electrically connected with a second interface 32 is shown, and this is not limited to the connection mode of each first switch 211 and each second switch 212. In the embodiment, the number of first ends of the second switches 212 electrically connected with the second end of the first switch 211 is not limited, and can be designed according to actual needs.

[0065] Optionally, Figure 5 Another structure diagram of the test adapter plate provided by the embodiment of the utility model is shown in Figure 5As shown, the first end of each first switch 211 is electrically connected to each first interface 31 in one-to-one correspondence, the second end of each first switch 211 is electrically connected to the first node a, the first end of each second switch 212 is electrically connected to the first node a, and the second end of each second switch 212 is electrically connected to each second interface 32 in one-to-one correspondence, so that the state of each first switch 211 and each second switch 212 is controlled through the strobe signal output by the adapter plate controller 1, and each first interface 31 can be electrically connected to any second interface 32 through the first switch 211 and the second switch 212.

[0066] Optionally, Figure 6 Another structure diagram of the test adapter plate provided by the embodiment of the utility model is shown in Figure 5. Figure 6 As shown, the plurality of first switches 211 form M first switch groups 2111, and the plurality of second switches 212 form M second switch groups 2121; the first end of each first switch 211 is electrically connected to each first interface 31 in one-to-one correspondence; the second end of each first switch 211 in the i-th first switch group 2111 is electrically connected to the first end of each second switch 212 in the j-th second switch group 2121; and the second end of each second switch 212 is electrically connected to each second interface 32 in one-to-one correspondence.

[0067] Wherein, M is an integer greater than or equal to 2, i and j are integers from 1 to M, and i and j can be equal or not equal.

[0068] The first switch group 2111 includes at least one first switch 211, and the second switch group 2121 includes at least one second switch 212. The state of each first switch 211 and each second switch 212 is controlled through the strobe signal output by the adapter plate controller 1, and the first interface 31 electrically connected to the same first switch group 2111 can be electrically connected to the corresponding plurality of second switches 212 through the first switch group 2111 and the second switch group 2121.

[0069] It should be noted that, Figure 6 It is only exemplarily shown that 5 first switches 211 form 2 first switch groups 2111, and 5 second switches 212 form 2 second switch groups 2121, which does not limit the number of first switches 211 and second switches 212, and the number of first switch groups 2111 and second switch groups 2121. In the embodiment, the number of first switch groups 2111, the number of second switch groups 2121, the number of first switches 211 in the first switch group 2111, and the number of second switches 212 in the second switch group 2121 are not limited, and can be designed according to actual needs.

[0070] In an optional embodiment, referring to Figures 2-6As shown, the test adapter 100 further comprises a circuit board 4; the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 are arranged on the circuit board 4 and electrically connected through the circuit board 4, so that the integration of the test adapter 100 can be improved, and the volume of the test adapter 100 can be reduced.

[0071] Wherein, the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 are electrically connected through the circuit board 4 can be understood as that the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 are electrically connected through the metal wiring and the metal conductive hole on the circuit board 4.

[0072] It should be noted that when the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 are electrically connected through the circuit board 4, their positions in the circuit board 4 can be arranged according to actual conditions. In an exemplary embodiment, if the number of components of the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 is large, each component can be dispersedly arranged on the front and back surfaces of the circuit board 4, so that the integration of the test adapter 100 can be further improved. In other exemplary embodiments, if the number of components of the adapter controller 1, each switch 21, each first interface 31 and each second interface 32 is small, each component can be arranged on only one side surface of the circuit board 4, so that the thickness of the test adapter 100 can be reduced. It should be understood that various forms of processes shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solution of the present application can be achieved, which is not limited herein.

[0073] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip testing apparatus characterized by comprising: The application relates to a test system, which comprises a main control module, a test platform, an environment control device, a test adapter board and a plurality of test instruments. The main control module comprises a test connection control end, a plurality of test signal interaction ends, a test environment control end and a test start control end; the test platform comprises a test input end, a plurality of test input interfaces and a plurality of test output interfaces; and the test adapter board comprises a plurality of first interfaces and a plurality of second interfaces. The test environment control end is electrically connected with the control end of the environment control device; the test start control end is electrically connected with the test input end; a plurality of the test input interfaces are electrically connected with a chip to be tested; the test connection control end is electrically connected with the control end of the test adapter board; each test signal interaction end is connected with a signal interaction end of each test instrument; each first interface is electrically connected with a corresponding test output interface, and each second interface is electrically connected with a corresponding test instrument. The test adapter board is used for controlling the connection state between each test output interface and each test instrument. The environment control device is used for controlling the environmental parameters of the test platform. The test adapter board further comprises an adapter board controller and a plurality of switches; the adapter board controller comprises a connection instruction receiving end and a strobe signal output end.

2. The chip testing apparatus according to claim 1, wherein The connection instruction receiving end is electrically connected with the control end of the test adapter board, and the strobe signal output end is electrically connected with the control end of each switch. At least one switch is arranged in the connection passage between one first interface and one second interface. The plurality of switches form a plurality of switch groups; each switch group comprises at least one switch.

3. The chip testing apparatus according to claim 2, wherein The first end of each switch is electrically connected with a corresponding first interface. In the same switch group, the second end of each switch is electrically connected with the same second interface. The plurality of switches comprise a plurality of first switches and a plurality of second switches.

4. The chip testing apparatus according to claim 2, wherein The first end of the first switch is electrically connected with one first interface; the second end of the first switch is electrically connected with the first end of at least one second switch; and the second end of the second switch is electrically connected with one second interface. The first end of each first switch is electrically connected with a corresponding first interface; the second end of each first switch is electrically connected with a first node; the first end of each second switch is electrically connected with the first node; and the second end of each second switch is electrically connected with a corresponding second interface.

5. The chip testing apparatus according to claim 4, wherein The plurality of first switches form M first switch groups, and the plurality of second switches form M second switch groups; the first end of each first switch is electrically connected with a corresponding first interface; the second end of each first switch in the ith first switch group is electrically connected with the first end of each second switch in the jth second switch group; and the second end of each second switch is electrically connected with a corresponding second interface; wherein M is an integer greater than or equal to 2, i and j are integers from 1 to M.

6. The chip testing apparatus according to claim 4, wherein The main control module comprises an upper computer.

7. The chip testing apparatus according to claim 1, wherein The test adapter board further comprises a circuit board.

8. The chip testing apparatus according to claim 2, wherein ​ The adapter plate controller, the switches, the first interfaces and the second interfaces are respectively arranged on the circuit board and electrically connected through the circuit board.

9. The chip testing apparatus according to claim 1, wherein The environment control device comprises a heating device, a refrigeration device and a temperature sensor; the heating device, the refrigeration device and the temperature sensor are electrically connected with the main control module.

10. The chip testing apparatus according to claim 9, wherein The environment control device further comprises a test box; the heating device, the refrigeration device, the temperature sensor and the test platform are located in the test box.

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