Low-voltage direct-current power supply anti-backflow circuit

Abstract

The utility model discloses an anti-backflow circuit for a low-voltage direct-current power supply. The core of the circuit comprises a P-MOS tube Q1, triodes Q2 / Q3 back to back, a current-limiting resistor and RC elements, wherein the output ends of the RC elements are connected in parallel. When the input end Vin of the power supply is normal, the Q3 is conducted, the Q2 is cut off, the grid voltage of the Q1 is negative and conducted, and current flows to the output end Vout from the input end Vin of the power supply through the P-MOS tube Q1; when the input end Vin of the power supply is powered off, the Q2 is switched on, the Q3 is switched off, the grid electrode of the Q1 is pulled up to the potential Vout to be switched off, the Vin and the Vout are thoroughly isolated, and backflow is prevented. A traditional diode or a mechanical switch is replaced by the low conduction voltage drop characteristic of the P-MOS tube, loss and heating are remarkably reduced, and meanwhile the problem of contact sparking oxidation is avoided through rapid logic control of the triode. The circuit has the advantages of low cost, high reliability and low power consumption, and is suitable for low-voltage direct current scenes such as machine tool equipment and solar energy systems needing backflow prevention.

Description

Technical Field

[0001] This utility model relates to the field of power supply backflow prevention technology, and in particular to a low-voltage DC power supply backflow prevention circuit. Background Technology

[0002] In low-voltage DC power supply systems, reverse current flow is a common and serious problem. Reverse current flow typically occurs when the power input is disconnected or the voltage drops below the output, causing current to flow back from the output to the input. This phenomenon not only damages power supply equipment but can also lead to decreased system efficiency, increased heat generation, and even safety hazards. Traditional reverse current protection solutions mainly use diodes or mechanical switches. However, diode solutions suffer from significant power loss and heat generation due to their high forward voltage drop (typically 0.3-0.7V), especially noticeable in low-voltage scenarios. While mechanical switches avoid the voltage drop problem of diodes, they are prone to contact arcing and oxidation upon disconnection, affecting circuit reliability and lifespan. Furthermore, the problem of slow, small-current reverse current flow is difficult to completely resolve in traditional solutions, further limiting system stability and safety. Therefore, a low-loss, high-efficiency, and reliable reverse current protection circuit is urgently needed to address the reverse current problem in low-voltage DC power supply systems. Utility Model Content

[0003] The purpose of this invention is to provide a low-voltage DC power supply anti-backflow circuit, which solves the aforementioned problem of power supply backflow.

[0004] This utility model is achieved through the following technical solution:

[0005] A low-voltage DC power supply anti-reverse current circuit includes a power supply, a first detection circuit, a second detection circuit, a control circuit, and a P-MOS transistor Q1. In this circuit, the input terminal of the power supply is connected to the drain of the P-MOS transistor Q1 and also connected to one end of the first detection circuit, forming a parallel connection. The source of the P-MOS transistor is connected to the output terminal, and its gate is connected to one end of the control circuit, forming a series connection. The other end of the control circuit is connected to the other ends of the first and second detection circuits, forming a parallel connection. The second detection circuit is also connected to the output terminal.

[0006] Furthermore,

[0007] The control circuit includes transistors Q2 and Q3, which are arranged back-to-back. The bases of transistors Q2 and Q3 are connected to the first detection circuit and the second detection circuit, respectively. The bases of transistors Q2 and Q3 are connected together. The emitter of transistor Q3 is directly connected to the input terminal Vin of the power supply. The emitter of transistor Q2 is connected to the source of P-MOS transistor Q1.

[0008] Furthermore,

[0009] Both the first detection circuit and the second detection circuit include a current-limiting resistor, which is connected in series in the collector circuit of transistors Q2 and Q3 and grounded, respectively, to limit the base current.

[0010] Furthermore,

[0011] The drain of the P-MOS transistor Q1 is connected to the input terminal Vin of the power supply, and the source is connected to the output terminal Vout. The source is also connected to the emitter of the transistor Q2. The gate of the P-MOS transistor is controlled by the collector terminal of the transistor Q2.

[0012] Furthermore,

[0013] When the input terminal Vin of the power supply is energized, current can flow through the P-MOS transistor to the output terminal Vout. When it is de-energized, the input terminal Vin and the output terminal Vout of the power supply are isolated.

[0014] The beneficial effects of this utility model are:

[0015] 1. Utilizing the characteristics of P-MOS transistors and back-to-back transistors, the P-MOS transistors are automatically cut off to completely isolate the input and output, effectively preventing current from flowing back from the output to the input and protecting the power output terminals.

[0016] 2. Compared with traditional diode anti-backflow solutions, this circuit greatly reduces voltage drop loss, lowers the possibility of circuit overheating, improves circuit efficiency, and maintains low power consumption. It solves the problem of arcing and oxidation at the contact point when disconnecting in traditional mechanical anti-backflow circuits, enhances circuit stability and service life, effectively reduces circuit overheating damage, and increases circuit reliability. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 This is a schematic diagram of the modules of this utility model;

[0019] Figure 2 This is a circuit diagram of the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the implementation of the present invention is not limited thereto.

[0021] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "have," "install," "connect," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0022] Example

[0023] See Figures 1 to 2 :

[0024] A low-voltage DC power supply anti-reverse current circuit includes a power supply, a first detection circuit, a second detection circuit, a control circuit, and a P-MOS transistor Q1. In this circuit, the input terminal of the power supply is connected to the drain of the P-MOS transistor Q1 and also connected to one end of the first detection circuit, forming a parallel connection. The source of the P-MOS transistor is connected to the output terminal, and its gate is connected to one end of the control circuit, forming a series connection. The other end of the control circuit is connected to the first detection circuit and the second detection circuit, forming a parallel connection. The second detection circuit is also connected to the source of the P-MOS transistor.

[0025] Furthermore,

[0026] The control circuit includes transistors Q2 and Q3, which are arranged back-to-back. The bases of transistors Q2 and Q3 are connected to the first detection circuit and the second detection circuit, respectively. The bases of transistors Q2 and Q3 are connected together. The emitter of transistor Q3 is directly connected to the input terminal Vin of the power supply. The emitter of transistor Q2 is connected to the source of P-MOS transistor Q1.

[0027] In one embodiment, two transistors and a P-MOS transistor are used to replace the traditional diodes for back-to-back protection. The two transistors are arranged back-to-back so that the bases of transistors Q2 and Q3 are opposite each other, making it easier to connect the bases of transistors Q2 and Q3 and avoiding circuit clutter. At the same time, the back-to-back structure can quickly switch the state of transistors Q2 and Q3, ensuring rapid isolation of the power input terminal Vin and the output terminal Vout when Vin is de-energized, preventing back-to-back. It also utilizes the fast response characteristics of transistors to achieve millisecond-level switching, preventing electric shock, arcing or oxidation.

[0028] Furthermore,

[0029] Both the first detection circuit and the second detection circuit include a current-limiting resistor, which is connected in series in the collector circuits of transistors Q2 and Q3 and grounded, respectively, to limit the current.

[0030] To prevent the transistor from burning out due to excessive base current, and to limit the current so that the transistor operates in the saturation or cutoff region, thereby enhancing the reliability of the transistor's switching state.

[0031] Furthermore,

[0032] The drain of the P-MOS transistor Q1 is connected to the input terminal Vin of the power supply, and the source is connected to the output terminal Vout. The source is also connected to the emitter of the transistor Q2. The gate of the P-MOS transistor Q1 is controlled by the collector terminal of the transistor Q2.

[0033] The P-MOS transistor achieves conduction isolation of the main current path through collector control of transistor Q2;

[0034] The P-MOS transistor has an extremely low on-resistance and a voltage drop of only millivolts, which is much lower than that of traditional diodes, thus reducing energy loss and heat generation.

[0035] Furthermore,

[0036] When the input terminal Vin of the power supply is energized, current can flow through the P-MOS transistor to the output terminal Vout. When it is de-energized, the input terminal Vin and the output terminal Vout of the power supply are isolated.

[0037] In one embodiment, one end of its output terminal Vout is connected to the load device, and the other end is grounded and has a capacitor C. The capacitor C is placed between the output terminal Vout and the ground. At the same time, a resistor is placed next to the capacitor C, which is connected in parallel with the capacitor C. The line where the resistor is located is also grounded. The capacitor C and the resistor form an RC circuit.

[0038] This RC circuit serves two purposes, as follows:

[0039] Filtering function: This RC circuit can filter out high-frequency noise and ensure stable output voltage;

[0040] Protection function: When the power input Vin is disconnected, this RC circuit can discharge quickly to prevent drastic voltage fluctuations.

[0041] It is connected in parallel with capacitor C, between Vout and ground.

[0042] Filtering function: The RC circuit filters out high-frequency noise to ensure stable output voltage.

[0043] Protection function: In the power-off state, the RC circuit helps to discharge quickly and prevent voltage fluctuations.

[0044] The principle of this utility model is as follows:

[0045] When the power input terminal Vin is energized, it is in normal power supply mode. In this mode, transistor Q3 is turned on, and the voltage at the emitter of transistor Q3 is the power supply at the input terminal Vin. The voltage at its base is the emitter-junction voltage drop of transistor Q3. The collector of transistor Q3 is grounded through a current-limiting resistor. At this time, the base voltage of transistor Q3 is higher than the base voltage of transistor Q2 because the base of transistor Q2 forms a voltage drop through the parasitic diode path of P-MOS transistor Q1, thus causing transistor Q2 to be turned off. When transistor Q2 is in the off state, the gate of P-MOS transistor Q1 is grounded through its pull-down resistor, thereby turning on P-MOS transistor Q1.

[0046] Under normal power supply conditions, the current path is as follows: the current flows from the input terminal Vin of the power supply to the turned-on P-MOS transistor Q1, and then from the P-MOS transistor Q1 to the output terminal, thereby supplying power to the load device.

[0047] When the power supply output terminal Vin is de-energized, in this state, transistor Q2 is on, transistor Q3 is off, and P-MOS transistor Q1 is off. After the power supply output terminal Vin is de-energized, and because of the on-resistance in P-MOS transistor Q1, the voltage at the output terminal Vout is applied to the base of transistor Q3 through this on-resistance. Therefore, the base voltage of transistor Q3 is provided by the output terminal Vout through the on-resistance of P-MOS transistor Q1 and the emitter junction voltage drop, and the emitter voltage of transistor Q3 is zero. The base voltage of transistor Q2... To provide voltage drop across the output terminal Vout and emitter junction, since the base voltage of transistor Q3 is lower than that of transistor Q2, transistor Q3 is cut off and transistor Q2 is turned on. After transistor Q2 is turned on, the gate potential of P-MOS transistor Q1 is pulled up to the output terminal Vout potential, making the voltage difference between the gate and source of P-MOS transistor Q1 approach zero, thereby turning off P-MOS transistor Q1. This completely isolates the device between the power supply input terminal Vin and the output terminal Vout, preventing current backflow at the output terminal.

[0048] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above description is only a specific embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A low-voltage DC power supply anti-reverse current circuit, characterized in that, The circuit includes a power supply, a first detection circuit, a second detection circuit, a control circuit, and a P-MOS transistor Q1. In this circuit, the input terminal of the power supply is connected to the drain of the P-MOS transistor and also to one end of the first detection circuit, forming a parallel connection. The source of the P-MOS transistor Q1 is connected to the output terminal, and its gate is connected to one end of the control circuit, forming a series connection. The other end of the control circuit is connected to the other ends of the first and second detection circuits, forming a parallel connection. The second detection circuit is also connected to the output terminal.

2. The low-voltage DC power supply anti-reverse current circuit according to claim 1, characterized in that, The control circuit includes transistors Q2 and Q3, which are arranged back-to-back. The bases of transistors Q2 and Q3 are connected to the first detection circuit and the second detection circuit, respectively. The bases of transistors Q2 and Q3 are connected together. The emitter of transistor Q3 is directly connected to the input terminal Vin of the power supply. The emitter of transistor Q2 is connected to the source of P-MOS transistor Q1.

3. The low-voltage DC power supply anti-reverse current circuit according to claim 2, characterized in that, Both the first detection circuit and the second detection circuit include a current-limiting resistor, which is connected in series in the collector circuits of transistors Q2 and Q3 and grounded, respectively, to limit the current.

4. The low-voltage DC power supply anti-reverse current circuit according to claim 2, characterized in that, The drain of the P-MOS transistor Q1 is connected to the input terminal Vin of the power supply, and the source is connected to the output terminal Vout. The source is also connected to the emitter of the transistor Q2. The gate of the P-MOS transistor is controlled by the collector terminal of the transistor Q2.

5. A low-voltage DC power supply anti-reverse current circuit according to claim 2, characterized in that, When the input terminal Vin of the power supply is energized, current can flow through the P-MOS transistor to the output terminal Vout. When it is de-energized, the input terminal Vin and the output terminal Vout of the power supply are isolated.

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