Quantum dot element

Abstract

A quantum dot device includes a substrate. A gate dielectric layer is over the substrate. A first plunger gate structure and a second plunger gate structure are over the gate dielectric layer, where in an upper view, the first plunger gate structure and the second plunger gate structure are arranged in the form of concentric circles, and wherein each of the first plunger gate structure and the second plunger gate structure includes a ring structure and a plurality of plunger gates extending downward from the ring structure. A plurality of barrier gates are over the gate dielectric layer, with each of the plunger gates of the first plunger gate structure and the second plunger gate structure laterally between adjacent two of the barrier gates in a cross-sectional view.

Description

Technical Field

[0001] This disclosure relates to a quantum dot device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have created several generations of ICs, each with smaller and more complex circuits than the previous one. Throughout the evolution of ICs, functional density (such as the number of interconnecting elements per chip) has continuously increased, while device size (such as the smallest component that a process can manufacture) has continuously shrunk. Size reduction generally provides increased production efficiency and reduced waste. However, size reduction also increases the complexity of processes and manufacturing. Therefore, manufacturing reliable semiconductor devices in increasingly smaller sizes remains a major challenge. Utility Model Content

[0003] In some embodiments disclosed herein, a quantum dot device includes a substrate. A plurality of first plunger gates are located on the substrate and arranged in a ring. A plurality of second plunger gates are located on the substrate and arranged in a ring. A first annular barrier gate is located on the substrate and positioned between the first and second plunger gates.

[0004] In some embodiments disclosed herein, a quantum dot device includes a substrate. A gate dielectric layer is located above the substrate. A first plunger gate structure and a second plunger gate structure are located above the gate dielectric layer, wherein, in a top view, the first and second plunger gate structures are arranged in a concentric circle configuration, and each of the first and second plunger gate structures includes an annular structure and a plurality of plunger gates extending downward from the annular structure. A plurality of barrier gates are located above the gate dielectric layer, wherein, in a cross-sectional view, each of the plunger gates of the first and second plunger gate structures is laterally located between adjacent barrier gates.

[0005] In some embodiments disclosed herein, a quantum dot device includes a substrate. A plurality of first plunger gates are located on the substrate and arranged in a ring. A plurality of second plunger gates are located on the substrate and arranged in a ring. A first annular barrier gate is located on the substrate and positioned between the first and second plunger gates. A plurality of first linear barrier gates are located on the substrate, wherein each of the first linear barrier gates separates a corresponding pair of the first plunger gates. Attached Figure Description

[0006] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 9C This diagram illustrates different stages of a method for manufacturing quantum dot devices according to some embodiments of this disclosure.

[0008] Figure 10A This is a top view of a quantum dot element representing a portion of the embodiments disclosed herein;

[0009] Figure 10B This is a cross-sectional view of a quantum dot device according to some embodiments of this disclosure;

[0010] Figure 11 These are simulation results for some embodiments disclosed herein.

[0011] [Symbol Explanation]

[0012] 100:Substrate

[0013] 102: Source / Drain Region

[0014] 105: Gate dielectric layer

[0015] 110A, 110B, 110C, 110D: Barrier gate

[0016] 111: Gate layer

[0017] 130A, 130B, 130C, 130D: Barrier gate

[0018] 120: Gate dielectric layer

[0019] 131: Gate layer

[0020] 140: Gate dielectric layer

[0021] 150A, 150B, 150C, 150D: Plunger gate structure

[0022] 150A_P, 150B_P, 150C_P, 150D_P: Plunger gate

[0023] 150A_R, 150B_R, 150C_R, 150D_R: Ring structure

[0024] 151: Gate layer

[0025] 160: Passivation layer

[0026] 171, 172, 173, 174, 175: Contact elements

[0027] 180: Passivation layer

[0028] BB, CC: lines

[0029] CE: Center

[0030] d: Spacing

[0031] M1, M2: Quantum dot elements

[0032] O1, O2, O3, O4, O5: Open

[0033] R: radius

[0034] R1, R2, R3, R4: Cavities

[0035] t QD ,t ox ,t g :thickness

[0036] W BG W PG :width Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define relationships between the various embodiments and / or configurations discussed.

[0038] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another element or feature. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0039] Quantum computing can solve difficult problems in traditional computing by leveraging the quantum entanglement and superposition properties of quantum bits. Silicon-based spin qubits are a potential candidate due to their long decoherence within silicon-rich quantum dots and their compatibility with very large-scale integration (VLSI) technology. In practical applications, the number of qubits needs to be as large as possible. Therefore, the architecture of qubits is crucial for large-size qubits. 1D linear qubit arrays are currently widely used for large-size qubits. In the embodiments disclosed herein, a novel 2D architecture qubit array is proposed, enabling the application of qubit arrays to large-size spin qubits in VLSI.

[0040] Figures 1A to 9C This diagram illustrates different stages of a method for manufacturing quantum dot devices according to some embodiments of this disclosure. In detail, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A This is a top view of a quantum dot element. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B For along Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A A cross-sectional view of line BB. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C For along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A A cross-sectional view of line CC. Figure 6D for Figure 6AA schematic diagram of the plunger gate structure. It should be noted that, for simplicity, some components in the cross-sectional view are not shown in the top view.

[0041] Although Figures 1A to 9C This is a reference diagram for a method, but it should be understood that... Figures 1A to 9C The structure is not limited to being formed using this method, and can be formed independently of this method. Although Figures 1A to 9C A series of operations have been described; however, it should be understood that these operations are not limited in their order. Therefore, in some embodiments, the order of these operations may be interchanged in other embodiments, and this method may also be applied to other structures. In some embodiments, the described operations or steps may be omitted in whole or in part.

[0042] refer to Figure 1A and Figure 1B The diagram illustrates a quantum dot element M1. The quantum dot element M1 includes a substrate 100. The substrate 100 can be a semiconductor substrate, such as a bulk semiconductor, a silicon-on-insulator (SiI) substrate, or the like. Generally, a SiI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, a silicon substrate, or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 100 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0043] Source / drain regions 102 are formed in substrate 100. Source / drain regions 102 may be doped regions within substrate 100 and may be formed via suitable processes, such as ion implantation. Dopants may include p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants and combinations thereof. In some embodiments using electrons as carriers, source / drain regions 102 may be n-type doped regions, while substrate 100 may be a p-type substrate. Conversely, when holes are used as carriers, source / drain regions 102 may be p-type doped regions, while substrate 100 may be an n-type substrate.

[0044] A gate dielectric layer 105 is formed above the substrate 100. The gate dielectric layer 105 may contain a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, or hafnium dioxide-alumina (HfO2). 23Alloys or other suitable materials. The gate dielectric layer 105 can be formed using appropriate deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes.

[0045] A gate layer 111 is formed above the gate dielectric layer 105. In some embodiments, the gate layer 111 may comprise tungsten (W), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), etc. In other embodiments, the gate layer 111 may comprise titanium (Ti), titanium nitride (TiN), etc. The gate layer 111 may be formed using a suitable deposition process, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0046] refer to Figure 2A and Figure 2B The gate layer 111 is patterned to form mutually separated barrier gates 110A and 110B. For example... Figure 2A As shown in the top view, each of barrier gates 110A and 110B includes an annular top profile (or a circular top profile). In some embodiments, barrier gates 110A and 110B are arranged in concentric circles relative to the center CE, wherein barrier gate 110B surrounds barrier gate 110A. In some embodiments, barrier gates 110A and 110B may also be referred to as annular barrier gates.

[0047] In some embodiments, a suitable lithography process can be used to pattern the gate layer 111. For example, a patterned mask (e.g., photoresist) can be formed over the gate layer 111. The patterned mask may include openings defining the contours of barrier gates 110A and 110B. An etching process is performed to remove portions of the gate layer 111 through the openings of the patterned mask. Once the etching process is complete, the patterned mask can be removed. In some embodiments, the etching process may be a reactive ion etching process or other suitable etching process.

[0048] refer to Figure 3A and Figure 3BA gate dielectric layer 120 is formed above the substrate 100 and extends along the underlying structure. Specifically, the gate dielectric layer 120 is deposited conformally such that it is formed along the top surface of the gate dielectric layer 105 and along the top surface and opposite sidewalls of each barrier gate 110A and 110A. In some embodiments, the gate dielectric layer 120 may comprise oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), etc. The gate dielectric layer 120 may also comprise high-k dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, and other suitable materials. The gate dielectric layer 120 can be formed using a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes.

[0049] A gate layer 131 is formed above the gate dielectric layer 120. For example, the gate layer 131 fills a circular region within the barrier gate 110A, an annular region between the barrier gates 110A and 110B, and a region outside the barrier gate 110B. In some embodiments, the gate layer 131 is deposited such that the top surface of the gate layer 131 is higher than the top surfaces of the barrier gates 110A and 110B. In some embodiments, the top surfaces of the barrier gates 110A and 110B are lower than the top surface of the gate layer 131 and higher than the bottom surface of the gate layer 131.

[0050] In some embodiments, the gate layer 131 may be made of a conductive material, such as a metal, and is therefore also referred to as a metal layer. In some embodiments, the gate layer 131 may comprise tungsten (W), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), etc. In other embodiments, the gate layer 131 may comprise titanium (Ti), titanium nitride (TiN), etc. The gate layer 131 may be formed using a suitable deposition process, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0051] refer to Figure 4A , Figure 4B and Figure 4C Gate layer 131 is patterned to form barrier gates 130A and 130B. Here, barrier gate 130A can be considered as the portion of patterned gate layer 131 extending from the center CE to barrier gate 110A. Barrier gate 130B can be the portion of patterned gate layer 131 extending from barrier gate 110A to barrier gate 110B. In some embodiments, barrier gates 130A are connected to each other at the center CE. Figure 4AAs shown in the top view, each of the barrier gates 130A and 130B includes a linear top profile (or a strip-shaped top profile). In some embodiments, each of the barrier gates 130A and 130B is arranged radially relative to the center CE. Therefore, the barrier gates 130A and 130B may also be referred to as radial gates or linear gates.

[0052] In some embodiments, a portion of the barrier gate 130B is connected to the barrier gate 130A, while a portion of the barrier gate 130B is not connected to the barrier gate 130A. Taking Figure 4 as an example, if one barrier gate 130B is connected to a corresponding barrier gate 130A, then the two barrier gates 130B on either side of this barrier gate 130B are not connected to the barrier gate 130A. Similarly, if one barrier gate 130B is not connected to a barrier gate 130A, then the two barrier gates 130B on either side of this barrier gate 130B are connected to the corresponding barrier gate 130A. Therefore, the number of barrier gates 130B is greater than the number of barrier gates 130A.

[0053] After forming barrier gates 130A and 130B, barrier gates 110A and 110B, together with barrier gates 130A and 130B, define a plurality of cavities R1 and R2. Cavities R1 are arranged in a ring relative to the center CE, and cavities R2 are arranged in a ring relative to the center CE. Specifically, cavities R1 are arranged along a first ring, while cavities R2 are arranged along a second ring surrounding the first ring. In some embodiments, the first ring and the second ring are arranged concentrically relative to the center CE.

[0054] like Figure 4A As shown in the top view, each cavity R1 is defined by two adjacent barrier gates 130A and 110A. Therefore, each cavity R1 has a circular sector top profile. That is, the top profile of each cavity R1 is defined by three boundaries. On the other hand, each cavity R2 is defined by barrier gate 110A, barrier gate 110B, and two adjacent barrier gates 130B. Therefore, each cavity R2 has an annular sector top profile. That is, the top profile of each cavity R2 is defined by four boundaries.

[0055] refer to Figure 5A , Figure 5B and Figure 5CA gate dielectric layer 140 is formed over the substrate 100 and extends along the underlying structure. Specifically, the gate dielectric layer 140 is deposited conformally such that it extends along the top surface of the gate dielectric layer 120 and along the top surface and opposite sidewalls of each barrier gate 130A and 130A. In some embodiments, the gate dielectric layer 140 may comprise oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), etc. The gate dielectric layer 120 may also comprise a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, and other suitable materials. The gate dielectric layer 140 may be formed using suitable deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes.

[0056] A gate layer 151 is formed over a gate dielectric layer 140. In some embodiments, the gate layer 151 is deposited such that the top surface of the gate layer 151 is higher than the top surfaces of the barrier gates 110A and 110B. In some embodiments, the top surfaces of the barrier gates 110A and 110B are lower than the top surface of the gate layer 151 and higher than the bottom surface of the gate layer 151. Similarly, the top surfaces of the barrier gates 130A and 130B are lower than the top surface of the gate layer 151 and higher than the bottom surface of the gate layer 151.

[0057] In some embodiments, gate layer 151 may be made of a conductive material such as a metal, and is therefore also referred to as a metal layer. In some embodiments, gate layer 151 may comprise tungsten (W), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), etc. In other embodiments, gate layer 151 may comprise titanium (Ti), titanium nitride (TiN), etc. Gate layer 151 may be formed using a suitable deposition process, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, gate layers 111, 131, and 151 may comprise the same conductive material.

[0058] refer to Figure 6A , Figure 6B , Figure 6C and Figure 6D Gate layer 151 is patterned to form mutually separated plunger gate structures 150A and 150B. Plunger gate structures 150A and 150B are arranged concentrically with respect to the center CE, wherein plunger gate structure 150B surrounds plunger gate structure 150A. In some embodiments, plunger gate structures 150A and 150B can be made of a dielectric material (such as...) Figure 6B and Figure 6C The gate dielectric layers 120 and 140 shown are electrically isolated from the barrier gates 110A, 110B, 130A and 130B.

[0059] Figure 6D This is a schematic diagram of a plunger gate structure 15A, where each plunger gate structure 150A includes an annular structure 150A_R and a plurality of plunger gates 150A_P extending downward from the annular structure 150A_R. Specifically, the plunger gate 150A_P can be considered as a portion of the gate layer 151 filling the cavity R1, and the annular structure 150A_R can be considered as the portion of the patterned gate layer 151 above the plunger gates 150A_P. The annular structure 150A_R has an annular top profile spanning each barrier gate 130A and is connected to the plunger gates 150A_P filled in the cavity R1. That is, the plunger gates 150A_P can be electrically connected to each other through the annular structure 150A_R.

[0060] Referring to the plunger gate structure 150B, each plunger gate structure 150B includes an annular structure 150B_R and a plurality of plunger gates 150B_P extending downward from the annular structure 150B_R. Specifically, the plunger gate 150B_P can be considered as a portion of the gate layer 151 filling the cavity R2, while the annular structure 150B_R can be considered as the portion of the patterned gate layer 151 above the plunger gate 150B_P. The annular structure 150B_R has an annular top profile spanning each barrier gate 130B and can be connected to the plunger gates 150B_P filled in the cavity R2. That is, the plunger gates 150B_P can be electrically connected to each other through the annular structure 150B_R.

[0061] Although not in Figure 6A The diagram is drawn in the image, but it should be noted that the plunger gate 150A_P filling the cavity R1 can inherit the contour of the corresponding cavity R1. Therefore, the plunger gate 150A_P can contain the same contour as the cavity R1. Figure 4A The top profile is similar to that of cavity R1. Similarly, the plunger gate 150B_P filling cavity R2 can inherit the profile of the corresponding cavity R2. Therefore, the plunger gate 150B_P can contain the same top profile as... Figure 4A The top profile of cavity R2 is similar. It is worth noting that although cavities R1 and R2 contain gate dielectric layers 120 and 140, these layers are deposited using a conformal deposition method. Therefore, gate dielectric layers 120 and 140 do not affect the profiles of cavities R1 and R2 defined by barrier gates 110A and 110B and barrier gates 130A and 130B. The description of the profiles of cavities R1 and R2 has been discussed previously and will not be repeated for the sake of brevity.

[0062] refer to Figure 6A As can be seen, barrier gates 110A and 110B, the annular structure 150A_R of the plunger gate structure 150A, and the annular structure 150B_R of the plunger gate structure 150B all contain annular top contours (or circular top contours), arranged concentrically with respect to the center CE. Furthermore, barrier gate 110B surrounds the annular structure 150B_R of the plunger gate structure 150B, the annular structure 150B_R of the plunger gate structure 150B surrounds barrier gate 110A, and barrier gate 110A surrounds the annular structure 150A_R of the plunger gate structure 150A.

[0063] refer to Figure 7A , Figure 7B and Figure 7C A passivation layer 160 is formed over the substrate 100 and covers the plunger gate structures 150A and 150B. In some embodiments, the passivation layer 160 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The passivation layer 160 may be formed using, for example, CVD, ALD, spin-coated glass (SOG), or other suitable techniques. In some embodiments, the passivation layer 160 may comprise a dielectric material different from that of the gate dielectric layers 105, 120, and 140. For example, passivation layer 160 may contain silicon oxide (SiO2), while gate dielectric layers 105, 120 and 140 may contain aluminum oxide (Al2O3).

[0064] refer to Figure 8A , Figure 8B and Figure 8C The passivation layer 160 is patterned to form via openings O1, O2, O3, O4, and O5. In some embodiments, via opening O1 extends through the passivation layer 160 and exposes the top surface of the plunger gate structure 150A. Via opening O2 extends through the passivation layer 160, the gate dielectric layer 140, and the gate dielectric layer 120 and exposes the top surface of the barrier gate 110A. Via opening O3 extends through the passivation layer 160 and exposes the top surface of the plunger gate structure 150B. Via opening O4 extends through the passivation layer 160 and the gate dielectric layer 140 and exposes the top surface of the barrier gate 130B. Via opening O5 extends through the passivation layer 160 and the gate dielectric layers 120 and 140 and exposes the top surface of the barrier gate 110B (see reference). Figure 8C ).

[0065] Via openings O1, O2, O3, O4, and O5 can be formed, for example, by forming a patterned mask (e.g., photoresist) layer over passivation layer 160. The patterned mask may include openings defining the locations of via openings O1, O2, O3, O4, and O5. An etching process is performed to remove portions of passivation layer 160 and gate dielectric layers 120 and 140 exposed through the openings of the patterned mask, and the patterned mask is removed after the etching process is complete. In some embodiments, the etching process may be a reactive ion etching (RIE) process, or other suitable etching processes.

[0066] refer to Figure 9A , Figure 9B and Figure 9C Contacts 171, 172, 173, 174, and 175 are formed above the passivation layer 160 and fill corresponding via openings O1, O2, O3, O4, and O5. Specifically, contact 171 has a metal line portion above the passivation layer 160 and a via portion filling opening O1, such that contact 171 is electrically connected to the plunger gate structure 150A. Contact 172 has a metal line portion above the passivation layer 160 and a via portion filling opening O2, such that contact 172 is electrically connected to the barrier gate 110A. Contact 173 has a metal line portion above the passivation layer 160 and a via portion filling opening O3, such that contact 173 is electrically connected to the plunger gate structure 150B. Contact 174 each has a metal line portion above the passivation layer 160 and a via portion filling the corresponding opening O4, such that contact 174 is electrically connected to the corresponding barrier gate 130B. Contact 175 has a metal line portion located above passivation layer 160 and a through-hole portion filling opening O5, such that contact 175 is electrically connected to barrier gate 110B. In some embodiments, since some barrier gates 130A are connected to barrier gate 130B, barrier gate 130A can also be electrically connected to contact 174 through corresponding barrier gate 130B.

[0067] Contacts 171, 172, 173, 174, and 175 can be formed, for example, by forming a patterned mask (e.g., photoresist) layer over a passivation layer 160. The patterned mask may include openings that define the positions and outlines of contacts 171, 172, 173, 174, and 175. Conductive material is deposited over a substrate 100 and fills the openings of the patterned mask and the via openings O1, O2, O3, O4, and O5. Then, a stripping process is performed to remove the patterned mask. The remaining conductive material in the openings of the patterned mask and the via openings O1, O2, O3, O4, and O5 serves as contacts 171, 172, 173, 174, and 175.

[0068] In some embodiments, contacts 171, 172, 173, 174, and 175 may comprise gold (Au), chromium (Cr), copper (Cu), etc. Contacts 171, 172, 173, 174, and 175 may be formed using suitable deposition processes, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0069] After the contacts 171 to 175 are formed, a passivation layer 180 is formed over the passivation layer 160 and covers the contacts 171 to 175. The material of the passivation layer 180 is similar to that of the passivation layer 160, so it will not be described in detail.

[0070] Figure 10A This is a top view of a quantum dot element representing a portion of the embodiments disclosed herein. Figure 10B This is a cross-sectional view of a quantum dot device according to some embodiments of this disclosure. More specifically, Figure 10B It is along Figure 10A A cross-sectional view of line BB. It is worth noting that... Figure 10A and Figure 10B Some components and the front Figures 1A to 9C Similar to those discussed in the previous section, these elements are labeled with the same symbols, and for the sake of brevity, the relevant details will not be repeated.

[0071] Figure 10A and Figure 10B The embodiments differ from Figures 1A to 9C An example of [the example]. Wherein... Figure 10A and Figure 10B The quantum dot devices also include barrier gates 110C and 110D, barrier gates 130C and 130D, and plunger gate structures 150C and 150D.

[0072] Referring to barrier gates 110C and 110D, both barrier gates 110C and 110D include an annular top profile (or circular top profile), similar to barrier gates 110A and 110B as described above. In some embodiments, barrier gates 110A, 110B, 110C, and 110D are arranged concentrically with respect to the center CE, wherein barrier gate 110D surrounds barrier gate 110C, barrier gate 110C surrounds barrier gate 110B, barrier gate 110C surrounds barrier gate 110C, and barrier gate 110B surrounds barrier gate 110A. In some embodiments, barrier gates 110A to 110D may also be referred to as annular barrier gates.

[0073] Barrier gates 110C and 110D can be formed together with barrier gates 110A and 110B during the process of patterning gate layer 111, as follows: Figure 2A and Figure 2BAs described. After forming barrier gates 110A to 110D, a gate dielectric layer 120 is formed over the substrate 100 and along the exposed surfaces of the barrier gates 110A to 110D, as follows. Figure 3A and Figure 3B As described.

[0074] Please refer to barrier gates 130C and 130D. Barrier gate 130C extends from barrier gate 110B to barrier gate 110C, and barrier gate 130D extends from barrier gate 110C to barrier gate 110D. For example... Figure 10A As shown in the top view, each of the barrier gates 130C and 130D includes a linear top profile (or a strip-shaped top profile). In some embodiments, each barrier gate 130D and some barrier gates 130C are arranged radially relative to the center CE.

[0075] Barrier gates 130C and 130D can be formed together with barrier gates 130A and 130B during the process of patterning gate layer 131, such as... Figure 4A , Figure 4B and Figure 4C As discussed. After forming the barrier gates 130A to 130D, a gate dielectric layer 140 is formed over the substrate 100 and along the exposed surfaces of the barrier gates 130A to 130D, as... Figure 5A , Figure 5B and Figure 5C The discussion.

[0076] After forming barrier gates 130A to 130D, a plurality of cavities R1, R2, R3, and R4 are formed. Specifically, barrier gates 110B / 110C / 110D and barrier gates 130C / 130D together define cavities R3 and R4. Cavities R3 are arranged in a ring relative to the center CE, and cavities R4 are also arranged in a ring relative to the center CE. Specifically, cavities R3 are arranged along a third ring, and cavities R4 are arranged along a fourth ring surrounding the third ring.

[0077] like Figure 10AAs shown in the top view, barrier gate 130C is connected to a corresponding barrier gate 130B. However, one barrier gate 130B can be connected to a single barrier gate 130C, while another barrier gate 130B can be connected to two barrier gates 130C. This results in the cavity R3 having different top profiles. For example, a first portion of the cavity R3 is defined by two adjacent barrier gates 130C and 110C. The top profile of the first portion of the cavity R3 is defined by three sides and has a circular fan-shaped top profile. On the other hand, a second portion of the cavity R3 is defined by two adjacent barrier gates 130C, 110B, and 110C. The top profile of the second portion of the cavity R3 is defined by four sides and has an annular fan-shaped top profile.

[0078] Each cavity R4 is defined by a barrier gate 110C, a barrier gate 110D, and two adjacent barrier gates 130D. Therefore, each cavity R4 has an annular fan-shaped top profile. That is, the top profile of each cavity R4 is defined by four sides. In some embodiments, a portion of the barrier gate 130D is connected to the barrier gate 130C, while a portion of the barrier gate 130D is not connected to the barrier gate 130C.

[0079] The plunger gate structures 150A, 150B, 150C and 150D are arranged concentrically with respect to the center CE, wherein the plunger gate structure 150D surrounds the plunger gate structure 150C, the plunger gate structure 150C surrounds the plunger gate structure 150B, and the plunger gate structure 150B surrounds the plunger gate structure 150A.

[0080] The plunger gate structures 150C and 150D can be formed together with the plunger gate structures 150A and 150B during the process of patterning the gate layer 151, such as... Figure 6A , Figure 6B and Figure 6C As discussed. After forming the plunger gate structures 150A to 150D, a passivation layer 160 is formed over the substrate 100 and along the exposed surfaces of the plunger gate structures 150A to 150D, as... Figure 7A , Figure 7B and Figure 7C The discussion.

[0081] Referring to the plunger gate structure 150C, each plunger gate structure 150C includes an annular structure 150C_R and a plurality of plunger gates 150C_P extending downward from the annular structure 150C_R. Specifically, the plunger gate 150C_P can be considered as a portion of the gate layer 151 filling the cavity R3, and the annular structure 150C_R can be considered as a portion of the patterned gate layer 151 above the plunger gates 150C_P. The annular structure 150C_R has an annular top profile spanning each barrier gate 130C and can be connected to the plunger gates 150C_P filled in the cavity R3. That is, the plunger gates 150C_P can be electrically connected to each other through the annular structure 150C_R.

[0082] Referring to the plunger gate structure 150D, each plunger gate structure 150D includes a ring structure 150D_R ​​and a plurality of plunger gates 150D_P extending downward from the ring structure 150D_R. Specifically, the plunger gate 150D_P can be considered as a portion of the gate layer 151 filling the cavity R4, and the ring structure 150D_R ​​can be considered as the portion of the patterned gate layer 151 above the plunger gate 150D_P. The ring structure 150D_R ​​has an annular top profile intersecting each barrier gate 130D and can be connected to the plunger gates 150D_P filled in the cavity R4. That is, the plunger gates 150D_P can be electrically connected to each other through the ring structure 150D_R.

[0083] Although not in Figure 10A As shown in the diagram, it should be noted that the plunger gate 150C_P filling cavity R3 can inherit the contour of cavity R3. Therefore, the plunger gate 150C_P can have a top contour similar to the corresponding cavity R3. Similarly, the plunger gate 150D_P filling cavity R4 can inherit the contour of the corresponding cavity R4. Therefore, the plunger gate 150D_P can have a top contour similar to the corresponding cavity R4. It is worth noting that although cavities R1 to R4 have gate dielectric layers 120 and 140, the gate dielectric layers 120 and 140 are deposited using a conformal deposition method. Therefore, the gate dielectric layers 120 and 140 are not bounded by the contours of cavities R1 to R4 defined by barrier gates 110A to 110D and barrier gates 130A to 130D.

[0084] In the operation of the quantum dot element M2, plunger gates 150A_P to 150D_P define qubits (or quantum dots; QDs) in the substrate 100. In other words, the positions of the qubits are defined by barrier gates 110A to 110D and barrier gates 130A to 130D. The positions of the qubits correspond to the individual plunger gates 150A_P to 150D_P, therefore, the plunger gates 150A_P to 150D_P can also be referred to as qubits of the quantum dot element M2. The qubits of the quantum dot element M2 are arranged in a circular array on the central region of the substrate 100, and the source / drain regions 102 are located in the peripheral region of the substrate 100 surrounding the central region of the substrate 100. The plunger gates 150A_P to 150D_P can also be referred to as storage cells of the quantum dot element M2.

[0085] Reference Figure 10B A cross-sectional view. In some embodiments, the thickness H of the substrate 100 is in the range of about 500 μm to about 2000 μm. In some embodiments, the thickness t of the gate dielectric layers 105, 120, and 140 is... ox Within the range of approximately 5 nm to approximately 20 nm. In some embodiments, the height H of the barrier gates 130A to 130D and the plunger gates 150A_P to 150D_P is... G In the range of approximately 25 nm to approximately 50 nm. In some embodiments, the width W of the barrier gates 110A to 110D is... BG Width W of plunger gate 150A_P to 150D_P PG Within the range of approximately 20 nm to approximately 50 nm. In some embodiments, the thickness t of the dielectric layer (e.g., gate dielectric layer 140) located between the overlapping gates (e.g., barrier gate 130A and plunger gate structure 150A) is... g Within the range of approximately 5 nm to approximately 20 nm. In some embodiments, the critical gate spacing t between the two plunger gates (e.g., plunger gates 150A_P and 150B_P) is... crit It can be greater than W PG +2t ox In some embodiments, the critical gate spacing t between the two barrier gates (e.g., barrier gates 110A and 110B) is... crit It can be greater than W BG +2t ox .

[0086] Reference Figure 10AIn the top view, the number of plunger gates 150A_P in the first ring can be λ (e.g., 8 in this case). The number of plunger gates 150B_P in the second ring can be λ*2 (e.g., 16 in this case). The number of plunger gates 150C_P in the third ring can be λ*3 (e.g., 24 in this case). The number of plunger gates 150D_P in the fourth ring can be λ*4 (e.g., 32 in this case). That is, the number of plunger gates in the nth ring is a multiple of λ, i.e., λ*n, where λ is the number of plunger gates in the first ring and n is a positive integer.

[0087] exist Figure 10A As can be seen from the diagram, each plunger gate can contain a thickness t along the circumferential direction. QD Please refer to the first ring for the thickness t of each plunger gate (e.g., plunger gate 150A_P). QD It is 2πd / λ, where the spacing d is the distance between two adjacent annular barrier gates (e.g., barrier gates 110A to 110D). Please refer to the nth ring, where the thickness t of each plunger gate is... QD It is 2πR / nλ, where the radius R = n x d (the radius of the nth ring). That is, the thickness t of each plunger gate. QD The value is 2π(n×d) / nλ = 2πd / λ. In some embodiments, the thickness t... QD It can be large enough, for example, greater than the critical gate pitch t. crit (For example, t) QD ≥t crit That is, 2πd / λ≥t crit Therefore, d≥(t) crit λ) / 2π. In some embodiments, if λ≥6, the value d=(t) can be chosen. crit λ) / 2π is used to ensure that the spacing d is not too small to be manufactured. However, if λ < 6, then the value of the spacing d must be chosen as t. crit Therefore, the density in a 2D circular quantum dot array can be optimized by choosing λ equal to or greater than 6.

[0088] The density of qubits (e.g., plunger gates) can be expressed as:

[0089]

[0090] In some embodiments, when n is a very large value, the density of qubits (e.g., plunger gates) can be expressed as:

[0091]

[0092] Figure 11The figures show simulation results for some embodiments of this disclosure. Specifically, simulation results for three different qubit arrangements are illustrated. It can be seen that when the qubits are arranged in a 2D circular array according to the disclosure, the qubit density can be higher than that arranged in a 1D linear array or a 2D rectangular array. Therefore, the circular gate design enables higher quantum dot density and a more compact device configuration. The two-dimensional qubit array design allows for programmable entanglement between quantum dots.

[0093] Based on the foregoing embodiments, it can be seen that this disclosure provides advantages for manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are all embodiments required to have specific advantages. Embodiments of this disclosure provide a qubit quantum dot device in which qubits are arranged in a 2D circular array. The circular gate design enables higher quantum dot density and a more compact device configuration.

[0094] In some embodiments disclosed herein, a quantum dot device includes a substrate. A plurality of first plunger gates are located on the substrate and arranged in a ring. A plurality of second plunger gates are located on the substrate and arranged in a ring. A first annular barrier gate is located on the substrate and positioned between the first and second plunger gates.

[0095] In some embodiments disclosed herein, the quantum dot element further includes a plurality of first linear barrier gates located on a substrate, wherein each of the first linear barrier gates separates a corresponding pair of first plunger gates.

[0096] In some embodiments disclosed herein, the first linear barrier gate extends radially in a top view.

[0097] In some embodiments disclosed herein, the quantum dot element further includes a second annular barrier gate located on the substrate and surrounding the first annular barrier gate. A plurality of second linear barrier gates extend from the first annular barrier gate to the second annular barrier gate, wherein each of the second linear barrier gates separates a corresponding pair of the second plunger gates.

[0098] In some embodiments disclosed herein, one of the second linear barrier gates is connected to one of the first linear barrier gates.

[0099] In some embodiments disclosed herein, the quantum dot element further includes a first annular structure located above the first plunger gate and electrically connecting the first plunger gates to each other.

[0100] In some embodiments disclosed herein, the number of second plunger gates is greater than the number of first plunger gates.

[0101] In some embodiments disclosed herein, the number of second plunger gates is a multiple of the number of first plunger gates.

[0102] In some embodiments disclosed herein, a quantum dot device includes a substrate. A gate dielectric layer is located above the substrate. A first plunger gate structure and a second plunger gate structure are located above the gate dielectric layer, wherein, in a top view, the first and second plunger gate structures are arranged in a concentric circle configuration, and each of the first and second plunger gate structures includes an annular structure and a plurality of plunger gates extending downward from the annular structure. A plurality of barrier gates are located above the gate dielectric layer, wherein, in a cross-sectional view, each of the plunger gates of the first and second plunger gate structures is laterally located between adjacent barrier gates.

[0103] In some embodiments disclosed herein, the plunger gates of the first plunger gate structure are arranged in a ring, and the plunger gates of the second plunger gate structure are arranged in a ring.

[0104] In some embodiments disclosed herein, the barrier gate includes an annular barrier gate, and the annular barrier gate separates the first plunger gate structure and the second plunger gate structure.

[0105] In some embodiments disclosed herein, the plurality of barrier gates includes a plurality of linear barrier gates, and each of the plurality of linear barrier gates is located between two of the plurality of plunger gates.

[0106] In some embodiments disclosed herein, in this cross-sectional view, the upper surface of the linear barrier gate is higher than the upper surface of the annular barrier gate.

[0107] In some embodiments disclosed herein, in this cross-sectional view, the upper surfaces of the first plunger gate structure and the second plunger gate structure are higher than the upper surface of the barrier gate.

[0108] In some embodiments disclosed herein, the first plunger gate structure, the second plunger gate structure, and the barrier gate are made of conductive material.

[0109] In some embodiments disclosed herein, a method includes forming a plurality of source / drain regions in a substrate. A first gate dielectric layer is formed over the substrate. A plurality of barrier gates are formed over the substrate, the plurality of barrier gates defining a first set of cavities and a second set of cavities surrounding the first set of cavities, wherein the plurality of cavities in the first set of cavities are arranged in a ring, and the plurality of cavities in the second set of cavities are arranged in a ring. A plurality of plunger gates are formed in the cavities.

[0110] In some embodiments disclosed herein, forming a barrier gate includes forming a plurality of annular barrier gates over a substrate. Following the annular barrier gates forming the barrier gates, a plurality of linear barrier gates are formed over the substrate.

[0111] In some embodiments disclosed herein, the method further includes forming a second gate dielectric layer along the annular barrier gate of the barrier gate before forming the linear barrier gate of the barrier gate. A third gate dielectric layer is formed along the linear barrier gate of the barrier gate before forming the plunger gate.

[0112] In some embodiments disclosed herein, forming the plunger gate further includes forming a plurality of annular structures located above the plunger gate and connected to the plunger gate.

[0113] In some embodiments disclosed herein, the barrier gate and the plunger gate are made of conductive materials.

[0114] In some embodiments disclosed herein, a quantum dot device includes a substrate. A plurality of first plunger gates are located on the substrate and arranged in a ring. A plurality of second plunger gates are located on the substrate and arranged in a ring. A first annular barrier gate is located on the substrate and positioned between the first and second plunger gates. A plurality of first linear barrier gates are located on the substrate, wherein each of the first linear barrier gates separates a corresponding pair of the first plunger gates.

[0115] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A quantum dot element, characterized by, Comprising: a substrate; a plurality of first plug gates arranged in a ring on the substrate; a plurality of second plug gates arranged in a ring on the substrate; and a first ring-shaped barrier gate on the substrate between the plurality of first plug gates and the plurality of second plug gates.

2. The quantum dot element of claim 1, wherein, Further comprising: a plurality of first linear barrier gates on the substrate, wherein each of the plurality of first linear barrier gates separates a corresponding two of the plurality of first plug gates.

3. The quantum dot element of claim 2, wherein, wherein the plurality of first linear barrier gates extends along a radial direction in a top view.

4. The quantum dot element of claim 2, wherein, Further comprising: a second ring-shaped barrier gate on the substrate surrounding the first ring-shaped barrier gate; and a plurality of second linear barrier gates extending from the first ring-shaped barrier gate to the second ring-shaped barrier gate, wherein each of the plurality of second linear barrier gates separates a corresponding two of the plurality of second plug gates.

5. The quantum dot element of claim 4, wherein, wherein one of the plurality of second linear barrier gates is connected to one of the plurality of first linear barrier gates.

6. The quantum dot element of claim 1, wherein, Further comprising a first ring-shaped structure above the plurality of first plug gates and electrically connecting the plurality of first plug gates to each other.

7. The quantum dot element of claim 1, wherein, wherein a number of the plurality of second plug gates is greater than a number of the plurality of first plug gates.

8. The quantum dot element of claim 7, wherein, wherein the number of the plurality of second plug gates is a multiple of the number of the plurality of first plug gates.

9. A quantum dot element, characterized by, Comprising: a substrate; a gate dielectric layer above the substrate; a first plug gate structure and a second plug gate structure above the gate dielectric layer, wherein in a top view, the first plug gate structure and the second plug gate structure are arranged in concentric circles, and wherein each of the first plug gate structure and the second plug gate structure comprises a ring-shaped structure and a plurality of plug gates extending downward from the ring-shaped structure; and a plurality of barrier gates above the gate dielectric layer, wherein in a cross-sectional view, each of the plurality of plug gates of the first plug gate structure and the second plug gate structure is laterally between two adjacent ones of the plurality of barrier gates.

10. A quantum dot element, characterized by, Comprising: a substrate; a plurality of first plug gates arranged in a ring on the substrate; a plurality of second plug gates arranged in a ring on the substrate; a first ring-shaped barrier gate on the substrate between the plurality of first plug gates and the plurality of second plug gates; and a plurality of first linear barrier gates on the substrate, wherein each of the plurality of first linear barrier gates separates a corresponding two of the plurality of first plug gates.

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