System integration integrated circuit structure

Abstract

The utility model provides a system integrated circuit structure, which comprises a first semiconductor crystal grain, a second semiconductor crystal grain, a dummy crystal grain and a gap filling layer, the second semiconductor die is disposed on the first semiconductor die and electrically connected to the first semiconductor die. The dummy die is disposed on the first semiconductor die to laterally surround the second semiconductor die. The gap filling layer is disposed on the first semiconductor die to laterally cover the dummy die and the second semiconductor die.

Description

TECHNICAL FIELD

[0001] The utility model relates to a system integration integrated circuit structure. BACKGROUND

[0002] Semiconductor assemblies are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor assemblies are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers or materials on a semiconductor substrate, and patterning the various material layers using photolithography techniques to form circuit features and components thereon. Typically, tens or hundreds of integrated circuits are fabricated on a single semiconductor wafer. Individual dies are singulated by cutting the integrated circuits along scribe lines. The individual dies are then separately packaged in a multi-chip module or other type of package.

[0003] The semiconductor industry continues to improve the performance and reliability of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. These smaller electronic components (e.g., integrated circuit dies) also require smaller packages, which in some applications use less area than the packages of the past. SUMMARY

[0004] The present application provides a SoIC structure including a first semiconductor die, a second semiconductor die, dummy dies, and a gap fill layer. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The dummy dies are disposed on the first semiconductor die to laterally surround the second semiconductor die. The gap fill layer is disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor die.

[0005] The present application provides a SoIC structure including a first semiconductor die, a second semiconductor die, dummy dies, and a gap fill layer. The second semiconductor die is stacked on the first semiconductor die. The dummy dies are stacked on the first semiconductor die. The gap fill layer is disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor die, wherein each of the dummy dies includes an outer sidewall, and the outer sidewall of each of the dummy dies is substantially aligned with a sidewall of the gap fill layer.

[0006] The present application provides a SoIC structure including a bottom semiconductor die, a top semiconductor die, a set of warpage control members, and a gap fill layer. The top semiconductor die is disposed on the bottom semiconductor die. The set of warpage control members is disposed on the bottom semiconductor die. The gap fill layer is disposed on the bottom semiconductor die and laterally encloses the set of warpage control members and the top semiconductor die, wherein a first coefficient of thermal expansion of the gap fill layer is greater than a second coefficient of thermal expansion of the set of warpage control members and / or the top semiconductor die.

[0007] In order to make the above features and advantages of the present application more apparent, the following embodiments are described in detail, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0008] The aspects of the application will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity. It is further noted that the disclosure can be used in a variety of applications. Variations of structures and methods that are not specifically enumerated herein will be apparent to those of ordinary skill in the art upon reading this document. For example, it should be understood that any of the features, techniques, compositions, or materials described herein can be easily substituted for or interchanged with any other features, techniques, compositions, or materials described herein or otherwise known to the skilled artisan. Furthermore, any intentionally omitted features, techniques, compositions, or materials can be easily added to the description as necessary.

[0009] Figures 1A-1J A process flow cross-sectional view of a system on integrated circuit (SoIC) structure according to some embodiments of the present disclosure is schematically illustrated.

[0010] Figures 2A-2M A process flow cross-sectional view of an integrated fan-out (InFO) package structure of a SoIC structure according to some embodiments of the present disclosure is schematically illustrated.

[0011] Figure 3A A distribution top view of a plurality of dummy dies 30 and a plurality of sets of semiconductor dies 20 according to some embodiments of the present disclosure is schematically illustrated.

[0012] Figure 3B A top view of a SoIC structure 50 according to some embodiments of the present disclosure is schematically illustrated.

[0013] REFERENCE NUMERALS

[0014] 10, 11: semiconductor wafer

[0015] 11a: first semiconductor die

[0016] 12, 13: substrate

[0017] 14: substrate via

[0018] 15, 16: interconnect structure

[0019] 16a: narrower portion

[0020] 16b: wider portion

[0021] 17, 18: bonded structures

[0022] 17a, 18a: bonding dielectric

[0023] 17b, 18b, 18c: bonding conductors

[0024] 20: semiconductor die

[0025] 20a: annular recess

[0026] 30: dummy die

[0027] 30a, 34a: outer sidewall

[0028] 32: die attach film

[0029] 34': gap fill layer

[0030] 40, 60: carrier

[0031] 42: patterned dielectric

[0032] 44, 46: conductive terminals

[0033] 50: system-on-a-chip structure

[0034] 61, 77: redistribution line structure

[0035] 62: debonding layer

[0036] 64, 68, 78, 82, 88: dielectric layer

[0037] 66, 80, 86: redistribution line

[0038] 70, 79, 84: opening

[0039] 72: metal pillar

[0040] 76: insulative encapsulation material

[0041] 76': insulative encapsulant

[0042] 92: under bump metal

[0043] 94: electrical connection

[0044] 98: solder region

[0045] 100, 102, 200: package

[0046] 202: device die

[0047] 204: package substrate

[0048] SL1, SL2: scribe line DETAILED DESCRIPTION

[0049] The present disclosure provides numerous different embodiments or examples for implementing different features of the present disclosure. The following detailed description of components and arrangements is made to provide a thorough understanding of the present disclosure. It is clear, however, that this description is not intended to limit the present disclosure to one particular embodiment, described and illustrated herein. For example, the description of forming a first feature on or over a second feature in the following description can include embodiments in which the first feature is formed in direct contact with the second feature, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can use reference numbers and / or letters repeatedly in various examples. Such repeated use is for the sake of brevity and clarity and does not itself imply a relationship between the various embodiments and / or configurations discussed.

[0050] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0051] Embodiments of the present disclosure can further include other features and processes. For example, the devices can include test structures to assist in verification testing of 3D packages or 3DIC components. For example, the test structures can include test pads formed in a redistribution layer or on a substrate, and the test pads allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0052] According to various exemplary embodiments, packages and methods of forming the same are provided herein. Various intermediate stages of forming the packages are illustrated in the embodiments. Variations of the embodiments are also discussed. Like reference numbers are used to denote like components throughout the various drawings and illustrative embodiments.

[0053] Figures 1A-1J A process flow cross-sectional view of a SoIC structure according to some embodiments of the present disclosure is schematically illustrated.

[0054] Reference Figure 1Asemiconductor dies. The semiconductor dies can be logic dies, system-on-chip (SoC) dies, or other suitable semiconductor dies. The semiconductor wafer 10 can include a substrate 12 (e.g., a semiconductor substrate), an interconnect structure 16 disposed on the substrate 12, and a bonding structure 18 disposed on the interconnect structure 16. The substrate 12 of the semiconductor wafer 10 can include a crystalline silicon substrate. The substrate 12 can include various doped regions (e.g., a p-type substrate or an n-type substrate) depending on design requirements. In some embodiments, the doped regions can be doped with p-type dopants or n-type dopants. The doped regions can be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations of the foregoing dopants. The doped regions can be configured as n-type FinFETs and / or p-type FinFETs. In some other embodiments, the substrate 12 can be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0055] The interconnect structure 16 can include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect lines embedded in the one or more dielectric layers, and the interconnect lines are electrically connected to semiconductor components (e.g., FinFETs) formed in the substrate 12. The material of the one or more dielectric layers can include silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N y where x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or combinations thereof.

[0056] The bonding structure 18 can include a bonding dielectric layer 18a and bonding conductors 18b embedded in the bonding dielectric layer 18a. The material of the bonding dielectric layer 18a can be silicon oxide (SiO x where x > 0), silicon nitride (SiN x where x > 0), silicon oxynitride (SiO x N ywhere x > 0 and y > 0) or other suitable dielectric material, and the bonding conductor 18b can be a via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 18 can be formed by depositing a dielectric material through a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD, a process, or other suitable process), patterning the dielectric material to form a bonding dielectric layer 18a including an opening or a via, and filling a conductive material into the opening or the via defined in the bonding dielectric layer 18a to form the bonding conductor 18b embedded in the bonding dielectric layer 18a.

[0057] Referring to Figure 1A and Figure 1B The semiconductor wafer 10 is singulated by a wafer sawing process performed along the saw lane SL1 to obtain singulated semiconductor dies 20. Each singulated semiconductor die 20 can include the substrate 12, the interconnect structure 16 disposed on the substrate 12, and the bonding structure 18 disposed on the interconnect structure 16. In some embodiments, the semiconductor wafer 10 is singulated by a pre-singulation process, and then the wafer sawing process is performed along the saw lane SL1 to obtain the singulated semiconductor dies 20. The pre-singulation process can be a plasma sawing process, a laser drilling process, or the like. As a result of the pre-singulation process, the width of the bonding dielectric layer 18a can be narrower than the width of the substrate 12. In some embodiments, the interconnect structure 16 includes a narrower portion 16a and a wider portion 16b, where the narrower portion 16a is a result of the pre-singulation process, the narrower portion 16a is disposed between the wider portion 16b and the bonding structure 18, and the wider portion 16b is disposed between the narrower portion 16a and the substrate 12. In other words, as shown in FIG. 1A, the interconnect structure 16 includes an annular recess 20a resulting from the aforementioned pre-singulation process, and the annular recess 20a is distributed around the sidewall of the bonding dielectric layer 18a and the sidewall of the narrower portion 16a. Figure 1B

[0058] Referring to Figure 1C ​semiconductor die 20 can be singulated into groups of semiconductor dies 20. After picking up semiconductor dies 20 and placing and bonding onto semiconductor wafer 11, a chip probing process can be performed to increase yield. The semiconductor dies in semiconductor wafer 11 can be logic dies, system on chip (SoC) dies, or other suitable semiconductor dies. Semiconductor dies 20 can perform the same function or different functions as the semiconductor dies in semiconductor wafer 11. In some embodiments, semiconductor dies 20 and the semiconductor dies in semiconductor wafer 11 are system on chip (SoC) dies. Semiconductor wafer 11 can include a substrate 13 (e.g., a semiconductor substrate), substrate vias 14 embedded in substrate 13, interconnect structures 15 disposed on substrate 13, and bonding structures 17 disposed on interconnect structures 15, where substrate vias 14 are electrically connected to interconnect structures 15. Substrate 13 of semiconductor wafer 11 can include a crystalline silicon wafer. Depending on design requirements, substrate 13 can include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions can be doped with p-type dopants or n-type dopants. The doped regions can be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations of the foregoing. The doped regions can be configured as n-type FinFETs and / or p-type FinFETs. In some other embodiments, substrate 13 is made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0059] The substrate via 14 can be formed by forming a recess in the substrate 13, e.g., by etching, grinding, laser techniques, and / or a combination thereof. A thin barrier layer can be conformally deposited over the front side of the substrate 13 and in the opening, e.g., via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, and / or a combination thereof. The barrier layer can include a nitride or oxynitride, e.g., titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination of the foregoing, and / or the like. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material can be formed via an electrochemical plating process, CVD, ALD, PVD, and / or a combination thereof. The conductive material is, e.g., copper, tungsten, aluminum, silver, gold, a combination of the foregoing, and / or the like. Excess conductive material and the barrier layer can be removed from the front side of the substrate 13, e.g., by chemical mechanical grinding (CMP). Thus, in some embodiments, the substrate via 14 can include a conductive material and a thin barrier layer between the conductive material and the substrate 13. In some embodiments, the substrate via 14 can extend through one or more layers of the interconnect structure 15 and protrude into the substrate 13. As shown, the substrate via 14 is embedded in the substrate 13 and the interconnect structure 15. At this stage, the substrate via 14 does not protrude from the back side of the substrate 13. Figure 1C

[0060] The interconnect structure 15 can include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic compound dielectric (IMD) layers, or the like) and interconnect lines embedded in the one or more dielectric layers, and the interconnect lines are electrically connected to semiconductor components (e.g., FinFETs) formed in the substrate 12. The material of the one or more dielectric layers can include silicon oxide (SiO x with x > 0), silicon nitride (SiN x with x > 0), silicon oxynitride (SiO x N y with x > 0 and y > 0), or other suitable dielectric materials. The interconnect lines can include metal lines. For example, the interconnect lines include copper lines, copper pads, aluminum pads, or a combination thereof.

[0061] The bonding structure 17 can include a bonding dielectric layer 17a and a bonding conductor 17b embedded in the bonding dielectric layer 17a. The material of the bonding dielectric layer 17a can be silicon oxide (SiO x with x > 0), silicon nitride (SiN x with x > 0), silicon oxynitride (SiO x N y ​dielectric material, and the bonding conductor 17b can be a via (e.g., a copper via), a conductive pad (e.g., a copper pad), or a combination thereof. The bonding structure 17 can be formed by depositing a dielectric material through a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process), patterning the dielectric material to form a bonding dielectric layer 17a including openings or vias, and filling a conductive material into the openings or vias defined by the bonding dielectric layer 17a to form the bonding conductor 17b embedded in the bonding dielectric layer 17a.

[0062] The singulated semiconductor die 20 is picked up and placed on the semiconductor wafer 11 through a chip-to-wafer bonding process such that the bonding structure 18 of the singulated semiconductor die 20 is in contact with the bonding structure 17 of the semiconductor wafer 11. The chip-to-wafer bonding process is performed to bond the bonding structure 18 of the singulated semiconductor die 20 to the bonding structure 17 of the semiconductor wafer 11. The chip-to-wafer bonding process can be a hybrid bonding process including dielectric-to-dielectric bonding and metal-to-metal bonding. After the chip-to-wafer bonding process is performed, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer 18a and the bonding dielectric layer 17a, and metal-to-metal bonding interfaces are formed between the bonding conductor 18c and the bonding conductor 17b.

[0063] Reference is made to Figure 1Ddummy dies 30 are placed, picked and attached to the semiconductor wafer 11 such that the dummy dies 30 contact and attach to the bond structures 17 of the semiconductor wafer 11. The dummy dies 30 are disposed in the gaps between the semiconductor dies 20. The dummy dies 30 are laterally spaced apart from the semiconductor dies 20 by a lateral distance, and the lateral distance is between about 30 microns and about 50 microns. For example, the dummy dies 30 are laterally spaced apart from the semiconductor dies 20 by a lateral distance of about 40 microns. In addition, in some embodiments, the semiconductor dies 20 are spaced apart from each other by a lateral distance, and the lateral distance is between about 30 microns and about 50 microns. For example, the semiconductor dies are spaced apart from each other by a lateral distance of about 40 microns. In embodiments in which the semiconductor dies 20 placed on the semiconductor wafer 11 are divided into groups of semiconductor dies 20, the dummy dies 30 are placed on the semiconductor wafer to laterally surround each group of semiconductor dies 20, as shown in FIG. 3B. In other words, the groups of semiconductor dies 20 are spaced apart from each other by the dummy dies 30, as shown in FIG. 3C. Figure 3A Figure 3A

[0064] Figure 1D As shown in FIG. 3B, the dummy dies 30 can be attached to the bond structures 17 of the semiconductor wafer 11 through a die attach film (DAF) 32. In some embodiments, in order to facilitate the placement process of the dummy dies 30, the top surface of the dummy dies 30 should be higher than the top surface of the semiconductor dies 20. In other words, the total thickness of the dummy dies 30 and the DAF 32 can be greater than the thickness of the semiconductor dies 20. The material of the dummy dies 30 can be the same as the material of the substrate 13 in the semiconductor wafer 11 and / or the material of the substrate 12 in the semiconductor dies 20. The coefficient of thermal expansion (CTE) of the dummy dies 30 can be substantially equal to the CTE of the substrate 13 in the semiconductor wafer 11 and / or the CTE of the substrate 12 in the semiconductor dies 20. In some embodiments, the dummy dies 30 are crystalline silicon dummy dies. In some other embodiments, the dummy dies 30 are made of some other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide or gallium indium phosphide.

[0065] ​​​In some embodiments, dummy die 30 is electrically floated. In some embodiments, dummy die 30 is electrically isolated from semiconductor die 20 and semiconductor wafer 11. In some embodiments, dummy die 30 does not provide an electrical function. In embodiments where the CTE of dummy die 30 is substantially equal to the CTE of substrate 13 in semiconductor wafer 11 and / or the CTE of substrate 12 in semiconductor die 20, dummy die 30 can provide a suitable warpage suppression function.

[0066] Referring to Figure 1E A gap fill material 34 is formed over semiconductor wafer 11 to cover semiconductor die 20. Gap fill material 34 can be a dielectric material (e.g., an oxide formed from tetraethoxysilane or other suitable dielectric material), a molding compound (e.g., an epoxy or other suitable resin) formed via a gap fill process, an over-molding process, etc. Gap fill material 34 fills the gaps between adjacent semiconductor die 20, the gaps between adjacent dummy die 30, and the gaps between dummy die 30 and semiconductor die 20 adjacent to dummy die 30. As shown, gap fill material 34 is formed to fill annular recess 20a such that gap fill material 34 is in contact with the sidewalls of narrower portion 16a and the sidewalls of bond dielectric layer 18a. In some embodiments, the gap between adjacent semiconductor die 20 is between about 30 microns and about 50 microns. For example, the gap between adjacent semiconductor die 20 is about 40 microns. In some embodiments, the gap between adjacent dummy die 30 is between about 30 microns and about 50 microns. For example, the gap between adjacent dummy die 30 is about 40 microns. In some embodiments, the gap between dummy die 30 and semiconductor die 20 adjacent to dummy die 30 is between about 30 microns and about 50 microns. For example, the gap between dummy die 30 and semiconductor die 20 adjacent to dummy die 30 is about 40 microns. Figure 1E

[0067] In some embodiments, a first grinding process is performed to partially remove gap fill material 34 so that gap fill material 34 can be thinned. After the first grinding process of gap fill material 34 is performed, semiconductor die 20 and dummy die 30 are still covered by gap fill material 34. At this stage, semiconductor die 20 and dummy die 30 are not exposed from the top surface of gap fill material 34.

[0068] As Figure 1E ​As shown, the placement of the dummy die 30 reduces the total amount of interstitial filling material 34 that laterally covers the semiconductor die 20 and the dummy die 30. Only a small amount of interstitial filling material 34 is formed in the gaps between adjacent semiconductor dies, the gaps between adjacent dummy dies 30, and the gap between the dummy die 30 and the semiconductor die 20. In some embodiments, the CTE of the interstitial filling material 34 is greater than the CTE of the semiconductor die 20 and the semiconductor wafer 11. Furthermore, the CTE mismatch between the interstitial filling material 34 and the semiconductor die 20 and / or the semiconductor wafer 11 is greater than the CTE mismatch between the dummy die 30 and the semiconductor die 20 and / or the semiconductor wafer 11. Because the CTE mismatch between the interstitial filling material 34 and the semiconductor die 20 (or the semiconductor wafer 11) is greater than the CTE mismatch between the dummy die 30 and the semiconductor die 20 (or the semiconductor wafer 11), therefore Figure 1E The warpage of the resulting structure (i.e., the reconstructed wafer structure) shown can be minimized.

[0069] refer to Figure 1E and Figure 1F Provide carrier plate 40, and will Figure 1E The resulting structure shown is attached to a carrier plate 40. In some embodiments, the carrier plate 40 is a glass substrate, a ceramic carrier plate, etc. The carrier plate 40 may be a silicon wafer having a circular top view shape and size. For example, the carrier plate 40 may have an 8-inch diameter, a 12-inch diameter, etc. A de-bonding layer may be formed on the carrier plate 40. The de-bonding layer formed on the carrier plate 40 may be or include a polymer-based material (e.g., a light-to-heat conversion (LTHC) material), which may subsequently be removed along with the carrier plate 40 from the overlay structure to be formed in subsequent steps. In some embodiments, the de-bonding layer is formed of an epoxy-based thermal-release material. In other embodiments, the de-bonding layer is formed of a UV adhesive. The de-bonding layer may be applied and cured in a liquid state. In other embodiments, the de-bonding layer is a laminate film, and this laminate film is laminated onto the carrier plate 40. The top surface of the de-bonding layer is substantially planar.

[0070] like Figure 1F As shown, in the case of Figure 1EAfter the resulting structure is attached to the carrier plate 40, a removal process is performed to partially remove the semiconductor substrate 13 until the substrate via 14 is exposed from the back side of the semiconductor substrate 13 of the semiconductor wafer 11. At this stage, the substrate via 14 can protrude from the back side of the semiconductor substrate 13 of the semiconductor wafer 11. In some embodiments, the semiconductor substrate 13 removal process includes chemical mechanical polishing (CMP), mechanical polishing, a combination of the foregoing processes, or other similar processes.

[0071] refer to Figure 1G A patterned dielectric layer 42 with openings formed therein is formed on the back side of the semiconductor substrate 13, such that the substrate via 14 is exposed by the openings of the patterned dielectric layer 42. The patterned dielectric layer 42 can be formed by a dielectric material deposition process (e.g., CVD process or the like) and a subsequent patterning process (e.g., photolithography process). The patterned dielectric layer 42 can be or includes silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric materials.

[0072] like Figure 1G As shown, after forming a patterned dielectric layer 42, a conductive terminal 44 is formed over the patterned dielectric layer 42. The conductive terminal 44 is electrically connected to a substrate via 14. In some embodiments, the conductive terminal 44 includes a controlled collapse chip connection (C4) bump. The formation of the conductive terminal 46 may include forming an under bump metallurgy (UBM) layer (not shown) over the patterned dielectric layer 42, forming a patterned mask (not shown) such as a photomask layer over the UBM layer, and then performing an electroplating process on the exposed UBM layer. The patterned mask and portions of the UBM layer covered by the patterned mask are then removed to leave the conductive terminal 44. A reflow process may be further performed to reshape the contour of the conductive terminal 44. According to some embodiments, the UBM layer includes a titanium layer and a copper layer above the titanium layer. The UBM layer may be formed using, for example, physical vapor deposition (PVD). Electroplating may be performed using, for example, electroless plating. In some embodiments, the conductive terminal 44 is further protected by a protective layer (such as... Figure 1J The area covered by the dotted line shown in the drawing.

[0073] refer to Figure 1G and Figure 1HAfter the formation of the conductive terminals 44, a second grinding process is performed to partially remove the gap fill material 34 until the substrate 10 of the semiconductor die 20 and the dummy die 30 are exposed, thereby forming a gap fill layer 34'. The second grinding process of the gap fill material 34 includes a chemical mechanical grinding (CMP) process, a mechanical grinding process, a combination of the foregoing processes, or other similar processes. After the second grinding process is performed, a top surface of the gap fill layer 34' is substantially flush with a back surface of the semiconductor die 20 and a top surface of the dummy die 30. During the second grinding process of the gap fill material 34, the dummy die 30 is also partially removed. The dummy die 30 is thinned until the back surface of the semiconductor die 20 is substantially flush with the top surface of the dummy die 30.

[0074] In some other embodiments, due to the grinding selectivity of the second grinding process, the top surface of the gap fill layer 34' can be slightly lower or slightly higher than the back surface of the semiconductor die 20 and the top surface of the dummy die 30.

[0075] Reference is made to Figure 1I With reference to Figure 1J , a wafer singulation process is performed along the scribe lanes SL2 to singulate the reconstituted wafer structure shown in Figure 1I , thereby obtaining the singulated component dies or singulated SoIC structures 50 shown in Figure 1J .

[0076] As shown in Figure 1J , the singulated SoIC structure 50 can include a first semiconductor die 11a, a second semiconductor die 20, a dummy die 30, and a gap fill layer 34. The second semiconductor die 20 is disposed above (or stacked above) the first semiconductor die 11a and is electrically connected to the first semiconductor die 11a. The dummy die 30 is disposed above (or stacked above) the first semiconductor die 11a to laterally surround the second semiconductor die 20, as shown in Figure 3B . The gap fill layer 34 is disposed on the first semiconductor die 11a to laterally encapsulate the dummy die 30 and the second semiconductor die 20. As shown in Figure 3B , in the singulated SoIC structure 50, the dummy die 30 has various geometrical shapes. For example, a plurality of the dummy die 30 has substantially the same thickness, and the dummy die 30 has different lengths and / or widths. In addition, as shown in Figure 3BAs shown, in the singulated SoIC structure 50, the gap fill layer 34 includes a plurality of segments for separating adjacent second semiconductor dies 20, and the plurality of segments have substantially the same width. In some embodiments, the first semiconductor die 11a includes a first bonding structure 17, each second semiconductor die 20 includes a second bonding structure 18, the second bonding structure 18 of each second semiconductor die 20 is in contact with the first bonding structure 17 of the first semiconductor die 11a, and the second bonding structure 18 of each second semiconductor die 20 is electrically connected with the first bonding structure 17 of the first semiconductor die 11a. In some embodiments, each dummy die 30 includes an outer sidewall 30a, and the outer sidewall 30a of each dummy die 30 is substantially aligned with a sidewall of the first bonding structure 17. In some embodiments, the dummy die 30 and the second bonding structure 18 of each of the second semiconductor dies 20 are spaced apart by the gap fill layer 34. In some embodiments, each dummy die 30 is laterally spaced apart from one of the second semiconductor dies 20 by the gap fill layer 34. In some embodiments, each dummy die 30 includes an outer sidewall 30a, and the outer sidewall 30a is substantially aligned with a sidewall of the first semiconductor die 11a. In some embodiments, two adjacent ones of the second semiconductor dies 20 are laterally spaced apart from each other by the gap fill layer 34. In some embodiments, two adjacent ones of the dummy dies 30 are laterally spaced apart from each other by the gap fill layer 34. In some embodiments, the SoIC structure 50 further includes a die attach film 32, wherein each dummy die 30 is attached to the first semiconductor die 11a by one of the die attach films 32, respectively.

[0077] In some embodiments, each dummy die 30 includes an outer sidewall 30a, and the outer sidewall 30a of each dummy die 30 is substantially aligned with a sidewall of the gap fill layer 34. The outer sidewall 30a of the dummy die 30 can include scratch marks caused by the wafer sawing process described above, and the top surface of the dummy die 30 can include grinding marks caused by the second grinding process described above. The roughness of the outer sidewall 30a of the dummy die 30 can be greater than the roughness of the top surface of the dummy die 30. Since the grinding process is not performed on the bottom surface of the dummy die 30, the roughness of the bottom surface of the dummy die 30 can be less than the roughness of the top surface of the dummy die 30. Similarly, the outer sidewall 34a of the gap fill layer 34 (e.g., the sidewall of the gap fill layer 34 that is in contact with the first bonding structure 17 of the first semiconductor die 11a) can include scratch marks caused by the wafer sawing process described above, and the top surface of the gap fill layer 34 can include grinding marks caused by the second grinding process described above. The roughness of the outer sidewall 34a of the gap fill layer 34 can be greater than the roughness of the top surface of the gap fill layer 34. Since the grinding process is not performed on the bottom surface of the gap fill layer 34, the roughness of the bottom surface of the gap fill layer 34 can be less than the roughness of the top surface of the gap fill layer 34. Figure 3BThe top surface of the gap fill layer 34 can include the scratch marks caused by the wafer dicing process described above, and the top surface of the gap fill layer 34 can include the polish marks caused by the second polishing process described above. The roughness of the outer sidewalls 34a of the gap fill layer 34 can be greater than the roughness of the top surface of the gap fill layer 34. In some embodiments, the dummy dies 30 are electrically floating. In some embodiments, the dummy dies 30 are electrically isolated from the first semiconductor dies 11a and the second semiconductor dies 20. In some embodiments, the dummy dies 30 are electrically isolated from each other. In some embodiments, the first coefficient of thermal expansion (CTE) mismatch between the gap fill layer 34 and the first semiconductor dies 11a is greater than the second CTE mismatch between the dummy dies 30 and the first semiconductor dies 11a. In some embodiments, the first coefficient of thermal expansion (CTE) of the gap fill layer 34 is greater than the second CTE of the dummy dies 30 or the second semiconductor dies 20.

[0078] In some other embodiments of the present disclosure, the first semiconductor dies 11a comprise bottom tier semiconductor dies, the second semiconductor dies 20 comprise top tier semiconductor dies, and the dummy dies 30 comprise a set of warpage control members, wherein the first coefficient of thermal expansion (CTE) of the gap fill layer 34 is greater than the second CTE of the set of warpage control members and / or the top tier semiconductor dies 20. In some embodiments, each warpage control member 30 includes an outer sidewall 30a, and the outer sidewall 30a of each warpage control member 30 is substantially aligned with the sidewall of the gap fill layer 34. In some embodiments, each warpage control member 30 includes an outer sidewall 30a, and the outer sidewall 30a of each warpage control member 30 is substantially aligned with the sidewall of the bottom tier semiconductor dies 11a. In some embodiments, each warpage control member 30 is laterally spaced apart from the other by a lateral distance, and the lateral distance is between about 30 microns and about 50 microns. In some embodiments, the set of warpage control members 30 is electrically floating. In some embodiments, the second semiconductor dies (e.g., top tier semiconductor dies) 20 are spaced apart from each other by a lateral distance, and the lateral distance is between about 30 microns and about 50 microns. For example, the second semiconductor dies (e.g., top tier semiconductor dies) are laterally spaced apart from each other by a lateral distance of about 40 microns.

[0079] In this architecture of the SoIC structure 50, the dummy dies 30 can minimize the warpage of the SoIC structure 50 because the dummy dies 30 reduce the amount of the gap fill layer 34. As a result, the delamination issue between the first bonding structure 17 and the second bonding structure 18 can be improved, and the manufacturing yield of the SoIC structure 50 can be enhanced.

[0080] Figures 2A-2M A process flow diagram of an integrated fan-out (InFO) package structure incorporating a SoIC structure in accordance with some embodiments of the present disclosure is schematically illustrated. Figures 2A-2M An integrated fan-out package structure incorporating a SoIC structure 50 is formed by a packaging process as illustrated in Figure 1J

[0081] Referring to Figure 2A , a carrier 60 is provided, which includes a debonding layer 62 formed thereon. In some embodiments, the carrier 60 is a glass substrate, a ceramic carrier, or the like. The carrier 60 can be a silicon wafer having a circular top view shape and size. For example, the carrier 60 can have an 8-inch diameter, a 12-inch diameter, or the like. The debonding layer 62 can be formed of a polymer base material, such as a light-to-heat conversion (LTHC) material, which can be later removed from overlying structures to be formed in subsequent steps along with the carrier 60. In some embodiments, the debonding layer 62 is formed of an epoxy base thermal release material. In other embodiments, the debonding layer 62 is formed of an ultraviolet (UV) glue. The debonding layer 62 can be applied in a liquid state and cured. In other embodiments, the debonding layer 62 is a lamination film and is laminated to the carrier 60. A top surface of the debonding layer 62 is substantially planar.

[0082] Referring to Figures 2A-2C , a redistribution line structure 61 including a dielectric layer 64, a redistribution line 66, and a dielectric layer 68 is formed on the debonding layer 62 such that the debonding layer 62 is between the carrier 60 and the dielectric layer 64 of the redistribution line structure 61. As shown in Figure 2A , the dielectric layer 64 is formed on the debonding layer 62. In some embodiments, the dielectric layer 64 is formed of a polymer, which can also be a photosensitive material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like, which can be readily patterned using a photolithography process. In some embodiments, the dielectric layer 64 is formed of a nitride, such as silicon nitride, an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. As shown in Figure 2B , the redistribution line 66 is formed on the dielectric layer 64. The formation of the redistribution line 66 can include forming a seed layer (not shown) on the dielectric layer 64, forming a patterned mask (not shown), such as a photoresist layer, on the seed layer, and then performing an electroplating process on the exposed seed layer. The patterned mask and portions of the seed layer covered by the patterned mask are then removed, leaving the redistribution line 66 as shown in Figure 2B ​The redistribution wiring 66 is shown. According to some embodiments, the seed layer includes a titanium layer and a copper layer situated on top of the titanium layer. For example, the seed layer can be formed using physical vapor deposition (PVD). For example, electroplating can be performed using electroless plating. Figure 2C As shown, a dielectric layer 68 is formed over a dielectric layer 64 to cover the redistribution wiring 66. The bottom surface of the dielectric layer 68 contacts the redistribution wiring 66 and the top surface of the dielectric layer 64. According to some embodiments of this disclosure, the dielectric layer 68 is formed of a polymer, which may be a photosensitive material such as PBO, PI, BCB, or the like. In some embodiments, the dielectric layer 68 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 68 is then patterned to form openings 70 therein. Thus, multiple portions of the redistribution wiring 66 are exposed through the openings 70 in the dielectric layer 68. For illustrative purposes, Figure 2C The following figures illustrate a single redistribution wiring structure 61 with a single layer redistribution wiring 66, and some embodiments may have a multi-layer redistribution wiring 66 by repeating the process discussed above.

[0083] refer to Figure 2D After a redistribution wiring structure 61 is formed on the debonding layer 62 supported by the carrier 60, metal pillars 72 are formed on the redistribution wiring structure 61, and the metal pillars 72 are electrically connected to the redistribution wiring 66 of the redistribution wiring structure 61. Throughout the description, because the metal pillars 72 penetrate the subsequently formed molding material (e.g., Figure 2G As shown in the figure, the metal pillar 72 can therefore be referred to as the conductive via 72. In some embodiments, the conductive via 72 is formed by electroplating. The electroplating of the conductive via 72 may include: forming a blanket-coated seed layer (not shown) over the dielectric layer 68, the blanket-coated seed layer extending to... Figure 2C In the opening 70 shown, a photoresist (not shown) is formed on a portion of the seed layer and patterned (not shown); and multiple portions of the seed layer exposed by the opening in the photoresist are electroplated to form a conductive via 72. The photoresist and the portions of the seed layer covered by the photoresist are then removed. The material of the conductive via 72 may include copper, aluminum, or the like. The conductive via 72 may have a rod shape. The top view shape of the conductive via 72 may be circular, rectangular, square, hexagonal, or similar.

[0084] refer to Figure 2E After forming the conductive via 72, at least one monomerized SoIC structure is picked up, for example Figure 1J The monolithic SoIC structure 50 shown is placed above the dielectric layer 68 of the redistributed circuit structure 61. For illustrative purposes, in Figure 2EOnly a single monolithic SoIC structure 50 and multiple conductive vias 72 are shown. However, it should be noted that... Figures 2A-2M The process steps shown can be performed at the wafer level and can be performed on all the monolithic SoIC structures 50 and conductive vias 72 disposed on the carrier 60. Figure 2E As shown, the top semiconductor die 20 is stacked on top of the bottom semiconductor die 11a, and the back side of the bottom semiconductor die 11a in the monolithic SoIC structure 50 can be attached to the dielectric layer 68 through, for example, a die bonding film (not shown).

[0085] Please refer to Figure 2F An insulating encapsulating material 76 is formed on the redistributed circuit structure 61 to cover the SoIC structure 50 and the conductive vias 72. The insulating encapsulating material 76 may be a molding compound (e.g., epoxy resin or other suitable resin) formed through an overmolding process. The insulating encapsulating material 76 fills the gaps between adjacent conductive vias 72, the gaps between top semiconductor dies 20, and the gaps between the conductive vias 72 and the SoIC structure 50. The top surface of the insulating encapsulating material 76 is higher than the back surface of the top semiconductor dies 20 and the conductive vias 72.

[0086] Next, as Figure 2G As shown, a planarization process, such as chemical mechanical polishing (CMP) and / or mechanical polishing, is performed to partially remove the insulating encapsulating material 76 until the conductive vias 72 and conductive terminals 44 are exposed. After the insulating encapsulating material 76 is thinned, an insulating encapsulation body 76' is formed to laterally cover the SoIC structure 50 and the conductive vias 72. Due to planarization, within process variations, the top ends of the conductive vias 72 are substantially flush with or coplanar with the exposed surfaces of the conductive terminals 44 and the top surface of the insulating encapsulation body 76'. In an exemplary embodiment, planarization is performed until the conductive vias 72 and conductive terminals 44 are exposed. Furthermore, the insulating encapsulation body 76' may fill the gaps between the conductive terminals 44. Additionally, the insulating encapsulation body 76' is in contact with the patterned dielectric layer 42.

[0087] Figures 2H-2M The diagram illustrates the formation of the redistributed circuit structure 77 and the solder area. (For example...) Figures 2H-2L As shown, a redistribution wiring structure 77, including dielectric layer 78, redistribution wiring 80, dielectric layer 82, redistribution wiring 86, and dielectric layer 88, is formed on substrate 12 and insulating encapsulation 76'. Figure 2M As shown, multiple solder regions, including under bump metal (UBM) 92 and electrical connectors 94 disposed on UBM 92, are formed on the redistributed circuit structure 77.

[0088] Please refer to Figure 2H A dielectric layer 78 is formed on the top semiconductor die 20 and the insulating encapsulator 76' of the SoIC structure 50. In some embodiments, the dielectric layer 78 is formed of PBO, PI, or the like. In some embodiments, the dielectric layer 78 is formed of silicon nitride, silicon oxide, or the like. An opening 79 is formed in the dielectric layer 78 to expose the conductive terminal 44 and the conductive via 72. The opening 79 can be formed by a photolithography process.

[0089] Next, refer to Figure 2I This forms a redistribution wiring 80 connecting the conductive terminal 44 and the conductive via 72. The redistribution wiring 80 may include a metal trace (metal line) located above the dielectric layer 78 and extending to the opening 79 ( Figure 2H The metal vias (shown in the diagram) allow the redistribution wiring 80 to be electrically connected to the conductive via 72 and the conductive terminal 44. In some embodiments, the redistribution wiring 80 is formed by an electroplating process, wherein each redistribution wiring 80 includes a seed layer (not shown) and a plated metallic material located above the seed layer. The seed layer and the plated metallic material may be formed of the same material or different materials. The redistribution wiring 80 may include metal or metal alloys including aluminum, copper, tungsten, and their alloys. The redistribution wiring 80 is formed of non-solder materials. The via portions of the redistribution wiring 80 may physically contact the top surface of the conductive terminal 44.

[0090] Please refer to Figure 2J A dielectric layer 82 is formed over the redistribution wiring 80 and the dielectric layer 78. The dielectric layer 82 can be formed using a polymer, which may be selected from the same candidate materials as the dielectric layer 78. For example, the dielectric layer 82 may include PBO, PI, BCB, or the like. In some embodiments, the dielectric layer 82 may include an organic dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. An opening 84 is also formed in the dielectric layer 82 to expose the redistribution wiring 80. The opening 84 may be formed using a photolithography process.

[0091] refer to Figure 2K , Figure 2K The diagram illustrates the formation of redistribution wiring 86, which is electrically connected to redistribution wiring 80. Redistribution wiring 86 can be formed using methods and materials similar to those used to form redistribution wiring 80.

[0092] refer to Figure 2LAn additional dielectric layer 88, which may be a polymer layer, is formed to cover the redistribution wiring 86 and the dielectric layer 82. The dielectric layer 88 may be selected from the same candidate polymer used to form the dielectric layers 78 and 82. An opening 90 is then formed in the dielectric layer 88 to expose multiple metal pad portions of the redistribution wiring 86. The formation of the opening 90 may be performed by a photolithography process.

[0093] Figure 2M The diagram illustrates the formation of the UBM 92 and the electrical connector 94 in some exemplary embodiments. (Reference) Figure 2M The formation of UBM 92 may include deposition and patterning. The formation of electrical connector 94 may include placing solder on the exposed portion of UBM 92 and then reflowing the solder to form solder balls. In some embodiments, the formation of electrical connector 94 includes performing an electroplating step to form solder areas on redistribution wiring 86 and then reflowing the solder areas. Electrical connector 94 may also include metal pillars or include both metal pillars and solder caps, and electrical connector 94 may also be formed by electroplating. Throughout the description, the combined structure including SoIC structure 50, conductive via 72, insulating encapsulation 76', redistribution wiring structure 61, and redistribution wiring structure 77 is referred to as package 100, which may be a composite wafer having a circular top view shape.

[0094] Next, the package 100 is debonded from the carrier 60. The debonding layer 62 is also removed from the package 100. The aforementioned debonding can be performed by irradiating the debonding layer 62 with light such as UV light or laser to decompose the debonding layer 62. In the aforementioned debonding process, tape (not shown) can be adhered to the dielectric layer 88 and the electrical connector 94. In a subsequent step, the carrier 60 and the debonding layer 62 are removed from the package 100. A die dicing process is performed to cut the package 100 into a plurality of integrated fan-out (InFO) packages, each of which includes at least one SoIC structure 50, conductive via 72, insulating encapsulation 76', redistribution structure 61, and redistribution structure 77. One of the resulting packages is as follows: Figure 2M The illustrated package 100.

[0095] According to some embodiments of the present disclosure, a SoIC structure including a first semiconductor die, a second semiconductor die, a dummy die, and a gap fill layer is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The dummy die is disposed on the first semiconductor die to laterally surround the second semiconductor die. The gap fill layer is disposed on the first semiconductor die to laterally enclose the dummy die and the second semiconductor die. In some embodiments, the first semiconductor die includes a first bonding structure, each of the second semiconductor dies includes a second bonding structure, the second bonding structure of each of the second semiconductor dies is in contact with the first bonding structure, and the second bonding structure of each of the second semiconductor dies is electrically connected to the first bonding structure. In some embodiments, each of the dummy dies includes an outer sidewall, and the outer sidewall of each of the dummy dies is substantially aligned with a sidewall of the first bonding structure. In some embodiments, the dummy die and the second bonding structure of each of the second semiconductor dies are spaced apart by the gap fill layer. In some embodiments, each of the dummy dies and one of the second semiconductor dies are laterally spaced apart by the gap fill layer. In some embodiments, each of the dummy dies includes an outer sidewall, and the outer sidewall is substantially aligned with a sidewall of the first semiconductor die. In some embodiments, two adjacent ones of the second semiconductor dies are laterally spaced apart from each other by the gap fill layer. In some embodiments, two adjacent ones of the dummy dies are laterally spaced apart from each other by the gap fill layer. In some embodiments, the foregoing structure further includes a die attach film, wherein each of the dummy dies is attached to the first semiconductor die by one of the die attach films, respectively.

[0096] According to some other embodiments of the present disclosure, a SoIC structure including a first semiconductor die, a second semiconductor die, a dummy die, and a gap fill layer is provided. The second semiconductor die is stacked on the first semiconductor die. The dummy die is stacked on the first semiconductor die. The gap fill layer is disposed on the first semiconductor die to laterally enclose the dummy die and the second semiconductor die, wherein each of the dummy dies includes an outer sidewall, and the outer sidewall of each of the dummy dies is substantially aligned with a sidewall of the gap fill layer. In some embodiments, the dummy dies are electrically floating. In some embodiments, the dummy dies are electrically insulated from the first semiconductor die and the second semiconductor dies. In some embodiments, the dummy dies are electrically insulated from each other. In some embodiments, a first coefficient of thermal expansion mismatch between the gap fill layer and the first semiconductor die is greater than a second coefficient of thermal expansion mismatch between the dummy dies and the first semiconductor die. In some embodiments, a first coefficient of thermal expansion of the gap fill layer is greater than a second coefficient of thermal expansion of the dummy dies or the second semiconductor dies.

[0097] According to some other embodiments of the present disclosure, a SoIC structure including a bottom semiconductor die, a top semiconductor die, a set of warpage control members, and a gap fill layer is provided. The top semiconductor die is disposed on the bottom semiconductor die. The set of warpage control members is disposed on the bottom semiconductor die. The gap fill layer is disposed on the bottom semiconductor die and laterally surrounds the set of warpage control members and the top semiconductor die, wherein a first coefficient of thermal expansion of the gap fill layer is greater than a second coefficient of thermal expansion of the set of warpage control members and / or the top semiconductor die. In some embodiments, each of the set of warpage control members includes an outer sidewall, and the outer sidewall of each of the set of warpage control members is substantially aligned with a sidewall of the gap fill layer. In some embodiments, each of the set of warpage control members includes an outer sidewall, and the outer sidewall of each of the set of warpage control members is substantially aligned with a sidewall of the bottom semiconductor die. In some embodiments, each of the set of warpage control members is spaced apart from the top semiconductor die by a lateral distance, and the lateral distance is between about 30 microns and about 50 microns. In some embodiments, the set of warpage control members is electrically floating.

[0098] Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the present application, rather than limiting them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A system-on-a-chip integrated circuit structure, comprising: Comprising: a first semiconductor die; a second semiconductor die disposed on the first semiconductor die and electrically connected with the first semiconductor die; dummy dies disposed on the first semiconductor die to laterally wrap the second semiconductor dies, wherein a roughness of a bottom surface of each of the dummy dies is less than a roughness of a top surface of each of the dummy dies; and a gap fill layer disposed on the first semiconductor die to laterally wrap the dummy dies and the second semiconductor dies. The first semiconductor die includes a first bonding structure, each of the second semiconductor dies includes a second bonding structure, the second bonding structure of each of the second semiconductor dies is in contact with the first bonding structure, and the second bonding structure of each of the second semiconductor dies is electrically connected with the first bonding structure.

2. The system-on-chip integrated circuit structure of claim 1, wherein, Each of the dummy dies includes an outer sidewall having a roughness greater than the roughness of the top surface of each of the dummy dies, and the outer sidewall of each of the dummy dies is aligned with a sidewall of the first bonding structure.

3. The system-on-chip integrated circuit structure of claim 2, wherein, Each of the dummy dies includes an outer sidewall, and the outer sidewall is aligned with a sidewall of the first semiconductor die.

4. The system-on-chip integrated circuit structure of claim 1, wherein, Further comprising a die attach film, wherein each of the dummy dies is connected to the first semiconductor die through one of the die attach films, respectively.

5. The system-on-chip integrated circuit structure of claim 1, wherein, Comprising:

6. A system-on-a-chip integrated circuit structure, comprising: a first semiconductor die; a second semiconductor die stacked on the first semiconductor die; a dummy die stacked on the first semiconductor die; a gap fill layer disposed on the first semiconductor die to laterally wrap the dummy die and the second semiconductor die, wherein each of the dummy dies includes an outer sidewall, and the outer sidewall of each of the dummy dies is aligned with a sidewall of the gap fill layer. The dummy die is electrically floating. A first coefficient of thermal expansion mismatch between the gap fill layer and the first semiconductor die is greater than a second coefficient of thermal expansion mismatch between the dummy die and the first semiconductor.

7. The system-on-chip integrated circuit structure of claim 6, wherein, Comprising:

8. The system-on-chip integrated circuit structure of claim 6, wherein, a bottom semiconductor die; 9. A system-on-a-chip integrated circuit structure, comprising: a top semiconductor die disposed on the bottom semiconductor die; a warpage control member group disposed on the bottom semiconductor die; and a gap fill layer disposed on the bottom semiconductor die and laterally wrapping the warpage control member group and the top semiconductor die, wherein a first coefficient of thermal expansion of the gap fill layer is greater than a second coefficient of thermal expansion of the warpage control member group and / or the top semiconductor die. The warpage control member group is electrically floating. ​ ​ 10. The system-on-chip integrated circuit structure of claim 9, wherein, ​

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