Display panel and display device

Abstract

The display panel and the display device provided by the embodiment of the utility model comprise the components of a substrate which comprises a plurality of pixel circuits; the pixel circuit comprises a driving transistor, a first capacitor and a second capacitor. A first pole plate of the first capacitor is coupled with a second pole of the driving transistor, and a second pole plate of the first capacitor is coupled with a grid electrode of the driving transistor; a first pole plate of the second capacitor is coupled with the first reference voltage signal line, and a second pole plate of the second capacitor is coupled with a second pole of the driving transistor; the orthographic projection of the first capacitor on the substrate is overlapped with the orthographic projection of the active layer of the driving transistor on the substrate.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to display panels and display devices. Background Technology

[0002] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) possess advantages such as self-illumination and low energy consumption, making them one of the hot topics in current display device application research. Generally, pixel circuits are used in display devices to drive the light-emitting devices to emit light. Utility Model Content

[0003] The display panel provided in this embodiment of the utility model includes:

[0004] The substrate includes multiple pixel circuits;

[0005] The pixel circuit includes: a driving transistor, a first capacitor, and a second capacitor; the first plate of the first capacitor is coupled to the second plate of the driving transistor, and the second plate of the first capacitor is coupled to the gate of the driving transistor.

[0006] The first plate of the second capacitor is coupled to the first reference voltage signal line, and the second plate of the second capacitor is coupled to the second terminal of the driving transistor.

[0007] The orthographic projection of the first capacitor onto the substrate overlaps with the orthographic projection of the active layer of the driving transistor onto the substrate.

[0008] In some possible implementations, the first terminal of the driving transistor is directly coupled to the first power supply signal line;

[0009] The orthographic projection of the first capacitor onto the substrate is adjacent to the orthographic projection of the first power signal line onto the substrate.

[0010] In some possible implementations, the first power signal line extends along a first direction, and the first capacitor extends along a second direction; the first direction and the second direction intersect each other.

[0011] In some possible implementations, the pixel circuit further includes: a first transistor;

[0012] The gate of the first transistor is coupled to the first reset signal line, the first terminal of the first transistor is coupled to the first initialization signal line, and the second terminal of the first transistor is coupled to the gate of the driving transistor.

[0013] The orthographic projection of the active layer of the first transistor onto the substrate overlaps with the orthographic projections of the first reset signal line and the first initialization signal line onto the substrate.

[0014] In some possible implementations, the orthographic projection of the first capacitor onto the substrate is located between the orthographic projections of the first power signal line and the first reset signal line onto the substrate.

[0015] In some possible implementations, the orthogonal projection of the second capacitor onto the substrate is adjacent to the orthogonal projection of the first reset signal line onto the substrate.

[0016] In some possible implementations, the pixel circuit further includes: a second transistor;

[0017] The gate of the second transistor is coupled to the scan signal line, the first terminal of the second transistor is coupled to the data signal line, and the second terminal of the second transistor is coupled to the gate of the driving transistor.

[0018] In some possible implementations, the active layer of the second transistor extends along the second direction;

[0019] The active layer of the second transistor is projected onto the substrate in a normal projection, located between the first power signal line and the active layer of the first transistor in a normal projection onto the substrate.

[0020] In some possible implementations, the pixel circuit further includes: a third transistor and a light-emitting device;

[0021] The gate of the third transistor is coupled to the light-emitting control signal line, the first terminal of the third transistor is coupled to the second terminal of the driving transistor, the second terminal of the third transistor is coupled to the first terminal of the light-emitting device, and the second terminal of the light-emitting device is coupled to the second power supply signal line.

[0022] In some possible implementations, the orthographic projection of the second capacitor onto the substrate overlaps with the orthographic projections of the first initialization signal line and the light emission control signal line onto the substrate.

[0023] In some possible implementations, the first reference voltage signal line, the second power signal line, and the data line extend along the second direction;

[0024] The second power signal line is projected onto the substrate between the data line and the first reference voltage signal line.

[0025] In some possible implementations, the pixel circuit further includes a fourth transistor;

[0026] The gate of the fourth transistor is coupled to the second reset signal line, the first terminal of the fourth transistor is coupled to the light-emitting device, and the second terminal of the fourth transistor is coupled to the second initialization signal line.

[0027] Wherein, the orthographic projection of the active layer of the fourth transistor onto the substrate overlaps with the orthographic projections of the second reset signal line and the second initialization signal line onto the substrate.

[0028] In some possible implementations, the orthographic projection of the second power signal line onto the substrate overlaps with the orthographic projections of the first transistor, the second transistor, the fourth transistor, the first capacitor, and the second capacitor onto the substrate.

[0029] In some possible implementations, the scan signal line, the first reset signal line, the first initialization signal line, the light emission control signal line, the second reset signal line, and the second initialization signal line extend along the first direction and are arranged at intervals along the second direction.

[0030] In some possible implementations, the signal loaded on the first reference voltage signal line is the same as the signal loaded on the second initialization signal line.

[0031] In some possible implementations, the signal loaded on the first reference voltage signal line is the same as the signal loaded on the first power supply signal line.

[0032] In some possible implementations, the orthographic projection of the first reference voltage signal line onto the substrate overlaps with the orthographic projections of the driving transistor, the first capacitor, and the second capacitor onto the substrate.

[0033] In some possible implementations, the plurality of pixel circuits includes: a first pixel circuit, a second pixel circuit, and a third pixel circuit;

[0034] The first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged at intervals along the first direction;

[0035] The first pixel circuit and the second pixel circuit are arranged symmetrically as mirror images;

[0036] The second pixel circuit and the third pixel circuit are arranged symmetrically.

[0037] The display device provided in this embodiment of the present invention includes the display panel described above. Attached Figure Description

[0038] Figure 1 Some layout structure diagrams of pixel circuits provided in embodiments of this utility model;

[0039] Figure 2 Some structural schematic diagrams of the pixel circuit provided in the embodiments of this utility model;

[0040] Figure 3 A schematic diagram of the layout structure of the first conductive layer in the pixel circuit provided in an embodiment of this utility model;

[0041] Figure 4 A schematic diagram of the layout structure of the superimposed first conductive layer and second conductive layer in the pixel circuit provided in the embodiment of this utility model;

[0042] Figure 5 A schematic diagram of the layout structure of the superimposed first conductive layer, second conductive layer and semiconductor layer in the pixel circuit provided in the embodiment of this utility model;

[0043] Figure 6 A schematic diagram of the layout structure of the superimposed first conductive layer, second conductive layer, semiconductor layer and third conductive layer in the pixel circuit provided in the embodiment of this utility model;

[0044] Figure 7 A schematic diagram of the layout structure of the pixel circuit provided in this embodiment of the present invention, comprising a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a first interlayer insulating layer, a second interlayer insulating layer, and a fourth conductive layer superimposed on it.

[0045] Figure 8 Other schematic diagrams of the pixel circuit provided in the embodiments of this utility model;

[0046] Figure 9 Further schematic diagrams of the pixel circuit provided in the embodiments of this utility model;

[0047] Figure 10 A schematic diagram of the layout structure of the superimposed first conductive layer, second conductive layer, semiconductor layer, third conductive layer, first interlayer insulating layer and second interlayer insulating layer in the pixel circuit provided in the embodiment of this utility model;

[0048] Figure 11 Some signal timing diagrams provided for embodiments of this utility model;

[0049] Figure 12 Other signal timing diagrams provided for embodiments of this utility model. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Furthermore, the embodiments and features in the embodiments of this utility model can be combined with each other without conflict. Based on the described embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0051] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0052] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this utility model. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout the drawings.

[0053] In some embodiments of this utility model, the display device provided by this utility model may include a display panel. The display panel may include a substrate. The substrate may include a display area and a non-display area (i.e., the area in the substrate other than the area surrounded by the display area). The display area may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of the same color or multiple sub-pixels of different colors. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following description uses a pixel unit including red sub-pixels, green sub-pixels, and blue sub-pixels as an example.

[0054] In this embodiment of the invention, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display an image. Due to process technology and device aging, the threshold voltage Vth of the driving transistor may be non-uniform, resulting in variations in the current flowing through different light-emitting devices and uneven display brightness, thus affecting the overall image display effect. Therefore, existing technologies generally compensate for the threshold voltage Vth of the driving transistor to avoid non-uniformity. However, in existing pixel circuits, threshold voltage compensation and data writing are generally performed simultaneously. Nowadays, customers have increasingly strong demands for high-frequency displays, which leads to compression of the scanning time of the pixel circuit in a row of sub-pixels, making it impossible to properly compensate for the threshold voltage Vth of the driving transistor and achieve high-frequency driving.

[0055] The display panel provided in this embodiment of the utility model, such as Figure 1 and Figure 2 As shown, it includes: a substrate 100, which includes a plurality of pixel circuits 10;

[0056] Pixel circuit 10 includes: driving transistor T0, first capacitor C1 and second capacitor C2; the first plate of the first capacitor C1 is coupled to the second plate of the driving transistor T0, and the second plate of the first capacitor C1 is coupled to the gate of the driving transistor T0.

[0057] The first plate of the second capacitor C2 is coupled to the first reference voltage signal line VREF1, and the second plate of the second capacitor is coupled to the second terminal of the driving transistor T0.

[0058] The orthographic projection of the first capacitor C1 onto the substrate 100 overlaps with the orthographic projection of the active layer of the driving transistor T0 onto the substrate 100.

[0059] This embodiment of the invention, through the cooperation of the driving transistor, the first capacitor, and the second capacitor in the pixel circuit, can compensate for the threshold voltage of the driving transistor, thereby avoiding non-uniformity in the threshold voltage of the driving transistor. Furthermore, the first plate of the first capacitor is coupled to the second electrode of the driving transistor, and the second plate of the first capacitor is coupled to the gate of the driving transistor; the first plate of the second capacitor is coupled to the first reference voltage signal line, and the second plate of the second capacitor is coupled to the second electrode of the driving transistor; the orthographic projection of the first capacitor onto the substrate overlaps with the orthographic projection of the active layer of the driving transistor onto the substrate; this increases the area of ​​the first or second capacitor, thereby increasing its capacitance value, reducing the proportion of parasitic capacitance at the gate of the driving transistor, avoiding interference from parasitic capacitance affecting the driving current generated by the driving transistor, and thus avoiding affecting the display effect and improving display quality.

[0060] For example, a substrate may include a first conductive layer 110, a first insulating layer, a second conductive layer 120, a second insulating layer, a semiconductor layer 130, a third insulating layer, a third conductive layer 140, a first interlayer insulating layer 150, a second interlayer insulating layer 160, a fourth conductive layer 170, a fourth insulating layer, and a fifth conductive layer 180, which are sequentially stacked on the substrate. The sequentially stacked first conductive layer 110, first insulating layer, second conductive layer 120, second insulating layer, semiconductor layer 130, third insulating layer, third conductive layer 140, first interlayer insulating layer 150, second interlayer insulating layer 160, fourth conductive layer 170, fourth insulating layer, and fifth conductive layer 180 can form a pixel circuit. For example, Figure 1 This is a schematic diagram of the structure consisting of a first conductive layer 110, a second conductive layer 120, a semiconductor layer 130, a third conductive layer 140, a first interlayer insulating layer 150, a second interlayer insulating layer 160, a fourth conductive layer 170, and a fifth conductive layer 180.

[0061] For example, the material of the semiconductor layer includes metal oxide semiconductor materials, such as IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials can also be used, which are not limited here. It should be noted that the semiconductor layer includes a source region, a drain region, and a channel region located between the source region and the drain region; wherein, the source region and the drain region can be conductive regions formed by doping with n-type impurities or p-type impurities.

[0062] For example, the materials of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be conductive materials. For example, conductive materials can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of this utility model do not limit the materials of each film layer.

[0063] For example, the first insulating layer, the second insulating layer, the third insulating layer, the interlayer insulating layer, and the fourth insulating layer are all formed of insulating materials. As needed, organic insulating materials, such as polyimide and resin materials, can be selected, or inorganic insulating materials, such as silicon oxide, silicon nitride, and silicon oxynitride, can be selected. The embodiments of this utility model do not specifically limit the materials of each film layer.

[0064] For example, Figure 3 This is a schematic diagram of the layout structure of the first conductive layer 110. Figure 4 This is a schematic diagram of the layout structure of the superimposed first conductive layer 110 and second conductive layer 120, wherein, as shown... Figure 3 As shown, the second plate C1-2 of the first capacitor C1 is disposed on the first conductive layer 110; as Figure 4 As shown, the first electrode C1-1 of the first capacitor C1 is disposed on the second conductive layer 120, and the orthographic projection of the second electrode C1-2 of the first capacitor C1 on the substrate 100 overlaps with the orthographic projection of the first electrode C1-1 of the first capacitor C1 on the substrate 100.

[0065] For example, such as Figure 3 As shown, the second plate C2-2 of the second capacitor C2 is disposed on the first conductive layer 110; as Figure 4 As shown, the first electrode C2-1 of the second capacitor C2 is disposed on the second conductive layer, and the orthographic projection of the second electrode C2-2 of the second capacitor C2 on the substrate 100 overlaps with the orthographic projection of the first electrode C2-1 of the second capacitor C2 on the substrate 100.

[0066] For example, Figure 5 This is a schematic diagram of the layout structure of the superimposed first conductive layer 110, second conductive layer 120, and semiconductor layer 130. Figure 6 This is a schematic diagram of the layout structure of the superimposed first conductive layer 110, second conductive layer 120, semiconductor layer 130, and third conductive layer 140, as shown below. Figure 5 As shown, the active layer T0-O of the driving transistor is disposed on the semiconductor layer 130; as Figure 6 As shown, the gate TO-G of the driving transistor is disposed on the third conductive layer 140.

[0067] In some embodiments of this utility model, such as Figure 1As shown, the first power signal line VDD extends along the first direction F1, and the first capacitor C1 extends along the second direction F2; the first direction F1 and the second direction F2 intersect each other.

[0068] For example, Figure 7 This is a schematic diagram of the layout structure of the superimposed first conductive layer 110, second conductive layer 120, semiconductor layer 130, third conductive layer 140, first interlayer insulating layer 150, second interlayer insulating layer 160 and fourth conductive layer 170, with the first power signal line VDD disposed on the fourth conductive layer 170.

[0069] In some embodiments of this utility model, such as Figure 1 and Figure 2 As shown, the pixel circuit 10 further includes: a first transistor T1; wherein, the gate of the first transistor T1 is coupled to the first reset signal line Reset1, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the gate of the driving transistor T0.

[0070] like Figure 7 As shown, the orthographic projection of the active layer of the first transistor T1 onto the substrate 100 overlaps with the orthographic projections of the first reset signal line Reset1 and the first initialization signal line Vinit1 onto the substrate 100.

[0071] For example, the first transistor T1 can be turned on under the control of the effective level of the first reset signal transmitted on the first reset signal line Reset1, and can be turned off under the control of the ineffective level of the first reset signal. For example, if the first transistor T1 is set as a P-type transistor, then the effective level of the first reset signal is low, and the ineffective level of the first reset signal is high. Alternatively, if the first transistor T1 is set as an N-type transistor, then the effective level of the first reset signal is high, and the ineffective level of the first reset signal is low.

[0072] For example, such as Figure 5 As shown, the active layer T1-O of the first transistor T1 extends along the second direction F2; the active layer T1-O of the first transistor is disposed on the semiconductor layer 130; as Figure 6 As shown, the gate T1-G of the first transistor is disposed on the third conductive layer 140.

[0073] For example, such as Figure 7 As shown, the first reset signal line Reset1 and the first initialization signal line Vinit1 are disposed on the fourth conductive layer 170.

[0074] In some embodiments of this utility model, such as Figure 7As shown, the orthographic projection of the active layer of the first transistor T1 onto the substrate 100 overlaps with the orthographic projections of the first reset signal line Reset1 and the first initialization signal line Vinit1 onto the substrate 100.

[0075] In some embodiments of this utility model, such as Figure 7 As shown, the orthographic projection of the first capacitor C1 onto the substrate 100 is located between the orthographic projections of the first power signal line VDD and the first reset signal line Reset1 onto the substrate 100.

[0076] In some embodiments of this utility model, such as Figure 1 As shown, the orthographic projection of the second capacitor C2 onto the substrate 100 is adjacent to the orthographic projection of the first reset signal line Reset1 onto the substrate 100.

[0077] In some embodiments of this utility model, such as Figure 1 and Figure 2 As shown, the pixel circuit 10 further includes a second transistor T2; wherein the gate of the second transistor T2 is coupled to the scan signal line Gate, the first terminal of the second transistor T2 is coupled to the data signal line Data, and the second terminal of the second transistor T2 is coupled to the gate of the driving transistor T0.

[0078] For example, the second transistor T2 can be turned on under the control of the effective level of the scan signal transmitted on the scan signal line Gate, and can be turned off under the control of the ineffective level of the scan signal. For example, if the second transistor T2 is set as a P-type transistor, then the effective level of the scan signal is low and the ineffective level of the scan signal is high. Alternatively, if the second transistor T2 is set as an N-type transistor, then the effective level of the scan signal is high and the ineffective level of the scan signal is low.

[0079] For example, such as Figure 5 As shown, the active layer T2-O of the second transistor is disposed on the semiconductor layer 130; as Figure 6 As shown, the gate T2-G of the second transistor is disposed on the third conductive layer 140.

[0080] For example, such as Figure 7 As shown, the scan signal line Gate is located on the fourth conductive layer 170.

[0081] For example, such as Figure 1 As shown, the data signal line Data is located on the fifth conductive layer 180.

[0082] In some embodiments of this utility model, such as Figure 5 As shown, the active layer T2-O of the second transistor T2 extends along the second direction F2.

[0083] In some embodiments of this utility model, such as Figure 7 As shown, the orthographic projection of the active layer of the second transistor T2 onto the substrate 100 is located between the first power signal line VDD and the orthographic projection of the active layer of the first transistor T1 onto the substrate 100.

[0084] In some embodiments of this utility model, such as Figure 7 As shown, the orthographic projection of the active layer of the second transistor T2 onto the substrate 100 overlaps with the orthographic projection of the scan signal line Gate onto the substrate 100.

[0085] In some embodiments of this utility model, such as Figure 1 and Figure 2 As shown, the pixel circuit 10 further includes: a third transistor T3 and a light-emitting device L; wherein, the gate of the third transistor T3 is coupled to the light-emitting control signal line EM1, the first terminal of the third transistor T3 is coupled to the second terminal of the driving transistor T0, the second terminal of the third transistor T3 is coupled to the first terminal of the light-emitting device L; the second terminal of the light-emitting device L is coupled to the second power supply signal line VSS.

[0086] For example, the third transistor T3 can be turned on under the control of the effective level of the light-emitting control signal transmitted on the light-emitting control signal line EM1, and can be turned off under the control of the ineffective level of the light-emitting control signal. For example, if the third transistor T3 is set as a P-type transistor, then the effective level of the light-emitting control signal is low, and the ineffective level of the light-emitting control signal is high. Alternatively, if the third transistor T3 is set as an N-type transistor, then the effective level of the light-emitting control signal is high, and the ineffective level of the light-emitting control signal is low.

[0087] For example, such as Figure 5 As shown, the active layer T3-O of the third transistor is disposed on the semiconductor layer 130; as Figure 6 As shown, the gate T3-G of the third transistor is disposed on the third conductive layer 140.

[0088] For example, such as Figure 7 As shown, the light emission control signal line EM1 is disposed on the fourth conductive layer 170.

[0089] For example, such as Figure 1 As shown, the second power signal line VSS is located on the fifth conductive layer 180.

[0090] For example, such as Figure 5 As shown, the active layer T3-O of the third transistor and the active layer T0-O of the driving transistor are integrated.

[0091] For example, the light-emitting device L may include at least one of a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). For example, the light-emitting device L may include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer may include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0092] In some embodiments of this utility model, such as Figure 7 As shown, the orthographic projection of the second capacitor C2 onto the substrate 100 overlaps with the orthographic projections of the first initialization signal line Vinit1 and the light emission control signal line EM1 onto the substrate 100.

[0093] In some embodiments of this utility model, such as Figure 1 As shown, the first reference voltage signal line Vref1, the second power signal line VSS, and the data line Data extend along the second direction F2;

[0094] The orthographic projection of the second power signal line VSS onto the substrate 100 lies between the orthographic projections of the data line DA and the first reference voltage signal line Vref1 onto the substrate 100.

[0095] In some embodiments of this utility model, such as Figure 1 and Figure 2 As shown, the pixel circuit 10 further includes: a fourth transistor T4; wherein, the gate of the fourth transistor T4 is coupled to the second reset signal line Reset2, the first electrode of the fourth transistor T4 is coupled to the light-emitting device L, and the second electrode of the fourth transistor T4 is coupled to the second initialization signal line Vinit2.

[0096] like Figure 7 As shown, the orthographic projection of the active layer of the fourth transistor T4 onto the substrate 100 overlaps with the orthographic projection of the second reset signal line Reset2 and the second initialization signal line Vinit2 onto the substrate 100.

[0097] For example, the fourth transistor T4 can be turned on under the control of the effective level of the second reset signal transmitted on the second reset signal line Reset2, and can be turned off under the control of the ineffective level of the second reset signal. For example, if the fourth transistor T4 is set as a P-type transistor, then the effective level of the second reset signal is low, and the ineffective level of the second reset signal is high. Alternatively, if the fourth transistor T4 is set as an N-type transistor, then the effective level of the second reset signal is high, and the ineffective level of the second reset signal is low.

[0098] For example, such as Figure 5 As shown, the active layer T4-O of the fourth transistor is integrally formed with the active layer T3-O of the third transistor; the active layer T4-O of the fourth transistor is disposed on the semiconductor layer 130; as Figure 6 As shown, the gate T3-G of the fourth transistor is disposed on the third conductive layer 140.

[0099] For example, such as Figure 7 As shown, the second reset signal line Reset2 and the second initialization signal line Vinit2 are disposed on the fourth conductive layer 170.

[0100] In some embodiments of this utility model, such as Figure 1 As shown, the orthographic projection of the second power signal line VSS onto the substrate 100 overlaps with the orthographic projections of the first transistor T1, the second transistor T2, the fourth transistor T4, the first capacitor C1, and the second capacitor C2 onto the substrate 100.

[0101] In some embodiments of this utility model, such as Figure 7 As shown, the scan signal line Gate, the first reset signal line Reset1, the first initialization signal line Vinit1, the light emission control signal line EM1, the second reset signal line Reset2, and the second initialization signal line Vinit2 all extend along the first direction F1 and are arranged at intervals along the second direction F2.

[0102] In specific implementation, depending on the type of transistor and the signal of its gate, the first terminal of the transistor can be used as its source and the second terminal as its drain; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction will be made here.

[0103] It should be noted that, as Figure 1As shown, the display panel also includes: a first sub-power signal line VDD1, a first sub-initialization signal line Vinit11, and a second sub-initialization signal line Vinit21; ​​wherein, the first sub-power signal line VDD1, the first sub-initialization signal line Vinit11, and the second sub-initialization signal line Vinit21 are all located in the fifth conductive layer 180; and, the first sub-power signal line VDD1, the first sub-initialization signal line Vinit11, and the second sub-initialization signal line Vinit21 all extend along the second direction F2.

[0104] For example, such as Figure 1 As shown, the orthographic projection of the first sub-initialization signal line Vinit11 onto the substrate 100 is adjacent to the orthographic projection of the first sub-power signal line VDD1 onto the substrate 100.

[0105] For example, such as Figure 1 As shown, the orthographic projection of the second sub-initialization signal line Vinit21 onto the substrate 100 is located between the orthographic projections of the data signal line Data and the first sub-power signal line VDD1 onto the substrate 100.

[0106] For example, the first sub-power signal line VDD1 can be coupled to the first power signal line VDD through a via, the first sub-initialization signal line Vinit11 can be coupled to the first initialization signal line Vinit1 through a via, and the second sub-initialization signal line Vinit21 can be coupled to the second initialization signal line Vinit2 through a via. This arrangement will make the first sub-power signal line VDD1 and the first power signal line VDD arranged in a grid pattern when projected onto the substrate 100, the first sub-initialization signal line Vinit11 and the first initialization signal line Vinit11 arranged in a grid pattern when projected onto the substrate 100, and the second sub-initialization signal line Vinit21 and the second initialization signal line Vinit2 arranged in a grid pattern when projected onto the substrate 100. This arrangement is beneficial for signal transmission and ensures signal stability.

[0107] In some embodiments of this utility model, such as Figure 8 As shown, the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first initialization signal line Vinit1.

[0108] For example, since the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first initialization signal line Vinit1, the signal of the first initialization signal line Vinit1 is more synchronized with the data voltage on the data line Data. Therefore, the influence on the gate of the driving transistor and the second electrode of the driving transistor is more synchronized, which can ensure the accuracy of the pixel circuit when it is working and improve the display quality.

[0109] In some embodiments of this utility model, such as Figure 9 As shown, the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first power supply signal line VDD.

[0110] For example, since the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first power signal line VDD, and the resistance of the first power signal line VDD is smaller than the resistance of the first initialization signal line Vinit1, the resistance of the pixel circuit can be reduced, current loss and heat generation of the pixel circuit can be avoided, thereby improving the display quality.

[0111] For example, such as Figure 1 As shown, when the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first power signal line VDD, that is, the first reference voltage signal line Vref1 and the first sub-power signal line VDD1 are the same signal line, that is, the first reference voltage signal line Vref1 is coupled to the first power signal line VDD through a via.

[0112] In some embodiments of this utility model, such as Figure 1 As shown, when the signal loaded on the first reference voltage signal line Vref1 is the same as the signal loaded on the first power supply signal line VDD, the orthographic projection of the first reference voltage signal line Vref1 on the substrate 100 overlaps with the orthographic projections of the driving transistor T0, the first capacitor C1, and the second capacitor C2 on the substrate 100.

[0113] For example, the first reference voltage signal line Vref1 is disposed on the fifth conductive layer 180.

[0114] For example, Figure 10 This is a schematic diagram of the layout structure of the superimposed first conductive layer 110, second conductive layer 120, semiconductor layer 130, third conductive layer 140, first interlayer insulating layer 150, and second interlayer insulating layer 160, wherein there are multiple vias (e.g. Figure 10 K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11, K12, K13, K14, K15) pass through the first interlayer insulation layer 150 and the second interlayer insulation layer 160; wherein, as Figure 1 , Figure 7 as well as Figure 10As shown, the gate of the second transistor T2 is coupled to the scan signal line Gate through via K2; the first terminal of the second transistor T2 is coupled to the data signal line DA through via K1; and the second terminal of the second transistor is coupled to the gate (i.e., the first node N1) of the driving transistor T0 through via K3. The first node N1 (which may be a transition portion located in the fourth conductive layer 170) is coupled to the gate of the driving transistor T0 through via K4. The first plate of the first capacitor C1 is coupled to the second terminal (i.e., the second node N2) of the driving transistor T0 through via K7; the second plate of the first capacitor C1 is coupled to the gate (i.e., the first node N1) of the driving transistor T0 through via K5; the second node N2 (which may be a transition portion located in the fourth conductive layer 170) is coupled to the second terminal of the driving transistor T0; the gate of the first transistor T1 is coupled to the first reset signal line Reset1 through via K8. The first electrode of transistor T1 is coupled to the first initialization signal line Vinit1 through via K9; the second electrode of transistor T1 is coupled to the gate (i.e., the first node N1) of driving transistor T0 through via K6; the first plate of second capacitor C2 is coupled to the first reference voltage signal line Vref1 through via K10; the transition part Z1 (located in the fourth conductive layer 170) is coupled to the second electrode of driving transistor T0 through via K12; the second plate of second capacitor C2 is coupled to the transition part Z1 (located in the fourth conductive layer 170) through via K13; the gate of third transistor T3 is coupled to the light emission control signal line EM11 through via K11; the second electrode of third transistor T3 is coupled to the light emission device L through via K14; the first electrode of fourth transistor T4 is coupled to the light emission device L through via K14; the second electrode of fourth transistor T4 is coupled to the second initialization signal line Vinit2 through via K15.

[0115] This embodiment of the invention, through the cooperation of the driving transistor, the first capacitor, the second capacitor, the first transistor, the second transistor, the third transistor, and the fourth transistor in the pixel circuit, enables separate threshold voltage compensation and data writing. This allows the threshold voltage compensation time to be no longer limited by the scan time of the pixel circuit in one row of sub-pixels, thus better realizing threshold voltage compensation of the driving transistor and achieving high-frequency driving.

[0116] Furthermore, since the number of transistors in the pixel circuit of this utility model embodiment is relatively small, the area of ​​the first capacitor and the second capacitor can be increased, thereby reducing the proportion of parasitic capacitance, improving display quality, and can be applied to display products with higher resolution. Also, since the number of transistors in the pixel circuit is relatively small, fewer gate driving circuits can be used (for example, only 4 sets of gate driving circuits are needed in this embodiment), making it easier to achieve a narrow bezel and meet the user's demand for a narrow bezel.

[0117] In some embodiments of this utility model, such as Figure 1 As shown, the plurality of pixel circuits 10 include: a first pixel circuit 101, a second pixel circuit 102, and a third pixel circuit 103;

[0118] The first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 are arranged sequentially at intervals along the first direction F1;

[0119] The first pixel circuit 101 and the second pixel circuit 102 are arranged in a mirror symmetrical manner;

[0120] The second pixel circuit 102 and the third pixel circuit 103 are arranged symmetrically.

[0121] The following is based on Figure 8 Taking the pixel circuit shown as an example, combined with Figure 11 The signal timing diagram shown describes the operation of the pixel circuit provided in this embodiment of the present invention.

[0122] In the embodiments of this utility model, such as Figure 11 As shown, em1 represents the light emission control signal transmitted on the light emission control signal line EM1, reset2 represents the second reset signal transmitted on the second reset signal line Reset2, reset1 represents the first reset signal transmitted on the first reset signal line Reset1, and gate represents the scan signal transmitted on the scan signal line Gate.

[0123] Furthermore, select the initialization phase F1, threshold compensation phase F2, data writing phase F3, reset phase F4, and light emission phase F5 in a display frame.

[0124] During the initialization phase F1, the first transistor T1 is turned on under the control of the high level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned on under the control of the high level of the light emission control signal em1, and the fourth transistor T4 is turned on under the control of the high level of the second reset signal reset2. The first transistor T1, when turned on, provides the signal on the first initialization signal line Vinit1 to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vinit1; the voltage value of the signal on the second node N2 is VN2 = vinit2; the fourth transistor T4, when turned on, provides the signal on the second initialization signal line Vinit2 to the second terminal of the third transistor T3 (i.e., the third node N3); then the voltage value of the signal on the third node N3 is VN3 = vinit2; the third transistor, when turned on, connects the third node N3 to the second terminal of the driving transistor T0 (i.e., the second node N2); then the voltage value of the signal on the second node N2 is VN2 = vinit2; where vinit1 represents the voltage value of the signal on the first initialization signal line Vinit1, and vinit2 represents the voltage value of the signal on the second initialization signal line Vinit2;

[0125] During the threshold compensation stage F2, the first transistor T1 is turned on under the control of the high level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned off under the control of the low level of the light emission control signal em1, and the fourth transistor T4 is turned off under the control of the low level of the second reset signal reset2. The turned-on first transistor T1 provides the signal on the first initialization signal line Vinit1 to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vinit1; the threshold voltage Vth of the driving transistor T0 is compensated. After the threshold voltage Vth compensation is completed, the voltage value of the signal on the second node N2 is VN2 = vinit1 - Vth. Here, the first reset signal reset1 is at a high level for a period of time greater than or equal to 1H, where 1H represents the time for scanning one row of sub-pixels.

[0126] During the data writing phase F3, the first transistor T1 is cut off under the control of the low level of the first reset signal reset1, the second transistor T2 is turned on under the control of the high level of the scan signal gate, the third transistor T3 is cut off under the control of the low level of the light emission control signal em1, and the fourth transistor T4 is cut off under the control of the low level of the second reset signal reset2. The turned-on second transistor T2 transmits the data voltage vda on the data signal line Data to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vda; the driving transistor T0 is in the on state, and since the second capacitor C2 performs voltage division, the voltage value of the signal on the second node N2 is VN2 = vinit1 - Vth + [c1 / (c1+c2)]*(vda-vinit1), where c1 represents the capacitance value of the first capacitor C1, c2 represents the capacitance value of the second capacitor C2, and vda represents the data voltage vda on the data signal line Data. The scan signal gate is typically high for 1 hour.

[0127] During the reset phase F4, the first transistor T1 is cut off under the control of the low level of the first reset signal reset1, the second transistor T2 is cut off under the control of the low level of the scan signal gate, the third transistor T3 is cut off under the control of the low level of the light emission control signal em1, and the fourth transistor T4 is turned on under the control of the high level of the second reset signal reset2. The turned-on fourth transistor T4 provides the signal on the second initialization signal line Vinit2 to the second terminal (i.e., the third node N3) of the third transistor T3; then the voltage value of the signal on the third node N3 is VN3 = vinit2. This phase eliminates the difference in the voltage of the signal on the third node N3 caused by the difference in transistors at different positions due to process and other reasons, which was coupled to different voltages in the first three phases. This avoids the problem of inconsistent voltage of the signal on the third node N3 in different pixel circuits when multiple pixel circuits are lit, thereby further improving the display quality.

[0128] During the light-emitting stage F5, the first transistor T1 is turned off under the control of the low level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned on under the control of the high level of the light-emitting control signal em1, and the fourth transistor T4 is turned off under the control of the low level of the second reset signal reset2. The conducting third transistor connects the third node N3 to the second terminal (i.e., the second node N2) of the driving transistor T0. In other words, the conducting third transistor T3 connects the second terminal of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. At this time, the voltage value of the signal on the third node N3 is VN3 = Voled + vsss; where Voled represents the voltage value of the light-emitting device L, and vsss represents the voltage value of the second power supply terminal VSS. At this time, the voltage difference between the gate and source of the driving transistor T0 is Vgs = VN1 - VN2 = vda - vinit1 + Vth - [c1 / (c1 + c2)] * (vda - vinit1). The driving transistor T0 is in a saturated state and generates a current Ioled = 1 / 2 * k * {vda - vinit1 - [c1 / (c1 + c2)] * (vda - vinit1)}^2; where... μ represents the mobility of the driving transistor T0, C ox This represents the gate insulation layer capacitance per unit area of ​​the driving transistor T0. This represents the channel width-to-length ratio of the driving transistor T0.

[0129] The following is based on Figure 8 Taking the pixel circuit shown as an example, combined with Figure 12 The signal timing diagram shown describes the operation of the pixel circuit provided in this embodiment of the present invention.

[0130] For example, Figure 12 The signal timing diagram shown is compared to Figure 11 The signal timing diagram shown is as follows. Figure 12 There is no Figure 11 The reset phase F4 in the middle can be set so that the light-emitting device L can respond and emit light more quickly, that is, improve the response speed. In addition, by removing the reset phase, the time occupied by the light-emitting phase may be longer, which can extend the light-emitting time of the light-emitting device.

[0131] In the embodiments of this utility model, such as Figure 12 As shown, em1 represents the light emission control signal transmitted on the light emission control signal line EM1, reset2 represents the second reset signal transmitted on the second reset signal line Reset2, reset1 represents the first reset signal transmitted on the first reset signal line Reset1, and gate represents the scan signal transmitted on the scan signal line Gate.

[0132] Furthermore, select the initialization phase F1, threshold compensation phase F2, data writing phase F3, and light emission phase F4 in a display frame.

[0133] During the initialization phase F1, the first transistor T1 is turned on under the control of the high level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned on under the control of the high level of the light emission control signal em1, and the fourth transistor T4 is turned on under the control of the high level of the second reset signal reset2. The first transistor T1, when turned on, provides the signal on the first initialization signal line Vinit1 to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vinit1; the voltage value of the signal on the second node N2 is VN2 = vinit2; the fourth transistor T4, when turned on, provides the signal on the second initialization signal line Vinit2 to the second terminal of the third transistor T3 (i.e., the third node N3); then the voltage value of the signal on the third node N3 is VN3 = vinit2; the third transistor, when turned on, connects the third node N3 to the second terminal of the driving transistor T0 (i.e., the second node N2); then the voltage value of the signal on the second node N2 is VN2 = vinit2; where vinit1 represents the voltage value of the signal on the first initialization signal line Vinit1, and vinit2 represents the voltage value of the signal on the second initialization signal line Vinit2;

[0134] During the threshold compensation stage F2, the first transistor T1 is turned on under the control of the high level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned off under the control of the low level of the light emission control signal em1, and the fourth transistor T4 is turned off under the control of the low level of the second reset signal reset2. The turned-on first transistor T1 provides the signal on the first initialization signal line Vinit1 to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vinit1; the threshold voltage Vth of the driving transistor T0 is compensated. After the threshold voltage Vth compensation is completed, the voltage value of the signal on the second node N2 is VN2 = vinit1 - Vth. Here, the first reset signal reset1 is at a high level for a period of time greater than or equal to 1H, where 1H represents the time for scanning one row of sub-pixels.

[0135] During the data writing phase F3, the first transistor T1 is cut off under the control of the low level of the first reset signal reset1, the second transistor T2 is turned on under the control of the high level of the scan signal gate, the third transistor T3 is cut off under the control of the low level of the light emission control signal em1, and the fourth transistor T4 is cut off under the control of the low level of the second reset signal reset2. The turned-on second transistor T2 transmits the data voltage vda on the data signal line Data to the gate of the driving transistor T0 (i.e., the first node N1); then the voltage value of the signal on the first node N1 is VN1 = vda; the driving transistor T0 is in the on state, and since the second capacitor C2 performs voltage division, the voltage value of the signal on the second node N2 is VN2 = vinit1 - Vth + [c1 / (c1+c2)]*(vda-vinit1), where c1 represents the capacitance value of the first capacitor C1, c2 represents the capacitance value of the second capacitor C2, and vda represents the data voltage vda on the data signal line Data. The scan signal gate is typically high for 1 hour.

[0136] During the light-emitting stage F4, the first transistor T1 is turned off under the control of the low level of the first reset signal reset1, the second transistor T2 is turned off under the control of the low level of the scan signal gate, the third transistor T3 is turned on under the control of the high level of the light-emitting control signal em1, and the fourth transistor T4 is turned off under the control of the low level of the second reset signal reset2. The conducting third transistor connects the third node N3 to the second terminal (i.e., the second node N2) of the driving transistor T0. In other words, the conducting third transistor T3 connects the second terminal of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. At this time, the voltage value of the signal on the third node N3 is VN3 = Voled + vsss; where Voled represents the voltage value of the light-emitting device L, and vsss represents the voltage value of the second power supply terminal VSS. At this time, the voltage difference between the gate and source of the driving transistor T0 is Vgs = VN1 - VN2 = vda - vinit1 + Vth - [c1 / (c1 + c2)] * (vda - vinit1). The driving transistor T0 is in a saturated state and generates a current Ioled = 1 / 2 * k * {vda - vinit1 - [c1 / (c1 + c2)] * (vda - vinit1)}^2; where... μ represents the mobility of the driving transistor T0, C ox This represents the gate insulation layer capacitance per unit area of ​​the driving transistor T0. This represents the channel width-to-length ratio of the driving transistor T0.

[0137] Based on the same inventive concept, this utility model embodiment also provides a display device, including the display panel provided in the above-mentioned embodiment. The principle of this display device in solving the problem is similar to that of the aforementioned display panel, therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.

[0138] In specific implementations, in the embodiments of this utility model, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present utility model.

[0139] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0140] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.

Claims

1. A display panel, wherein, The pixel circuit comprises a driving transistor, a first capacitor and a second capacitor; a first plate of the first capacitor is coupled with a second electrode of the driving transistor, and a second plate of the first capacitor is coupled with a gate electrode of the driving transistor; a first plate of the second capacitor is coupled with a first reference voltage signal line, and a second plate of the second capacitor is coupled with the second electrode of the driving transistor; a projection of the first capacitor on the substrate substrate overlaps with a projection of the active layer of the driving transistor on the substrate substrate. a first electrode of the driving transistor is directly coupled with a first power signal line; a projection of the first capacitor on the substrate substrate is adjacent to a projection of the first power signal line on the substrate substrate.

2. The display panel of claim 1, wherein, the first power signal line extends along a first direction, and the first capacitor extends along a second direction; the first direction and the second direction intersect each other. the pixel circuit further comprises a first transistor; 3. The display panel of claim 2, wherein, a gate electrode of the first transistor is coupled with a first reset signal line, a first electrode of the first transistor is coupled with a first initialization signal line, and a second electrode of the first transistor is coupled with the gate electrode of the driving transistor; 4. The display panel of claim 2 or 3, wherein, a projection of the active layer of the first transistor on the substrate substrate overlaps with projections of the first reset signal line and the first initialization signal line on the substrate substrate. a projection of the first capacitor on the substrate substrate is located between projections of the first power signal line and the first reset signal line on the substrate substrate. a projection of the second capacitor on the substrate substrate is adjacent to a projection of the first reset signal line on the substrate substrate.

5. The display panel of claim 4, wherein, the pixel circuit further comprises a second transistor; 6. The display panel of claim 4, wherein, a gate electrode of the second transistor is coupled with a scan signal line, a first electrode of the second transistor is coupled with a data signal line, and a second electrode of the second transistor is coupled with the gate electrode of the driving transistor.

7. The display panel of claim 5, wherein, an active layer of the second transistor extends along the second direction; a projection of the active layer of the second transistor on the substrate substrate is located between a projection of the first power signal line and a projection of the active layer of the first transistor on the substrate substrate.

8. The display panel of claim 7, wherein, the pixel circuit further comprises a third transistor and a light emitting device; a gate electrode of the third transistor is coupled with a light emitting control signal line, a first electrode of the third transistor is coupled with the second electrode of the driving transistor, and a second electrode of the third transistor is coupled with a first electrode of the light emitting device; a second electrode of the light emitting device is coupled with a second power signal line.

9. The display panel of any of claims 5-8, wherein, a projection of the second capacitor on the substrate substrate has an overlapping area with projections of the first initialization signal line and the light emitting control signal line on the substrate substrate. the first reference voltage signal line, the second power signal line and the data signal line extend along the second direction; 10. The display panel of claim 9, wherein, a projection of the second power signal line on the substrate substrate is located between projections of the data signal line and the first reference voltage signal line on the substrate substrate.

11. The display panel of claim 9, wherein, the pixel circuit further comprises a fourth transistor; ​ 12. The display panel of claim 9, wherein, ​ A gate of the fourth transistor is coupled with a second reset signal line, a first electrode of the fourth transistor is coupled with the light emitting device, and a second electrode of the fourth transistor is coupled with a second initialization signal line. The active layer of the fourth transistor is in the projection of the substrate and overlaps with the second reset signal line and the second initialization signal line in the projection of the substrate.

13. The display panel of claim 12, wherein, The second power signal line has an overlapping area with the first transistor, the second transistor, the fourth transistor, the first capacitor and the second capacitor in the projection of the substrate.

14. The display panel of claim 12, wherein, The scan signal line, the first reset signal line, the first initialization signal line, the light emitting control signal line, the second reset signal line and the second initialization signal line extend along a first direction and are arranged in sequence along a second direction.

15. The display panel of claim 12, wherein, The signal loaded on the first reference voltage signal line is the same as the signal loaded on the second initialization signal line.

16. The display panel of claim 12, wherein, The signal loaded on the first reference voltage signal line is the same as the signal loaded on the first power signal line.

17. The display panel of claim 16, wherein, The first reference voltage signal line has an overlapping area with the driving transistor, the first capacitor and the second capacitor in the projection of the substrate.

18. The display panel of any of claims 1-3, wherein, The plurality of pixel circuits comprises a first pixel circuit, a second pixel circuit and a third pixel circuit. The first pixel circuit, the second pixel circuit and the third pixel circuit are arranged in sequence along a first direction. The first pixel circuit and the second pixel circuit are mirror-symmetrically arranged. The second pixel circuit and the third pixel circuit are symmetrically arranged.

19. A display device, wherein, Comprising: The display panel of any one of claims 1-18.

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