Display device

Abstract

The utility model relates to a display device, and the display device according to the embodiment comprises a substrate which comprises a first substrate layer and a first barrier layer; the metal layer is positioned on the substrate; the buffer layer is located on the metal layer; and a semiconductor layer located on the buffer layer, the first substrate layer including a first opening portion, and a side surface of the metal layer being located in the first opening portion on a plane.

Description

TECHNICAL FIELD

[0001] The utility model relates to display device. BACKGROUND

[0002] Display device is the device of display picture, it has liquid crystal display device (Liquid Crystal Display, LCD), organic light emitting display device (Organic Light Emitting Diode, OLED) etc. Such display device is used in such as mobile phone, navigation, digital camera, electronic book, portable game machine or various terminal etc. Variety electronic equipment.

[0003] In display device manufacturing process, as the method of crystallization of amorphous silicon to form polycrystalline silicon, mainly using excimer laser annealing (Excimer laser annealing, ELA) method or solid laser annealing (Solid laser annealing, SLA) method. SLA method is to use solid laser source to amplify the generation of high energy, and can use high laser energy to carry out heat treatment process. SUMMARY

[0004] The purpose of the embodiment is to provide a display device and a manufacturing method thereof, which can prevent film rupture of a semiconductor layer when crystallizing the semiconductor layer.

[0005] The display device according to an embodiment includes a substrate including a first base layer and a first barrier layer; a metal layer on the substrate; a buffer layer on the metal layer; and a semiconductor layer on the buffer layer. The first base layer includes a first opening portion, and a side surface of the metal layer is located within the first opening portion in a plan view.

[0006] The semiconductor layer can include a protrusion portion corresponding to the side surface and an upper surface of the metal layer, and a side surface of the protrusion portion is located within the first opening portion in a plan view.

[0007] The display device can further include a second base layer under the first base layer.

[0008] The first base layer can have a thickness thinner than a thickness of the second base layer.

[0009] The first base layer can have a thickness of half of a thickness of the second base layer.

[0010] The second base layer can include a second opening portion.

[0011] The side surface of the metal layer can be located within the second opening portion in a plan view.

[0012] An edge of the first opening portion can be aligned with an edge of the corresponding second opening portion.

[0013] An edge of the first opening portion can be misaligned with an edge of the second opening portion.

[0014] The first opening portion can not overlap the second opening portion.

[0015] A side surface of the protruding portion can be located within the second opening portion in a plan view.

[0016] A manufacturing method of a display device according to an embodiment includes: a step of forming a first base layer; a step of patterning the first base layer to form a first opening portion in the first base layer; a step of forming a first barrier layer on the first base layer; a step of forming a metal layer on the first barrier layer; a step of forming a buffer layer on the metal layer; and a step of forming a semiconductor layer on the buffer layer, a side surface of the metal layer being located within the first opening portion in a plan view.

[0017] In the step of forming the first opening portion, a laser can be irradiated to an upper surface or a lower surface of the first base layer to form the first opening portion.

[0018] The method can further include, before the step of forming the first base layer: a step of forming a second base layer; and a step of forming a second barrier layer on the second base layer.

[0019] The first base layer can have a thickness that is thinner than a thickness of the second base layer.

[0020] The method can further include, after the step of forming the second base layer: a step of patterning the second base layer to form a second opening portion.

[0021] In the step of forming the second opening portion, a laser can be irradiated to an upper surface or a lower surface of the second base layer to form the second opening portion.

[0022] A side surface of the metal layer can be located within the second opening portion in a plan view.

[0023] An edge of the first opening portion can be aligned with an edge of the corresponding second opening portion.

[0024] The first opening portion can not overlap the second opening portion.

[0025] (UTILITY EFFECT)

[0026] According to embodiments, it is possible to provide a display device and a manufacturing method thereof, which can prevent film breakage of a semiconductor layer when crystallizing the semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a sectional view showing a portion of a display region in a display device of an embodiment.

[0028] Figure 2 is a plan view showing a portion of a display region in a display device of an embodiment.

[0029] Figure 3 is a sectional view showing a portion of a display region in a display device of an embodiment.

[0030] Figures 4 to 6 are sectional views each showing a portion of a display region in a display device of an embodiment.

[0031] Figures 7 to 9 are sectional views each showing a portion of a display region in a display device of another embodiment.

[0032] Figure 10 is a sectional view showing a portion of a display region in a display device of a comparative example.

[0033] Figure 11 is a plan view showing Figure 5 is a graph showing temperature of a semiconductor layer, a buffer layer, and a substrate of a display device of an embodiment.

[0034] Figure 12 is a graph showing temperature of a semiconductor layer, a buffer layer, and a substrate of a display device of an embodiment. Figure 10

[0035] is a graph showing temperature of a buffer layer of a display device of an embodiment. Figure 13 Figure 5 is a graph showing temperature of a buffer layer of a display device of another embodiment.

[0036] Figure 14 Figure 7 is a graph showing temperature of a buffer layer of a display device of another embodiment.

[0037] Figure 15 is a graph showing temperature of a buffer layer of a display device of a comparative example. Figure 10

[0038] is a graph showing a shape on a plane of a display device of an embodiment. Figure 16

[0039] is a graph showing a shape on a cross section of a display device of an embodiment. Figure 17

[0040] is a graph showing Figure 18 Figure 10 ​​​A planar shape diagram of the display device of the comparative example shown.

[0041] Figure 19 is a cross-sectional view of the display device of the comparative example shown. Figure 10 A planar shape diagram of the display device of the comparative example shown.

[0042] Explanation of reference numerals

[0043] 100, 200, 300, 400: substrate; 110: buffer layer; 120: metal layer; 130: semiconductor layer; GI: gate insulating film; GE: gate electrode; IL1: first insulating film; SE: source electrode; DE: drain electrode; IL2: second insulating film; PDL: pixel definition film; OP1: pixel opening portion; EML: light emitting layer; E1: first electrode; E2: second electrode; 101: base layer; 102: barrier layer; 201, 301, 401: first base layer; 203, 303, 403: second base layer; 202, 302, 402: first barrier layer; 204, 304, 404: second barrier layer; 111: first buffer layer; 112: second buffer layer; 105: opening portion; 205, 305: first opening portion; 206, 306: second opening portion DETAILED DESCRIPTION

[0044] Hereinafter, a plurality of embodiments of the present application will be described in detail with reference to the accompanying drawings, so that an ordinarily skilled person in the art to which the present application pertains can easily implement the present application. The present application can be implemented in a variety of different forms, and is not limited to the embodiments described herein.

[0045] In order to clearly describe the present application, parts irrelevant to the description of the present application are omitted, and the same reference numerals are given to the same or similar constituent elements throughout the description.

[0046] Further, in order to facilitate the description, the size and thickness of each structure shown in the drawings are arbitrarily shown, and thus the present application is not necessarily limited to the contents shown in the drawings. In the drawings, in order to clearly express a plurality of layers and regions, the thicknesses thereof are exaggeratedly shown. Furthermore, in the drawings, in order to facilitate the description, the thicknesses of a part of the layers and regions are exaggeratedly shown.

[0047] Also, in the case where a portion is referred to as being "on" or "above" another portion, this means not only that the portion is directly on the other portion, but also that another portion is interposed therebetween. Conversely, in the case where a portion is referred to as being "directly on" another portion, this means that no other portion is interposed therebetween. Also, in the case where a portion is referred to as being "on" or "above" another portion, this means on or below the other portion as a reference, and does not mean that it must be "on" or "above" in the opposite direction of gravity.

[0048] Also, throughout the specification, when described as a portion "comprising" a constituent element, this means that other constituent elements can also be included unless specifically stated to the contrary, rather than excluding other constituent elements.

[0049] Also, throughout the specification, when referred to as being "on a plane", this means the case when viewed from above the portion of interest, and when referred to as being "on a cross section", this means the case when viewed from the side of the cross section of the portion of interest after being cut perpendicularly.

[0050] Hereinafter, referring to Figure 1 The outline structure of a display device of an embodiment will be described. Figure 1 is a cross-sectional view showing a portion of a display region in a display device of an embodiment.

[0051] Referring to Figure 1 The substrate 100 can include a substance having a rigid characteristic such as glass or a flexible substance composed of a polymer such as plastic, polyimide, or the like. According to an embodiment, the substrate 100 can be a single layer or a multi-layer structure including the above substances. For example, the substrate 100 can include one or more base layers and one or more barrier layers, and the base layers and the barrier layers can be alternately stacked. The barrier layer can prevent moisture, oxygen, or the like from permeating.

[0052] A buffer layer 110 can be located on the substrate 100. In the present specification, in the direction in which the substrate 100 is viewed from a plane, the direction in which the substrate 100 extends is denoted as a first direction DR1 and a second direction DR2, and the direction in which it is stacked on the substrate 100 is denoted as a third direction DR3. The buffer layer 110 can include an inorganic substance, and as an example, can include an inorganic insulating substance such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. According to an embodiment, the buffer layer 110 can be a single layer or a multi-layer structure including the above inorganic insulating substances. The buffer layer 110 can planarize the surface of the substrate 100 and can block the permeation of impurity elements. The buffer layer 110 can include hydrogen.

[0053] A metal layer 120 can be located on the substrate 100. The metal layer 120 can be located between the substrate 100 and the buffer layer 110. The metal layer 120 can include a metal or a metal alloy of copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), or the like. The metal layer 120 can be configured as a single layer or multiple layers.

[0054] A semiconductor layer 130 can be located on the buffer layer 110. The semiconductor layer 130 can include one of amorphous silicon, polysilicon, and an oxide semiconductor. As an example, the semiconductor layer 130 can include polysilicon, and more specifically, low temperature polysilicon (LTPS). The semiconductor layer 130 can include a channel region C, a source region S, and a drain region D, which are distinguished according to whether impurities are doped. The source region S and the drain region D can have a conductive characteristic corresponding to a conductor.

[0055] A polysilicon layer can be formed by irradiating laser light to an amorphous silicon layer of the semiconductor layer 130. For example, an SLA (Solid Laser Annealing) method that generates a laser beam having a short wavelength, a high power, and a high efficiency can be used. The SLA method is a process that amplifies a high energy using a solid laser source, and thus heat treatment can be performed using a high laser energy. In the process of crystallizing the amorphous silicon layer of the semiconductor layer 130 into the polysilicon layer, heat energy can be generated.

[0056] A gate insulating film GI can be located on the semiconductor layer 130. The gate insulating film GI can cover the semiconductor layer 130 and the substrate 100. The gate insulating film GI can include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. The gate insulating film GI can be a single layer or a multi-layer structure including the above inorganic insulating material.

[0057] A gate electrode GE can be located on the gate insulating film GI. The gate electrode GE can include a metal or a metal alloy of copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), or the like. The gate electrode GE can be configured as a single layer or multiple layers. In the semiconductor layer 130, a region overlapping the gate electrode GE in a planar direction can be the channel region C.

[0058] A first insulating film IL1 can be located on the gate electrode GE. The first insulating film IL1 can include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. The first insulating film IL1 can be a single layer or a multi-layer structure including the above inorganic insulating material.

[0059] The source electrode SE and the drain electrode DE can be positioned on the first insulating film IL1. The source electrode SE and the drain electrode DE are connected to the source region S and the drain region D of the semiconductor layer 130, respectively, using openings formed in the first insulating film IL1 and the gate insulating film GI. Thus, the aforementioned semiconductor layer 130, the gate electrode GE, the source electrode SE, and the drain electrode DE constitute a transistor. According to an embodiment, the transistor TFT can also include only the source region and the drain region of the semiconductor layer 130 instead of the source electrode SE and the drain electrode DE.

[0060] The source electrode SE and the drain electrode DE can include a metal or a metal alloy of aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), or the like. The source electrode SE and the drain electrode DE can be configured as a single layer or multiple layers. The source electrode SE and the drain electrode DE of another embodiment can be configured as three layers including an upper layer, an intermediate layer, and a lower layer, and the upper layer and the lower layer can include titanium (Ti), and the intermediate layer can include aluminum (Al).

[0061] The second insulating film IL2 can be positioned on the source electrode SE and the drain electrode DE. The second insulating film IL2 can cover the source electrode SE and the drain electrode DE. The second insulating film IL2 serves to planarize the surface of the substrate 100 on which the transistor is provided, and can be an organic insulating film and can include one or more substances selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin.

[0062] The first electrode E1 can be positioned on the second insulating film IL2. The first electrode E1 can also be referred to as an anode electrode, and can be configured as a transparent conductive oxide film or a single layer including a metal substance or multiple layers including the same. The transparent conductive oxide film can include indium tin oxide (ITO), poly-ITO, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or the like. The metal substance can include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), aluminum (Al), or the like.

[0063] The first electrode E1 can be physically and electrically connected to the drain electrode DE through an opening of the second insulating film IL2. Thus, the first electrode E1 can receive an output current to be delivered to a light-emitting layer EML described later from the drain electrode DE.

[0064] A pixel define film PDL and a spacer (not shown) can be positioned on the first electrode E1 and the second insulating film IL2. The pixel define film PDL includes a pixel opening portion OP1 overlapping at least a portion of the first electrode E1. At this time, the pixel opening portion OP1 can overlap a central portion of the first electrode E1 and can not overlap an edge of the first electrode E1. Thus, a size in a plane of the pixel opening portion OP1 can be smaller than a size in a plane of the first electrode E1. The pixel define film PDL can divide a formation position of the light emitting layer EML such that the light emitting layer EML is positioned on a portion exposed by the upper surface of the first electrode E1. The pixel opening portion OP1 can define a light emitting area of each pixel.

[0065] The pixel define film PDL and the spacer can each be an organic insulating film including one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. According to an embodiment, the pixel define film PDL can be formed as a black pixel define film (BPDL) including a black pigment.

[0066] The light emitting layer EML can be positioned within the pixel opening portion OP1 divided by the pixel define film PDL. The light emitting layer EML can include an organic or inorganic material that emits light of red, green, blue, or the like. The light emitting layer EML that emits light of red, green, blue, or the like can include a low molecular or high molecular organic material. Although Figure 1 The light emitting layer EML is shown as a single layer in FIG. 1, but in practice, auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer can also be included above and below the light emitting layer EML. The hole injection layer and the hole transport layer can be positioned at a lower portion of the light emitting layer EML, and the electron transport layer and the electron injection layer can be positioned at an upper portion of the light emitting layer EML. According to an embodiment, the light emitting layer EML can include quantum dots. The quantum dots (hereinafter, also referred to as semiconductor nanocrystals) can include a II-VI compound, a III-V compound, a IV-VI compound, a IV element or compound, a I-III-VI compound, a II-III-VI compound, a I-II-IV-VI compound, or a combination thereof. The quantum dots can not include cadmium.

[0067] The second electrode E2 can be located on the pixel definition film PDL and the light emitting layer EML. The second electrode E2, also called a cathode electrode, can be formed to include a transparent conductive layer of ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), and ITZO (Indium Tin Zinc Oxide), etc. Also, the second electrode E2 can have a semi-transparent property, in which case it can constitute a microcavity together with the first electrode E1. According to the microcavity structure, light of a specific wavelength can be emitted upward due to the interval between the two electrodes and the properties, as a result of which red, green, or blue can be displayed.

[0068] The first electrode E1, the light emitting layer EML, and the second electrode E2 can constitute one light emitting element ED.

[0069] An encapsulation layer (not shown) can be located on the second electrode E2. The encapsulation layer can include at least one inorganic film and at least one organic film.

[0070] Hereinafter, the structure of a display device according to an embodiment will be described with reference to Figure 2 and Figure 3 The structure of a display device according to an embodiment will be described. Figure 2 is a plan view illustrating a substrate 100, a metal layer 120, and a semiconductor layer 130 in a display device according to an embodiment. Figure 3 is a cross-sectional view illustrating a substrate 100, a buffer layer 110, a metal layer 120, and a semiconductor layer 130 in a display device according to an embodiment. Figure 3 is a cross-sectional view illustrating the display device shown in Figure 2 cut along the A1-A2 line and illustrated.

[0071] Referring to Figure 2 and Figure 3 The substrate 100 can include at least one base layer 101. The base layer 101 can include a flexible material composed of a polymer such as polyimide, polyamide, polyethyleneterephthalate, etc.

[0072] The substrate 100 can further include at least one barrier layer 102 located on the base layer 101. The barrier layer 102 can be located between the metal layer 120 and the base layer 101. The barrier layer 102 can include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), etc. The barrier layer 102 can be a single layer or a multi-layer structure including the above inorganic insulating material.

[0073] The metal layer 120 can be located between the substrate 100 and the buffer layer 110. The metal layer 120 can include an upper surface T1, a lower surface B1, and a side surface S1. The area of the lower surface B1 of the metal layer 120 can be greater than the area of the upper surface T1. The side surface S1 connects the lower surface B1 and the upper surface T1, and the side surface S1 can extend in a direction that is not parallel to the third direction DR3.

[0074] The buffer layer 110 can be located on the substrate 100 and the metal layer 120. The buffer layer 110 can include a first buffer layer 111 and a second buffer layer 112. The first buffer layer 111 can include silicon nitride (SiNx), and the second buffer layer 112 can include silicon oxide (SiOx). The hydrogen content of the first buffer layer 111 can be greater than the hydrogen content of the second buffer layer 112.

[0075] The semiconductor layer 130 can be located on the buffer layer 110. The semiconductor layer 130 can include a protruding portion 131 corresponding to the upper surface T1 and the side surface S1 of the metal layer 120. The side surface S2 of the protruding portion 131 of the semiconductor layer 130 can correspond to the side surface S1 of the metal layer 120, and the upper surface T2 of the protruding portion 131 can correspond to the upper surface T1 of the metal layer 120. A step of the semiconductor layer 130 can be formed with reference to the side surface S2 of the protruding portion 131 of the semiconductor layer 130, which is transferred upward in the shape of the side surface S1 of the metal layer 120.

[0076] The base layer 101 of the substrate 100 can include an opening portion 105. The opening portion 105 of the base layer 101 can be a hole in which the base layer 101 is removed in the thickness direction of the base layer 101, i.e., the third direction DR3.

[0077] Referring to Figure 2 The side surface S1 of the metal layer 120 can be located within the opening portion 105 of the base layer 101 in a plan view. The side surface S2 of the protruding portion 131 of the semiconductor layer 130 can be located within the opening portion 105 in a plan view. The opening portion 105 can overlap at least one of the side surface S1 of the metal layer 120 and the side surface S2 of the semiconductor layer 130 in the third direction DR3.

[0078] The opening portion 105 can be formed by patterning the base layer 101.

[0079] The opening portion 105 can be formed by etching the base layer 101 exposed from the photoresist film after forming the photoresist film that exposes a portion of the base layer 101. According to an embodiment, the opening portion 105 can be formed using laser cutting. For example, the opening portion 105 can be formed by removing a portion of the base layer 101 using microfabrication of a femto and / or pico laser, or the like. In this case, the laser can be irradiated to the lower portion and / or the upper portion of the base layer 101.

[0080] In the process of crystallizing the amorphous silicon layer of the semiconductor layer 130 into a polycrystalline silicon layer, heat energy can be released through the opening portion 105 of the substrate 100. Depending on the material of the base layer 101, the temperature of the upper side boundary surface of the base layer 101 can rise due to the heat accumulated during the crystallization process, but according to the present embodiment, heat is released through the opening portion 105 of the base layer 101, so that the temperature rise of the buffer layer 110 is less, and the diffusion of hydrogen contained in the buffer layer 110 toward the semiconductor layer 130 side can be reduced. Thus, film rupture of the semiconductor layer 130 due to hydrogen can be prevented. Further, in the vicinity of the step formed in the semiconductor layer 130, film rupture is likely to occur due to the relatively thin thickness and high surface energy of the semiconductor layer 130, but according to the present embodiment, film rupture in the vicinity of the step of the semiconductor layer 130 can be particularly prevented.

[0081] Hereinafter, the display device according to an embodiment will be described with reference to the drawings. Figures 4 to 6 A display device according to an embodiment will be described. Figures 4 to 6 FIGS. 1A, 1B, 1C, and 1D are cross-sectional views each illustrating a substrate 200, a buffer layer 110, a metal layer 120, and a semiconductor layer 130, etc. in a display device according to an embodiment.

[0082] Hereinafter, the display device according to an embodiment will be described with reference to the drawings. Figures 4 to 6 The substrate 200 according to an embodiment can include a plurality of base layers 201, 203. The substrate 200 can include a first base layer 201 and a second base layer 203 positioned below the first base layer 201. The first base layer 201 and the second base layer 203 can include a flexible material composed of a polymer such as polyimide, polyamide, polyethylene terephthalate, or the like.

[0083] The substrate 200 can include a plurality of barrier layers 202, 204. The substrate 200 can further include a first barrier layer 202 positioned above the first base layer 201 and a second barrier layer 204 positioned above the second base layer 203. The first barrier layer 202 and the second barrier layer 204 can include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like.

[0084] Hereinafter, the display device according to an embodiment will be described with reference to the drawings. Figure 4The first base layer 201 can comprise a first opening portion 205. The side S1 of the metal layer 120 can be located within the first opening portion 205 in the plane. According to embodiments, the side S2 of the protruding portion 131 of the semiconductor layer 130 can be located within the first opening portion 205 in the plane. The first opening portion 205 can overlap at least one of the side S1 of the metal layer 120 and the side S2 of the semiconductor layer 130 in the third direction DR3.

[0085] With reference to Figure 5 and Figure 6 , the first base layer 201 can comprise a first opening portion 205 and the second base layer 203 can comprise a second opening portion 206. The side S1 of the metal layer 120 can be located within the first opening portion 205 and / or the second opening portion 206 in the plane. According to embodiments, the side S2 of the protruding portion 131 of the semiconductor layer 130 can be located within the first opening portion 205 and / or the second opening portion 206 in the plane. The first opening portion 205 and / or the second opening portion 206 can overlap at least one of the side S1 of the metal layer 120 and the side S2 of the semiconductor layer 130 in the third direction DR3.

[0086] With reference to Figure 5 , the first opening portion 205 and the second opening portion 206 can be aligned in the third direction DR3. In particular, an edge of the first opening portion 205 can be aligned with an edge of the corresponding second opening portion 206 in the third direction DR3. The first opening portion 205 and the second opening portion 206 can overlap in the plane.

[0087] With reference to Figure 6 , the first opening portion 205 and the second opening portion 206 can be misaligned in the third direction DR3. In particular, an edge of the first opening portion 205 can be misaligned with an edge of the second opening portion 206 in the third direction DR3.

[0088] In the process of crystallizing the amorphous silicon layer of the semiconductor layer 130 into a polysilicon layer, heat energy can be released through the first opening portion 205 and / or the second opening portion 206. Depending on the material of the base layers 201, 203, the temperature of the upper side boundary surface of the first base layer 201 can rise due to the heat accumulated during the crystallization process, but according to the present embodiment, heat is released through the first opening portion 205 and / or the second opening portion 206, so that the temperature rise of the buffer layer 110 is small, and the diffusion of hydrogen contained in the buffer layer 110 toward the semiconductor layer 130 side can be reduced. Thus, film rupture of the semiconductor layer 130 caused by hydrogen can be prevented. Further, in the vicinity of the step formed in the semiconductor layer 130, film rupture is likely to occur due to the relatively thin thickness and high surface energy of the semiconductor layer 130, but according to the present embodiment, film rupture in the vicinity of the step of the semiconductor layer 130 can be particularly prevented.

[0089] Hereinafter, with reference to Figures 7 to 9 A display device according to another embodiment will be described. Figures 7 to 9 is a cross-sectional view showing a substrate 300, a buffer layer 110, a metal layer 120, a semiconductor layer 130, and the like in a display device according to another embodiment.

[0090] With reference to Figures 7 to 9 A display device according to an embodiment is mostly the same as the display device according to the previously described embodiment, but differs in the structure of the substrate 300. The substrate 300 according to an embodiment can include a plurality of base layers 301, 303, and the thickness of at least two of the plurality of base layers 301, 303 can be different from each other.

[0091] The substrate 300 can include a first base layer 301 and a second base layer 303 positioned below the first base layer 301. The first base layer 301 and the second base layer 303 can include a flexible material composed of a polymer such as polyimide, polyamide, polyethylene terephthalate, or the like.

[0092] The substrate 300 can further include a first barrier layer 302 positioned above the first base layer 301 and a second barrier layer 304 positioned above the second base layer 303. The first barrier layer 302 and the second barrier layer 304 can include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like.

[0093] With reference to Figure 7The thickness of the first base layer 301 can be thinner than the thickness of the second base layer 303. In one embodiment, the thickness of the first base layer 301 can be half of the thickness of the second base layer 303. For example, the first base layer 301 can be about 5 μm, and the second base layer 303 can be about 10 μm. In this specification, "about" can include an error range of 1 μm.

[0094] In the process of crystallizing the amorphous silicon layer of the semiconductor layer 130 into a polycrystalline silicon layer, the thinner the thickness of the first base layer 301, the more the thermal energy can diffuse downward. Thus, the temperature of the buffer layer 110 is less likely to rise, and the diffusion of hydrogen contained in the buffer layer 110 toward the semiconductor layer 130 side can be reduced. Therefore, the film rupture of the semiconductor layer 130 caused by hydrogen can be prevented.

[0095] Referring to Figure 8 The first base layer 301 can include a first opening portion 305. The side surface S1 of the metal layer 120 can be located within the first opening portion 305 in the plan view. According to an embodiment, the side surface S2 of the protruding portion 131 of the semiconductor layer 130 can be located within the first opening portion 305 in the plan view. The first opening portion 305 can overlap at least one of the side surface S1 of the metal layer 120 and the side surface S2 of the semiconductor layer 130 in the third direction DR3.

[0096] Referring to Figure 9 The first base layer 301 can include a first opening portion 305, and the second base layer 303 can include a second opening portion 306. The side surface S1 of the metal layer 120 can be located within the first opening portion 305 and / or the second opening portion 306 in the plan view. According to an embodiment, the side surface S2 of the protruding portion 131 of the semiconductor layer 130 can be located within the first opening portion 305 and / or the second opening portion 306 in the plan view. The first opening portion 305 and / or the second opening portion 306 can overlap at least one of the side surface S1 of the metal layer 120 and the side surface S2 of the semiconductor layer 130 in the third direction DR3.

[0097] Referring to Figure 9 The first opening portion 305 and the second opening portion 306 can be aligned in the third direction DR3. Specifically, an edge of the first opening portion 305 can be aligned with an edge of the corresponding second opening portion 306 in the third direction DR3.

[0098] According to an embodiment, the first opening portion 305 and the second opening portion 306 can be misaligned in the third direction DR3. Specifically, an edge of the first opening portion 305 can be misaligned with an edge of the second opening portion 306 in the third direction DR3.

[0099] In the process of crystallizing the amorphous silicon layer of the semiconductor layer 130 into a polysilicon layer, heat energy can be released through the first opening portion 305 and / or the second opening portion 306. Depending on the materials of the base layers 301, 303, the temperature of the upper side boundary surface of the first base layer 301 can increase due to the heat accumulated during the crystallization process, but according to the present embodiment, the heat is released through the first opening portion 305 and / or the second opening portion 306, so that the temperature increase of the buffer layer 110 is small, and the diffusion of hydrogen contained in the buffer layer 110 to the semiconductor layer 130 side can be reduced. Thus, the film rupture of the semiconductor layer 130 caused by hydrogen can be prevented. Further, in the step portion formed in the semiconductor layer 130, the film rupture is likely to occur due to the instability caused by the relatively thin thickness and high surface energy of the semiconductor layer 130, but according to the present embodiment, the film rupture in the step portion of the semiconductor layer 130 can be particularly prevented.

[0100] Hereinafter, the display device of the comparative example will be described with reference to Figure 10 The structure of the display device of the comparative example will be described. Figure 10 is a cross-sectional view showing a substrate 400, a buffer layer 110c, a metal layer 120c, a semiconductor layer 130c, and the like of the display device of the comparative example. The buffer layer 110c can include a first buffer layer 111c and a second buffer layer 112c.

[0101] With reference to Figure 10 , the display device of the comparative example is mostly the same as the display device of the embodiment of the present application described above, but there is a certain difference in the structure of the substrate 400. The substrate 400 can include a plurality of base layers 401, 403. The substrate 400 can include a first base layer 401 and a second base layer 403 located below the first base layer 401.

[0102] The substrate 400 can include at least one barrier layer 402, 404. The substrate 400 can further include a first barrier layer 402 located above the first base layer 401 and a second barrier layer 404 located above the second base layer 403.

[0103] In the display device of the comparative example, the base layers 401, 403 of the substrate 400 do not include opening portions.

[0104] Also, in the display device of the comparative example, the thickness of the first base layer 401 and the thickness of the second base layer 403 are substantially the same. For example, the thickness of the first base layer 401 and the second base layer 403 can be about 10 μm. In the present specification, "substantially" and "about" can include an error range of 1 μm.

[0105] Since the base layers 401, 403 do not include the opening portions, heat accumulated in the process of crystallizing the amorphous silicon layer of the semiconductor layer 130c into a polysilicon layer is not sufficiently released. The temperature at the upper side boundary surface of the first base layer 401 rises, causing the temperature of the buffer layer 110c to rise, and hydrogen contained in the buffer layer 110 diffuses toward the semiconductor layer 130 side. Therefore, film rupture of the semiconductor layer 130 caused by hydrogen occurs. In particular, in the vicinity of the step formed in the semiconductor layer 130, instability due to the relatively thin thickness and the relatively high surface energy of the semiconductor layer 130 causes film rupture to easily occur.

[0106] Hereinafter, the temperature distribution of the substrate of the display device of the embodiment of the present application and the display device of the comparative example will be described together with the above-described Figure 5 and Figure 10 Figure 11 and Figure 12 Figure 11 and Figure 12 are graphs showing the temperature of the semiconductor layer 130 to the substrate 200 of the display device of the embodiment of the present application and the temperature of the semiconductor layer 130c to the substrate 400 of the display device of the comparative example, respectively.

[0107] Figure 11 is a graph showing the temperature of the semiconductor layer 130, the buffer layer 110, and the substrate 200 when the amorphous silicon layer of the semiconductor layer 130 is crystallized into a polysilicon layer using the SLA method in the display device of the embodiment of the present application when the crystallization time t is 0.008 s. The cross-sectional view of the display device of the embodiment of the present application is shown in Figure 5 . Referring to Figure 5 , the first base layer 201 can include the first opening portion 205, and the second base layer 203 can include the second opening portion 206. The side surface S1 of the metal layer 120 can be positioned within the first opening portion 205 and the second opening portion 206 in the plan view.

[0108] Figure 11 The x-axis of Figure 5 shows the length of the semiconductor layer 130 in the first direction in the cross-sectional view of Figure 5 . The y-axis shows the depth of the display device from the upper surface of the semiconductor layer 130 in the cross-sectional view of

[0109] Figure 12 is a graph showing the temperature of the semiconductor layer 130c, the buffer layer 110c, and the substrate 400 when the amorphous silicon layer of the semiconductor layer 130c is crystallized into a polysilicon layer using the SLA method in the display device of the comparative example when the crystallization time t is 0.008 s. The cross-sectional view of the display device of the comparative example is shown in Figure 10 .

[0110] ​​Figure 12 The x-axis shows that in Figure 10 The length of semiconductor layer 130c in the first direction is shown in the cross-sectional view. The y-axis indicates the length of the semiconductor layer 130c in the first direction. Figure 10 The depth of the display device is shown in the cross-sectional view with reference to the upper surface of the semiconductor layer 130c.

[0111] by Figure 11 The vertical line A shown is (x = 2.4 × 10). 5 Based on nm, in one embodiment of the display device, when the thickness y = -1 μm, the temperature of the substrate 200 is in the range of 120°C to 160°C.

[0112] by Figure 12 The vertical line A shown is (x = 2.4 × 10). 5 Using nm as a reference, the temperature of the substrate 400 in the comparative example display device is in the range of 150°C to 200°C when the thickness is y = -1 μm.

[0113] Reference Figure 11 and Figure 12 In one embodiment, the temperature of the substrate 200 of the display device is lower than the temperature of the substrate 400 of the display device in the comparative example.

[0114] The following is consistent with the previous explanation. Figure 5 , Figure 7 as well as Figure 10 Together, refer to Figures 13 to 15 The temperature distribution of the buffer layer of a display device according to one embodiment of the present invention, a display device according to another embodiment, and a comparative example display device will be described. Figures 13 to 15 These are graphs showing the temperature of the buffer layer 110 of a display device according to one embodiment, the buffer layer 110 of a display device according to another embodiment, and the buffer layer 110c of a comparative example display device.

[0115] Figure 13 This is a graph showing the temperature T of the buffer layer 110 as a function of the crystallization time t in a display device according to an embodiment of the present invention, when the amorphous silicon layer of the semiconductor layer 130 is crystallized into a polycrystalline silicon layer using the SLA method. A cross-sectional view of a display device according to an embodiment is shown in [image missing]. Figure 5 . Reference Figure 13 The temperature T of the buffer layer 110 does not exceed 500℃ even after time t.

[0116] Figure 14 This is a graph showing the temperature of the buffer layer 110 versus crystallization time t in a display device according to another embodiment of the present invention, when the amorphous silicon layer of the semiconductor layer 130 is crystallized into a polycrystalline silicon layer using the SLA method. A cross-sectional view of the display device according to another embodiment is shown. Figure 7Referring to Figure 14 The temperature T of the buffer layer 110 does not exceed 500°C even after the time t.

[0117] Figure 15 is a graph showing the temperature of the buffer layer 110c of the display device of the comparative example corresponding to the crystallization time t when the amorphous silicon layer of the semiconductor layer 130c is crystallized into a polysilicon layer by the SLA method. The cross-sectional view of the display device of the comparative example is shown in Figure 10 Referring to Figure 15 The temperature T of the buffer layer 110c of the comparative example exceeds 500°C from about t = 2.00 x 10 -3 s.

[0118] Hereinafter, the shapes of the metal layer and the semiconductor layer of the display device of an embodiment of the present application and the display device of the comparative example are described in conjunction with the above-described Figure 5 and Figure 10 Referring to Figures 16 to 19 Figure 16 and Figure 17 are diagrams showing a part of the display device of an embodiment. Figure 18 and 19 are diagrams showing a part of the display device of the comparative example shown in Figure 10

[0119] Figure 16 is a diagram showing the planar shape of the metal layer 120 and the semiconductor layer 130 after the amorphous silicon layer of the semiconductor layer 130 is crystallized into a polysilicon layer by the SLA method in the display device of an embodiment of the present application. Figure 16 The planar shape of the patterned metal layer 120 and the semiconductor layer 130 covering the metal layer 120 is shown. Figure 17 is a diagram showing the cross-sectional shape of the metal layer 120 and the semiconductor layer 130 after the amorphous silicon layer of the semiconductor layer 130 is crystallized into a polysilicon layer by the SLA method in the display device of an embodiment of the present application. Referring to Figure 16 and Figure 17 It can be seen that no film breakage occurs on the film of the crystallized semiconductor layer 130.

[0120] Figure 18 is a diagram showing the planar shape of the metal layer 120c and the semiconductor layer 130c after the amorphous silicon layer of the semiconductor layer 130c is crystallized into a polysilicon layer by the SLA method in the display device of the comparative example. Figure 19 is a diagram showing the cross-sectional shape of the metal layer 120c and the semiconductor layer 130c after the amorphous silicon layer of the semiconductor layer 130c is crystallized into a polysilicon layer by the SLA method in the display device of the comparative example. Referring to Figure 18 and Figure 19 ​​It is found that film breakage occurs on the film of the crystallized semiconductor layer 130c, and thus the semiconductor layer 130c is lost L.

[0121] Although the above has carried on the detailed explanation to the embodiment of the utility model, the right scope of the utility model is not limited to this, the person skilled in the art utilizes the basic concept of the utility model defined in the appended claims to carry out multiple deformation and improvement ways, and all fall into the right scope of the utility model.

Claims

1. A display device comprising: a substrate including a first base layer and a first barrier layer, a metal layer over the substrate, a buffer layer over the metal layer, and a semiconductor layer over the buffer layer; the first base layer including a first opening portion, a side surface of the metal layer being located within the first opening portion in plan view.

2. The display device according to claim 1, wherein: the semiconductor layer includes a protruding portion corresponding to the side surface and an upper surface of the metal layer, a side surface of the protruding portion being located within the first opening portion in plan view.

3. The display device according to claim 1, further comprising: a second base layer under the first base layer.

4. The display device according to claim 3, wherein: a thickness of the first base layer is thinner than a thickness of the second base layer.

5. The display device according to claim 4, wherein: the thickness of the first base layer is half of the thickness of the second base layer.

6. The display device according to claim 3, wherein: the second base layer includes a second opening portion.

7. The display device according to claim 6, wherein: the side surface of the metal layer is located within the second opening portion in plan view.

8. The display device according to claim 7, wherein: an edge of the first opening portion is aligned with an edge of the corresponding second opening portion.

9. The display device according to claim 6, wherein: an edge of the first opening portion is not aligned with an edge of the second opening portion.

10. The display device according to claim 6, wherein: the first opening portion does not overlap the second opening portion. ​ ​

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