LCDI circuit and power line shielding monitoring circuit

Abstract

The utility model provides an LCDI circuit and a power line shielding monitoring circuit, which are used for interrupting alternating current from an alternating current power supply, and the alternating current power supply is connected to a load through an insulation middle line and an insulation phase line. The LCDI circuit includes: an insulating midline surrounded by a midline shield; an insulated phase line surrounded by a phase line shield, wherein the phase line shield is connectable to the neutral line shield; a power line fault circuit for monitoring the integrity of neutral and phase line shields and leakage current. The power line fault circuit includes: a non-linear device connectable to the neutral line shield; a bistable latching device for interrupting the alternating current from the alternating current power source; and a power supply circuit for providing a first rectified voltage waveform to the power line fault circuit and the phase line shield.

Description

[0001] Cross-reference to related applications

[0002] This application is a continuation-in-part application relating to the application listed below (the “Related Application”), namely U.S. Patent Application 18 / 168,341, filed February 13, 2023, entitled “LCDI Power Line Circuit,” with V.V. Aronmin as the first inventor. This application claims the benefit of the earliest known effective filing date of the Related Application (e.g., for a patent application other than a provisional patent application, the benefit of the earliest known priority date; for a provisional patent application, the benefit of 35 USC §119(e)), and, where the subject matter of the Related Application does not conflict with this application, by referencing the entire subject matter of the Related Application. This application also claims the benefit of the earliest known effective filing date of any and all parent, grandparent, great-grandparent, etc., applications of the Related Application, and, where the subject matter of these applications does not conflict with this application, by referencing the entire subject matter of those applications. Technical Field

[0003] This utility model relates to a leakage current detection and interruption (LCDI) power line circuit for detecting leakage current in power lines and shielding open circuit or fault detectors. Background Technology

[0004] With the widespread use of household appliances such as air conditioners, washing machines, and refrigerators, the safety of using these appliances is receiving increasing attention. These appliances typically have power cords that are one meter or longer.

[0005] Power cords can age due to prolonged use or break when moving appliances, potentially leading to high current leakage between the phase wire and the neutral or ground wire. Besides personal safety concerns, leakage current can also cause sparks, resulting in fires and property damage. Leakage current can be detected by monitoring a small test voltage or current on a conductive metal sheath surrounding a conductive shield that insulates the phase and neutral wires. This metal sheath is typically made by braiding fine copper wire, which usually surrounds an aluminum conductive shield.

[0006] Conductive metal sheaths can fail due to structural integrity failures (such as open circuits) or corrosion caused by electrochemical interactions between dissimilar metals (such as copper braids and aluminum sheaths). Failure of the metal sheath can prevent conventional LCDI circuits from detecting dangerous leakage currents. Traditional LCDI circuits that test the continuity of the metal sheath only test whether it is conductive or open-circuited. However, conventional LCDI circuits do not test for galvanic corrosion between dissimilar metals, which can cause hot spots on the power lines, indicating impending failure of the conductive metal sheath.

[0007] Furthermore, existing technology solutions typically provide circuitry for detecting open-circuit shielding (i.e., structural integrity failure) and separate circuitry for detecting leakage current. However, multiple circuits require more components, increased footprint, and longer production cycles. Therefore, there is a need for a single circuitry that detects leakage current, the structural integrity of the metal sheath, and corrosion of the metal sheath that may interfere with leakage current detection. Utility Model Content

[0008] This invention provides a power cord circuit for use in electrical appliances such as air conditioners, washing machines, and refrigerators.

[0009] According to one embodiment of the present invention, a leakage current detection interruptor (LCDI) circuit is provided for interrupting AC power from an AC power source connected to a load via an insulated neutral wire and an insulated phase wire. The LCDI circuit includes: an insulated neutral wire surrounded by a neutral wire shield (NWS); and an insulated phase wire surrounded by a phase wire shield (LWS); the phase wire shield is connected to the neutral wire shield. The LCDI circuit further includes a power line fault circuit (PCFC) for monitoring the integrity of the neutral wire shield and the phase wire shield, as well as leakage current. The power line fault circuit includes a nonlinear device (NLD) and a bistable latching device, the bistable latching device being used to interrupt the AC power from the AC power source via a relay. The LCDI circuit also includes a power supply circuit for providing a rectified voltage waveform to the power line fault circuit and the phase wire shield.

[0010] On the other hand, this invention provides a power line shield monitoring (PCSM) circuit for interrupting AC power from an AC power source connected to a load via an insulated neutral wire surrounded by a neutral wire shield (NWS) and an insulated phase wire surrounded by a phase wire shield (LWS), wherein the neutral wire shield and the phase wire shield are connected via a shielded connector. The PCSM circuit includes a nonlinear NPN transistor connectable to the neutral wire shield. The nonlinear NPN transistor includes a saturation mode, a cutoff mode, and an active mode. The PCSM circuit further includes: a base bias circuit for biasing the base of the NPN transistor, the base bias circuit including one or more base bias resistors, a neutral wire shield, a phase wire shield, and a shielded connector; and at least one collector bias resistor connectable to the collector and a bistable latch-up device. The NPN transistor, the base bias circuit, and the at least one collector bias resistor determine the mode of the NPN transistor. It also includes: a mechanically locked bipolar switch disposed between the AC power supply and the load; a relay for releasing the lock of the bipolar switch; and a bistable latching device connected to the nonlinear device and the relay for interrupting AC power from the AC power supply based on the mode of the nonlinear device. At least one capacitor connectable to the nonlinear device and the bistable latching device is also provided, as well as a power supply circuit for biasing the nonlinear device and the bistable latching device.

[0011] This invention also relates to a power line shield monitoring (PCSM) circuit for interrupting AC power from an AC power source connected to a load via an insulated neutral wire surrounded by a neutral wire shield (NWS) and an insulated phase wire shield surrounded by a phase wire shield (LWS), wherein the neutral wire shield and the phase wire shield are connected via shielded connectors. The PCSM circuit includes a nonlinear device (NLD) connectable to the neutral wire shield. The nonlinear device can be any suitable nonlinear device, such as a transistor having a collector, emitter, and base. The nonlinear device has several operating modes: a saturation mode, in which the nonlinear device acts as a short circuit; a cutoff mode, in which the nonlinear device acts as an open circuit; and an activation mode, in which the current through the nonlinear device is proportional to the bias current at the control port of the nonlinear device (the base of an NPN transistor configured as a common emitter, as described herein). The PCSM circuit further includes a bistable latch-up device connected to the nonlinear device for interrupting AC power from the AC power source based on the operating mode of the nonlinear device.

[0012] Various other features and advantages will become apparent from the following description. In this description, reference is made to the accompanying drawings, which form part of this invention, illustrating specific embodiments for carrying out this invention. These embodiments will be described in sufficient detail to enable those skilled in the art to practice this invention. It should be understood that other embodiments may be employed, and structural changes may be made without departing from the scope of this invention. This means that the following detailed description should not be considered limiting. Attached Figure Description

[0013] The subject matter considered to be this utility model is pointed out and explicitly claimed at the end of the specification. The above and other objects, features, and advantages of this utility model will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a circuit block diagram of the LCDI power line circuit according to the present invention.

[0015] Figure 1A yes Figure 1 Detailed schematic diagram of the middle block diagram;

[0016] Figure 2 yes Figure 1 and Figure 1A Waveform diagram of the power supply line circuit under normal operating conditions;

[0017] Figure 3 yes Figure 1 and Figure 1A Waveform diagram of leakage current detection in the power supply line circuit;

[0018] Figure 4 yes Figure 1 and Figure 1A Waveform diagram of the shielded open circuit condition of the power supply line circuit;

[0019] Figure 5 yes Figure 1 and Figure 1A Waveform diagram of shielding degradation in the power line circuit. Detailed Implementation

[0020] The following simplified definitions of the terms should apply throughout the application:

[0021] The term "comprising" means including but not limited to, and should be interpreted in the manner in which it is usually used in the patent context;

[0022] The phrases “in one embodiment” and “according to one embodiment” generally mean that a particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention (these phrases do not necessarily refer to the same embodiment).

[0023] If a specification describes something as "exemplary" or "example," it should be understood as referring to a non-exclusive example; and

[0024] If the specification states that a component or feature "may," "can," "may," "should," "preferred," "possibly," "usually," "optionally," "for example," or "probably" (or other such language) be included or have a certain characteristic, then that particular component or feature is not required to be included or have that characteristic.

[0025] refer to Figure 1 The diagram shows a circuit block diagram of the LCDI power line circuit 10 (LCDI). The LCDI circuit 10 includes a phase line shield (LWS) 24A and a neutral line shield (NWS) 24B, a test switch 18, a power supply circuit 100, a power line fault circuit (PCFC) 110, a relay 16, and manual engagement linkage switches 12A and 12B, i.e., manual reset switches. The LCDI circuit 10 also includes resistor R4 and an LED for indicating normal operation. It also includes metal oxide rheostats MOV1 and MOV2 for circuit overload protection.

[0026] When manual reset switches 12A and 12B are set, the line voltage is connected to the load and then to the power supply circuit 100 via relay 16. Power supply circuit 100 provides bias voltage to the power line fault circuit 110 and shields 24A and 24B. Shields 24A and 24B are connected in series at the load end. As discussed and shown in more detail herein, the power line fault circuit 110 allows a small amount of relay current to flow through relay 16, but less than the excitation current required to actuate relay 16 to disconnect manual reset switches 12A and 12B. It should be understood that not starting from zero excitation current allows for faster actuation of solenoid 16 upon fault detection.

[0027] Also refer to Figure 1A , showed Figure 1The detailed circuit 10A of the intermediate circuit 10. The LCDI circuit 10A includes: a phase line shield (LWS) 24A, a neutral line shield (NWS) 24B, a shielded connector 24C, a test switch 18, a power supply circuit 100A, and a power line fault circuit 110A. The power line fault circuit 110A includes a transistor Q1, a capacitor C1, and a silicon controlled rectifier (SCR). It should be understood that the transistor Q1 can be any suitable nonlinear device with saturation mode, cutoff mode, and active mode. The SCR can be any suitable bistable latch-up device. The phase line shield (LWS) 24A and the neutral line shield (NWS) 24B can be any suitable conductive shield surrounding the phase line and neutral line, as discussed in more detail herein. When the manual reset switches 12A and 12B are set, the line voltage is connected to the load and then to the power supply circuit 100A via relay 16. Power supply circuit 100A provides bias voltage to power line fault circuit 110A and shielding components 24A and 24B. As discussed and shown in more detail herein, power line fault circuit 110A allows a small amount of relay current to flow through relay 16, but less than the excitation current required to actuate relay 16 to disconnect manual reset switches 12A and 12B. It should be understood that not starting from zero excitation current allows relay 16 to be actuated more quickly upon fault detection.

[0028] Now for reference Figure 1A and Figure 2 When switches 12A and 12B are mechanically (manually) engaged, the AC line voltage is connected to the load. The 60Hz AC line voltage is also connected to power supply circuit 100A via manual engagement relay 16. Power supply circuit 100A, including bridge rectifiers (diodes D1-D4), outputs a rectified non-smooth DC signal at the bridge output. This rectified non-smooth DC signal at the bridge output is routed to the base of Q1 via shields 24A and 24B and resistors R1 and R3. The rectified non-smooth DC signal at the bridge output is also routed to the collector of Q1 and the gate of SCR1 via resistors R2 and R2A.

[0029] Still referencing Figure 1A and Figure 2 The rectified non-smooth DC signal output from the bridge is routed to the base of NPN transistor Q1, R1, and R3. During the positive cycle of the rectified non-smooth DC signal, transistor Q1 is biased into a conducting state, and the rectified voltage is reduced through resistors R2 and R2A. When the voltage of Q1(B) drops below VB of Q1... BEAt saturation voltage, Q1 is turned off. Because the non-smooth DC signal at the bridge output drops to near 0 volts during this cycle, the voltages at the gates of Q1(C) and SCR1 are close to 0 volts. When the non-smooth DC signal at the bridge output changes to a positive value, Q1 is biased to conduct again, reducing the non-smooth DC signal at the bridge output through resistors R2 and R2A, thus keeping SCR1 off during normal operation.

[0030] Still referencing Figure 1A Under normal conditions, the rectified non-smooth DC signal at the bridge output is reduced through resistors R2 and R2A. The values ​​of resistors R2 and R2A allow a certain amount of AC current, less than the excitation current of relay 16, to flow through resistors R2 and R2A, through transistor Q1, and back to the neutral line when transistor Q1 is turned on. While transistor Q1 is in the off or non-conducting state, relay 16 inductively prevents current changes until transistor Q1 is turned on again, thereby maintaining or nearly maintaining the current flowing through relay 16. It is understood and recognized that this small relay current flowing through relay 16 is less than the excitation current required to actuate relay 16 to disconnect manual reset switches 12A and 12B. It should also be understood that not starting from zero excitation current allows relay 16 to be actuated more quickly upon fault detection.

[0031] Still referencing Figure 1A And also refer to Figure 4 When the integrity of shielding component 24A or 24B is compromised (e.g., open circuit), the bias on-state voltage V at the base of Q1 will... BE Insufficient to keep Q1 fully on. The voltage at the collector of Q1 (V(SCR gate)) rises during the first positive cycle of the rectified input to trigger SCR1 to turn on, sufficiently increasing the current flowing through relay 16 to energize relay 16, thereby disconnecting manual reset switches 12A and 12B. Thus, power from the AC line power supply to the load is interrupted. It is understood and recognized that during the positive or negative cycle of the AC input waveform (not shown), the full-wave bridge rectifier 100A enables the power line fault circuit 110A to detect and disconnect the AC line power supply from the load when a fault is detected.

[0032] Also refer to Figure 5 It showed Figure 1 , Figure 1A Waveform diagram of shielding degradation in the power line circuit. It should be understood that R1, shielding element 24A, shielding element 24B, connector 24C, and R3 form the base bias circuit for Q1. As the shielding resistance increases (e.g., due to galvanic corrosion caused by dissimilar metals in the power line shield), the V0 of Q1... BE It will begin to decline, falling below Q1's V. BE Saturation voltage, thereby reducing ICE With I CE As the charge on capacitor C1 decreases, capacitor C1 begins to charge. When the charge on capacitor C1 reaches the gate trigger voltage of SCR1, the SCR is triggered into the on state. This increases the current flowing through relay 16, thereby activating relay 16 and disconnecting manual reset switches 12A and 12B. Therefore, power from the AC line power supply to the load is interrupted.

[0033] It should be understood that this invention detects degraded shielding and open-circuit shielding. Furthermore, it should be understood that the above description is for illustrative purposes only. Therefore, those skilled in the art can devise various alternatives and modifications without departing from this invention. For example, the solid-state device SCR1 or Q1 can be any suitable solid-state device. For example, Q1 can be any suitable nonlinear device or transistor configuration, such as a common-base configuration. This invention is intended to cover all such alternatives, variations, and modifications falling within the scope of the appended claims.

Claims

1. An LCDI circuit for interrupting alternating current from an AC power source, the AC power source being connected to a load via an insulated neutral wire and an insulated phase wire, the LCDI circuit comprising: An insulated neutral wire surrounded by a neutral wire shield; An insulated phase wire surrounded by a phase wire shield, wherein the phase wire shield can be connected to the neutral wire shield; A power line fault circuit for monitoring the integrity of the neutral and phase shields and leakage current, wherein the power line fault circuit includes: Nonlinear devices that can be connected to the centerline shield; A bistable latching device for interrupting AC power from an AC power source; and A power supply circuit used to provide the first rectified voltage waveform to the power line fault circuit and the phase line shield.

2. The LCDI circuit as described in claim 1, wherein, The nonlinear device includes: An NPN transistor with emitter, base, and collector is configured as a common-emitter amplifier; At least one first base bias resistor that can be connected to the neutral shield and the base; At least one second base bias resistor that can be connected to the phase line shield and the power supply circuit; and At least one collector bias resistor that can be connected to the collector and power supply circuit.

3. The LCDI circuit as described in claim 2, further comprising: The collector of the NPN transistor is connected to a bistable latch-up device having an on / off state, selectively turning on the NPN transistor and turning off the bistable latch-up device based on a first sufficient portion of a first rectified signal applied to the base of the NPN transistor.

4. The LCDI circuit as described in claim 3, further comprising: Based on a first insufficient portion of the first rectified signal applied to the base of the NPN transistor, the NPN transistor is selectively turned off and the bistable latch-up device is turned on, wherein the bistable latch-up device is selectively turned on during a first time period.

5. The LCDI circuit as described in claim 4, further comprising: A first capacitor connected to the collector of the NPN transistor and at least one collector bias resistor, wherein the NPN transistor, the first capacitor, at least one collector bias resistor, at least one base bias resistor, and a degraded neutral shield or a degraded phase shield determine the first time period.

6. The LCDI circuit as described in claim 5, further comprising: Based on a second insufficient portion of the first rectified signal applied to the base of the NPN transistor, the NPN transistor is selectively turned off and the bistable latch-up device is turned on, wherein the bistable latch-up device is selectively turned on during a second time period, and the first capacitor and at least one collector bias resistor determine the second time period, and the second time period is shorter than the first time period.

7. The LCDI circuit as described in claim 6, further comprising: Based on the negative voltage applied to the base of the NPN transistor, the NPN transistor is selectively turned off and the bistable latch-up device is turned on.

8. A power line shielding monitoring circuit for interrupting AC power from an AC power source, the AC power source being connected to a load via an insulated neutral wire surrounded by a neutral wire shield and an insulated phase wire surrounded by a phase wire shield, wherein, The neutral wire shield and the phase wire shield are connected via a shielding connector, and the power line shielding monitoring circuit includes: A nonlinear device capable of being connected to the neutral shield, wherein the nonlinear device includes: Saturation mode; Cutoff mode; Activation mode; and A bistable latching device connected to the nonlinear device interrupts the AC power from the AC power source based on the mode interruption of the nonlinear device.

9. The power line shielding monitoring circuit as described in claim 8, wherein, The nonlinear device includes: An NPN transistor having an emitter, a base, and a collector; A base biasing circuit for biasing the base of the NPN transistor includes: At least one resistor; Centerline shielding; Phase wire shielding; Shielded connector; At least one collector bias resistor can be connected to the collector and the bistable latch-up device, wherein the NPN transistor, the base bias circuit, and the at least one collector bias resistor determine the mode of the NPN transistor; and At least one capacitor that can be connected to the at least one collector bias resistor and the bistable latch-up device.

10. The power line shielding monitoring circuit as described in claim 9, further comprising: When the NPN transistor is in saturation mode, the NPN transistor is selectively turned on and the bistable latch-up device is turned off.

11. The power line shielding monitoring circuit as described in claim 9, further comprising: When the NPN transistor is in cutoff mode, the NPN transistor is selectively turned off and the bistable latch-up device is turned on during a first time period, wherein the first time period is determined by at least one collector bias resistor and at least one capacitor.

12. The power line shielding monitoring circuit as described in claim 9, further comprising: When the NPN transistor is in active mode, the NPN transistor is selectively partially turned off and the bistable latch-up device is turned on during a second time period, wherein the second time period is determined by the NPN transistor, the base bias circuit, at least one collector bias resistor and at least one capacitor.

13. A power line shielding monitoring circuit for interrupting AC power from an AC power source, the AC power source being connected to a load via an insulated neutral wire surrounded by a neutral wire shield and an insulated phase wire surrounded by a phase wire shield, wherein, The neutral wire shield and the phase wire shield are connected via a shielding connector, and the power line shielding monitoring circuit includes: A nonlinear device capable of being connected to the neutral shield, wherein the nonlinear device includes: Saturation mode; Cutoff mode; Activation mode; The nonlinear device includes: An NPN transistor having an emitter, a base, and a collector; A base biasing circuit for biasing the base of the NPN transistor, the base biasing circuit comprising: At least one base bias resistor; The centerline shielding component; The phase wire shielding component; The shielding connector; At least one collector bias resistor that can be connected to the collector and the bistable latch-up device, wherein the NPN transistor, the base bias circuit and the at least one collector bias resistor determine the mode of the NPN transistor. A mechanically locked double-pole switch positioned between the AC power source and the load; A relay used to unlock the mechanically locked double-pole switch; A bistable latching device connected to the nonlinear device and the relay, which interrupts the AC power from the AC power source based on the mode of the nonlinear device; At least one capacitor that can be connected to the nonlinear device and the bistable latch-up device; and A power supply circuit for biasing the nonlinear device and the bistable latch-up device.

14. The power line shielding monitoring circuit as described in claim 13, wherein, The power supply circuit includes a full-wave bridge rectifier.

15. The power line shielding monitoring circuit as described in claim 13, further comprising: When the NPN transistor is in saturation mode, the NPN transistor is selectively turned on and the bistable latch-up device is turned off.

16. The power line shielding monitoring circuit as described in claim 13, further comprising: When the NPN transistor is in cutoff mode, the NPN transistor is selectively turned off and the bistable latch-up device is turned on during a first time period, wherein the at least one collector bias resistor and at least one capacitor determine the first time period.

17. The power line shielding monitoring circuit as described in claim 13, further comprising: When the NPN transistor is in active mode, the NPN transistor is selectively partially turned off and the bistable latch-up device is turned on during a second time period, wherein the NPN transistor, the base bias circuit, at least one collector bias resistor, and at least one capacitor determine the second time period.

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