Server AI computing power optimization device and electronic equipment

Abstract

The utility model relates to the technical field of artificial intelligence computing power, in particular to a server AI computing power optimization device and electronic equipment. The device is applied to a 4U case and comprises a mainboard, a SWITCH board and a double-golden-finger AI card, the mainboard comprises two CPUs (Central Processing Unit); the SWITCH board comprises two SWITCH chip sets and ten PCIE (Peripheral Component Interconnect Express) slot sets, each SWITCH chip set comprises two SWITCH chips, and each PCIE slot set comprises two PCIE slots; each CPU is divided into four paths to be connected to one SWITCH chip set, every two paths are connected with one SWITCH chip, and each SWITCH chip is divided into multiple paths to be connected with the multiple PCIE slot sets and used for outputting PCIE uplink resources to the PCIE slots through the CPUs; the double-golden-finger AI card comprises two AI chips and two golden fingers, and one AI chip is connected with the two PCIE slots through the two golden fingers. On the premise that the size of the case is not increased, the number of the AI cards is increased, and therefore the beneficial effect of improving the overall computing power of the server is achieved.

Description

Technical Field

[0001] This application relates to the technical field of artificial intelligence computing power, and in particular to a server AI computing power optimization device and electronic device. Background Technology

[0002] In recent years, the rapid development of artificial intelligence technology has led to a continuous increase in the demand for AI computing power, which has driven the continuous upgrading of AI server hardware platforms. Currently, the mainstream server platforms on the market are mainly CPU+AI servers, and their computing power depends primarily on the chassis size and the number of AI cards. 2U (4 AI cards) and 4U (10 AI cards) chassis are commonly used; the larger the chassis, the more AI cards can be installed, thereby increasing the server's computing power.

[0003] However, existing 4U servers only support 10 double-width AI cards. Limited by chassis size, it's difficult to significantly increase the number of AI cards, thus restricting the server's computing power upgrade potential. Despite continuous improvements in AI card performance, the number of AI cards cannot be effectively increased within the same chassis space, creating a bottleneck for computing power enhancement.

[0004] Therefore, how to effectively increase the number of AI cards and improve the overall computing power of the server without increasing the size of the chassis has become a technical problem that urgently needs to be solved. Utility Model Content

[0005] To overcome the shortcomings of existing technologies, this application provides a server AI computing power optimization device and electronic device, which effectively increases the number of AI cards without increasing the size of the chassis, thereby achieving the beneficial effect of improving the overall computing power of the server.

[0006] The technical solution adopted by this application to solve its technical problem is:

[0007] In the first aspect, this application provides a server AI computing power optimization device, applied to a 4U chassis, including: a motherboard, a switch board, and dual gold finger AI cards;

[0008] The motherboard includes two CPUs; the switch board includes two switch chipsets and ten PCIe slot groups, each switch chipset includes two switch chips, and each PCIe slot group includes two PCIe slots.

[0009] Each CPU is connected to a SWITCH chipset in four ways, and two ways are connected to a SWITCH chip. Each SWITCH chip is connected to multiple PCIe slot groups in multiple ways, for outputting PCIe uplink resources to the PCIe slots through the CPU.

[0010] A dual-gold-finger AI card includes two AI chips and two gold fingers, with one AI chip connected to two PCIe slots via the two gold fingers.

[0011] Optionally, each CPU is connected to a switch chipset via four paths, with each pair of paths connecting to a switch chip, including:

[0012] Each CPU includes four CPU ports. One CPU port is connected to one SWITCH chip through a set of MCIO connectors to form a connection branch. One SWITCH chip connects two of the connection branches.

[0013] Optionally, the two SWITCH chipsets include a first SWITCH chip and a second SWITCH chip;

[0014] The ten PCIe slot groups include the first slot group to the fifth slot group;

[0015] Each of the aforementioned switch chips is connected to multiple PCIe slot groups via multiple paths, including:

[0016] The first end of the first SWITCH chip is connected to the first slot of the first slot group, the second end of the first SWITCH chip is connected to the second slot of the first slot group, the third end of the first SWITCH chip is connected to the first slot of the second slot group, and the fourth end of the first SWITCH chip is connected to the second slot of the second slot group.

[0017] The first end of the second SWITCH chip is connected to the first slot of the third slot group, the second end of the second SWITCH chip is connected to the second slot of the third slot group, the third end of the second SWITCH chip is connected to the first slot of the fourth slot group, the fourth end of the second SWITCH chip is connected to the second slot of the fourth slot group, the fifth end of the second SWITCH chip is connected to the first slot of the fifth slot group, and the sixth end of the second SWITCH chip is connected to the second slot of the fifth slot group.

[0018] Optionally, the two SWITCH chipsets may further include a third SWITCH chip and a fourth SWITCH chip;

[0019] The ten PCIe slot groups also include the sixth to tenth slot groups;

[0020] Each of the aforementioned switch chips is connected to multiple PCIe slot groups via multiple paths, and further includes:

[0021] The first end of the third switch chip is connected to the first slot of the sixth slot group, the second end of the third switch chip is connected to the second slot of the sixth slot group, the third end of the third switch chip is connected to the first slot of the seventh slot group, and the fourth end of the third switch chip is connected to the second slot of the seventh slot group.

[0022] The first end of the fourth switch chip is connected to the first slot of the eighth slot group, the second end of the fourth switch chip is connected to the second slot of the eighth slot group, the third end of the fourth switch chip is connected to the first slot of the ninth slot group, the fourth end of the fourth switch chip is connected to the second slot of the ninth slot group, the fifth end of the fourth switch chip is connected to the first slot of the tenth slot group, and the sixth end of the fourth switch chip is connected to the second slot of the tenth slot group.

[0023] Optionally, the switch board includes ten PCIe slot groups, each PCIe slot group including two PCIe slots, including:

[0024] In each PCIe slot group, the two corresponding PCIe slots are arranged vertically to form a PCIe slot group.

[0025] Optionally, each of the gold fingers is configured with 16 PCIe lanes to support x16 PCIe signal transmission.

[0026] Optionally, the length of the dual-finger AI card is no more than 400mm.

[0027] Secondly, this application provides an electronic device equipped with the aforementioned server AI computing power optimization device.

[0028] The beneficial effects of this application are as follows: This application provides a server AI computing power optimization device suitable for a 4U chassis. Through ingenious design, it effectively improves the AI ​​computing power of the server without increasing the chassis size. The device mainly consists of a motherboard, a switch board, and a dual-finger AI card. The motherboard is equipped with two CPUs, each CPU connected to a switch chipset, and each switch chipset consists of two switch chips. Each switch chip is responsible for allocating the PCIe uplink resources output by the CPU to multiple PCIe slot groups, and each PCIe slot group contains two PCIe slots. The dual-finger AI card consists of two AI chips and two gold fingers. Each AI chip, through its connection to two PCIe slots, achieves double the AI ​​computing power. This achieves the goal of increasing the number of AI cards within the same chassis space, breaking through the bottleneck of traditional server computing power upgrades and significantly improving the overall AI computing power of the server. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the server AI computing power optimization device provided in the embodiments of this application;

[0030] Figure 2 This is a schematic diagram of the structure of the dual-gold finger AI card in the server AI computing power optimization device provided in this application embodiment. Detailed Implementation

[0031] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0032] The following will clearly and completely describe the concept, specific structure, and resulting technical effects of this application in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this application can be combined interactively without contradicting each other.

[0033] Reference Figure 1 , Figure 1 This is a schematic diagram of the server AI computing power optimization device provided in this application embodiment, applied to a 4U chassis, including: a motherboard, a switch board, and dual gold finger AI cards.

[0034] Among them, the 4U chassis is a standardized server chassis specification. 4U refers to the height unit of the chassis. 1U is approximately equal to 44.45mm. The external dimensions are 770mm×433mm×177mm (length×width×height). Based on the length of the chassis (770mm), considering factors such as internal space layout, heat dissipation requirements and stability, the maximum supported length of the AI ​​card is limited to 400mm. This provides physical size support for placing two AI chips on one AI card.

[0035] Furthermore, the motherboard includes two CPUs; the switch board includes two switch chipsets and ten PCIe slot groups, each switch chipset includes two switch chips, and each PCIe slot group includes two PCIe slots.

[0036] Specifically, the motherboard contains two CPUs, indicating that the server employs a multi-processor configuration to enhance computing power and the ability to handle complex tasks. The CPUs are connected to the PCIe slots using the aforementioned connection method. The CPUs on the motherboard then output computing resources to the switch board via the PCIe interface for further resource allocation and management.

[0037] Specifically, the SWITCH board refers to a network switching card or PCIe switching card, responsible for high-speed data transmission between various components within the server and between the server and the external network. In this application, the SWITCH board is equipped with 20 standard PCIe slots, such as... Figure 1 As shown, the PCIe slots are arranged in pairs vertically to form PCIe slot groups. This vertical arrangement optimizes heat dissipation efficiency, expandability, and ease of maintenance, thereby improving the overall performance and stability of the chassis.

[0038] More specifically, the SWITCH chip is responsible for managing and expanding PCIe (Peripheral Component Interconnect Express) resources, enabling the system to support more peripheral connections and data transfers. This application includes four SWITCH chips; for ease of explanation, every two SWITCH chips are grouped together. These groups connect the PCIe slots to the CPU, facilitating the motherboard's output of PCIe uplink resources to the SWITCH board.

[0039] Furthermore, each CPU is connected to a SWITCH chipset in four ways, and two ways are connected to a SWITCH chip. Each SWITCH chip is connected to multiple PCIe slot groups in multiple ways, for outputting PCIe uplink resources to the PCIe slots through the CPU.

[0040] Specifically, each CPU has four independent data channels, each capable of transmitting data independently, such as... Figure 1 As shown, the CPU connects to a switch chip for every two data channels, and the two data channels are combined into one switch chip for processing, thereby improving the efficiency and flexibility of data processing.

[0041] That is, each CPU is connected to a switch chipset via four paths, with each pair of paths connecting to a switch chip, including:

[0042] Each CPU includes four CPU ports. One CPU port is connected to one SWITCH chip through a set of MCIO connectors to form a connection branch. One SWITCH chip connects two of the connection branches.

[0043] Specifically, a set of MCIO connectors includes two MCIO connectors. In the set of MCIO connectors, one MCIO connector is set on the motherboard and the other MCIO connector is set on the switch board. The connection between the two boards is established through the MCIO connectors set on the two boards respectively.

[0044] More specifically, each SWITCH chip is connected to multiple PCIe slot groups via multiple paths, indicating that one SWITCH chip can manage and control multiple PCIe slots to achieve data distribution and routing.

[0045] In the embodiments provided in this application, the SWITCH chipset includes four SWITCH chips, namely a first SWITCH chip, a second SWITCH chip, a third SWITCH chip, and a fourth SWITCH chip, and ten PCIe slot groups, namely the first slot group to the tenth slot group, specifically:

[0046] Each of the aforementioned switch chips is connected to multiple PCIe slot groups via multiple paths, including:

[0047] The first end of the first SWITCH chip is connected to the first slot of the first slot group, the second end of the first SWITCH chip is connected to the second slot of the first slot group, the third end of the first SWITCH chip is connected to the first slot of the second slot group, and the fourth end of the first SWITCH chip is connected to the second slot of the second slot group.

[0048] The first end of the second SWITCH chip is connected to the first slot of the third slot group, the second end of the second SWITCH chip is connected to the second slot of the third slot group, the third end of the second SWITCH chip is connected to the first slot of the fourth slot group, the fourth end of the second SWITCH chip is connected to the second slot of the fourth slot group, the fifth end of the second SWITCH chip is connected to the first slot of the fifth slot group, and the sixth end of the second SWITCH chip is connected to the second slot of the fifth slot group.

[0049] The first end of the third switch chip is connected to the first slot of the sixth slot group, the second end of the third switch chip is connected to the second slot of the sixth slot group, the third end of the third switch chip is connected to the first slot of the seventh slot group, and the fourth end of the third switch chip is connected to the second slot of the seventh slot group.

[0050] The first end of the fourth switch chip is connected to the first slot of the eighth slot group, the second end of the fourth switch chip is connected to the second slot of the eighth slot group, the third end of the fourth switch chip is connected to the first slot of the ninth slot group, the fourth end of the fourth switch chip is connected to the second slot of the ninth slot group, the fifth end of the fourth switch chip is connected to the first slot of the tenth slot group, and the sixth end of the fourth switch chip is connected to the second slot of the tenth slot group.

[0051] Combination Figure 1 It can be seen that a CPU (e.g.) Figure 1 The CPU0 shown is divided into four paths, two of which are connected to a SWITCH chip (e.g., SWITCH0), and the other two are connected to another SWITCH chip (e.g., SWITCH1).

[0052] One of the switch chips (e.g., SWITCH0) is divided into four paths, each connecting to a PCIe slot in either the first or second slot group. Specifically, SWITCH0 connects to PCIe slots 01, 02, 03, and 04 respectively. The other switch chip (e.g., SWITCH1), connecting to three slot groups, is divided into six paths, each connecting to a PCIe slot in one of those three slot groups. Figure 1 The SWITCH2 shown can be referred to as SWITCH0 above, and the SWITCH3 can be referred to as SWITCH1 above.

[0053] Among them, SWITCH0 is the first SWITCH chip, SWITCH1 is the second SWITCH chip, SWITCH2 is the third SWITCH chip, and SWITCH3 is the fourth SWITCH chip.

[0054] Furthermore, referring to Figure 2 , Figure 2 This is a schematic diagram of the structure of a dual-gold finger AI card in the server AI computing power optimization device provided in this application embodiment. Specifically, one of the dual-gold finger AI cards includes two AI chips and two gold fingers, and one of the AI ​​chips is connected to two PCIe slots through the two gold fingers.

[0055] Specifically, the gold fingers consist of numerous golden conductive contacts, named for their gold-plated surface and finger-like arrangement. They are used to insert into the aforementioned PCIe slot, thereby connecting the AI ​​card to the switch board. Currently, the gold fingers only support x16 PCIe signals, meaning they can only connect and support one AI chip. This application adds an extra gold finger—physically lengthening it—to support x32 PCIe signals, thus enabling support for two AI chips. Based on this, an AI card is designed, resulting in a dual-gold-finger AI card containing two AI chips.

[0056] More specifically, the design of the two gold fingers of the dual-gold-finger AI card should correspond to the design of the aforementioned PCIe slot, i.e., adopt a side-by-side design to facilitate the insertion of new AI cards onto the switch board. Due to the limitations of the aforementioned 4U chassis dimensions, the length of the dual-gold-finger AI card should not exceed 400mm.

[0057] In summary, this application improves AI performance by adding gold fingers and AI chips to the AI ​​card and designing a corresponding PCIe slot on the switch board, thereby doubling the AI ​​computing power through positive electrode combination. This achieves the goal of increasing the number of AI cards within the same chassis space, breaking through the bottleneck of traditional server computing power upgrades and significantly improving the overall AI computing power of the server.

[0058] Secondly, this application provides an electronic device equipped with the aforementioned server AI computing power optimization device and electronic device.

[0059] The above is a detailed description of the preferred embodiments of this application. However, the invention of this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A server AI computing power optimization device, characterized in that, Applied to 4U chassis, including: motherboard, switch board and dual gold finger AI card; The motherboard includes two CPUs; the switch board includes two switch chipsets and ten PCIe slot groups, each switch chipset includes two switch chips, and each PCIe slot group includes two PCIe slots. Each CPU is connected to a SWITCH chipset in four ways, and two ways are connected to a SWITCH chip. Each SWITCH chip is connected to multiple PCIe slot groups in multiple ways, for outputting PCIe uplink resources to the PCIe slots through the CPU. A dual-gold-finger AI card includes two AI chips and two gold fingers, with one AI chip connected to two PCIe slots via the two gold fingers.

2. The server AI computing power optimization device according to claim 1, characterized in that, Each CPU is connected to a switch chipset via four paths, with each pair of paths connecting to a switch chip, including: Each CPU includes four CPU ports. One CPU port is connected to one SWITCH chip through a set of MCIO connectors to form a connection branch. One SWITCH chip connects two of the connection branches.

3. The server AI computing power optimization device according to claim 1, characterized in that, The two SWITCH chipsets include a first SWITCH chip and a second SWITCH chip; The ten PCIe slot groups include the first slot group to the fifth slot group; Each of the aforementioned switch chips is connected to multiple PCIe slot groups via multiple paths, including: The first end of the first SWITCH chip is connected to the first slot of the first slot group, the second end of the first SWITCH chip is connected to the second slot of the first slot group, the third end of the first SWITCH chip is connected to the first slot of the second slot group, and the fourth end of the first SWITCH chip is connected to the second slot of the second slot group. The first end of the second SWITCH chip is connected to the first slot of the third slot group, the second end of the second SWITCH chip is connected to the second slot of the third slot group, the third end of the second SWITCH chip is connected to the first slot of the fourth slot group, the fourth end of the second SWITCH chip is connected to the second slot of the fourth slot group, the fifth end of the second SWITCH chip is connected to the first slot of the fifth slot group, and the sixth end of the second SWITCH chip is connected to the second slot of the fifth slot group.

4. The server AI computing power optimization device according to claim 3, characterized in that, The two SWITCH chipsets also include a third SWITCH chip and a fourth SWITCH chip; The ten PCIe slot groups also include the sixth to tenth slot groups; Each of the aforementioned switch chips is connected to multiple PCIe slot groups via multiple paths, and further includes: The first end of the third switch chip is connected to the first slot of the sixth slot group, the second end of the third switch chip is connected to the second slot of the sixth slot group, the third end of the third switch chip is connected to the first slot of the seventh slot group, and the fourth end of the third switch chip is connected to the second slot of the seventh slot group. The first end of the fourth switch chip is connected to the first slot of the eighth slot group, the second end of the fourth switch chip is connected to the second slot of the eighth slot group, the third end of the fourth switch chip is connected to the first slot of the ninth slot group, the fourth end of the fourth switch chip is connected to the second slot of the ninth slot group, the fifth end of the fourth switch chip is connected to the first slot of the tenth slot group, and the sixth end of the fourth switch chip is connected to the second slot of the tenth slot group.

5. The server AI computing power optimization device according to claim 1, characterized in that, The switch board includes ten PCIe slot groups, each PCIe slot group including two PCIe slots, including: In each PCIe slot group, the two corresponding PCIe slots are arranged vertically to form a PCIe slot group.

6. The server AI computing power optimization device according to claim 1, characterized in that, Each of the gold fingers is configured with 16 PCIe lanes to support x16 PCIe signal transmission.

7. The server AI computing power optimization device according to claim 1, characterized in that, The length of the dual-gold-finger AI card is no more than 400mm.

8. An electronic device, characterized in that, It is equipped with a server AI computing power optimization device as described in any one of claims 1-7.

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