Encryption chip power-on reset circuit of energy-saving intelligent door lock

Abstract

The utility model relates to an encryption chip power-on reset circuit of an energy-saving intelligent door lock. The encryption chip power-on reset circuit comprises a first switching circuit and a second switching circuit, the power receiving ends of the first switching circuit and the second switching circuit are used for connecting the positive electrode of the battery pack; the first switching circuit is used for driving the on-off of the second switching circuit, the second switching circuit is used for providing a power-on reset voltage for an encryption chip when the second switching circuit is switched on or not providing the power-on reset voltage for the encryption chip when the second switching circuit is switched off, and the input end of the first switching circuit is used for being connected with an SCL clock line to receive a low level or clock square wave signal; the problem that the encryption chip of the intelligent door lock consumes power during standby is solved, normal work of the encryption chip is ensured, and the problem that the encryption chip is possibly locked in the using process, communication is abnormal, and consequently functions are poor is solved.

Description

Technical Field

[0001] This utility model relates to the field of smart door lock technology, and in particular to a power-on reset circuit for an encryption chip of an energy-saving smart door lock. Background Technology

[0002] A door lock is a device that serves as an insurance and security device.

[0003] With the development of automation and intelligent technologies, and under the wave of smart homes, the intelligentization of door locks is also a development trend, leading to the emergence of smart door locks.

[0004] Because features such as facial recognition, peephole, and Wi-Fi connectivity are integrated into smart locks, the power consumption of smart locks is higher than that of traditional fingerprint locks, making them unsuitable for use with dry cell batteries.

[0005] Currently, most smart door locks use rechargeable lithium batteries for power. However, the lithium batteries in existing smart door locks continuously power the encryption chip, causing the encryption chip to consume power even in standby mode. Furthermore, the encryption chip is prone to locking during use (the program enters an infinite loop), leading to communication abnormalities and malfunctions.

[0006] Therefore, in this utility model patent application, the applicant has carefully researched a power-on reset circuit for the encryption chip of an energy-saving smart door lock to solve the above problems. Utility Model Content

[0007] This utility model addresses the shortcomings of the existing technology by providing a power-on reset circuit for the encryption chip of an energy-saving smart door lock. This circuit solves the problem of power consumption of the encryption chip in standby mode, ensures the normal operation of the encryption chip, and resolves the issue of communication abnormalities leading to malfunction during use.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A power-on reset circuit for an encryption chip in an energy-saving smart door lock is based on a host connected to the encryption chip via an SCL clock line, and includes a first switch circuit and a second switch circuit.

[0010] The power receiving terminals of the first and second switching circuits are used to connect to the positive terminal of the battery pack.

[0011] The first switching circuit is used to drive the second switching circuit to switch on and off. The second switching circuit is used to provide a power-on reset voltage to the encryption chip when it is on or not to provide a power-on reset voltage to the encryption chip when it is off. The input terminal of the first switching circuit is used to connect to the SCL clock line to receive a low-level or clock square wave signal.

[0012] When the host does not access the encryption chip, the SCL clock line is at a low level, that is, the input of the first switching circuit is at a low level. The first switching circuit is cut off, which in turn cuts off the second switching circuit. Consequently, the second switching circuit does not provide the encryption chip with a power-on reset voltage.

[0013] When the host accesses the encryption chip, there is a clock square wave signal on the SCL clock line, that is, the input terminal of the first switching circuit is a clock square wave signal. The first switching circuit is turned on, thereby turning on the second switching circuit, which in turn provides the encryption chip with a power-on reset voltage.

[0014] As a preferred embodiment, the first switching circuit includes a MOSFET Q5, the drain of which is connected to the positive terminal of the battery pack, the drain of which is also connected to the second switching circuit, the source of which is grounded, and the gate of which is connected to the SCL clock line to receive a low-level or clock square wave signal.

[0015] As a preferred embodiment, the first switching circuit further includes resistors R25 and R26. The gate of MOSFET Q5 is connected to one end of resistor R25, the other end of resistor R25 is used to connect to the SCL clock line, and resistor R26 is connected between the gate and source of MOSFET Q5.

[0016] As a preferred embodiment, the second switching circuit includes a MOSFET Q6, a chip U3, a resistor R23, and a resistor R24;

[0017] The gate of MOSFET Q6 is connected to both the drain of MOSFET Q5 and one end of resistor R23. The other end of resistor R23 is used to connect to the positive terminal of the battery pack. The source of MOSFET Q6 and the input terminal of chip U3 are both connected to the other end of resistor R23. The drain of MOSFET Q6 is grounded through resistor R24. The enable terminal of chip U3 is connected to the drain of MOSFET Q6. The output terminal of chip U3 is used to connect to the power receiving terminal of the encryption chip to output the corresponding power supply voltage to the encryption chip. The ground terminal of chip U3 is grounded.

[0018] As a preferred embodiment, the second switching circuit further includes a capacitor C19, which is connected in parallel across the resistor R24.

[0019] As a preferred embodiment, the second switching circuit further includes a capacitor C17, and the output terminal of the chip U3 is grounded through the capacitor C17.

[0020] Compared with the prior art, this utility model has obvious advantages and beneficial effects. Specifically, it mainly achieves this by cooperating with the first and second switching circuits. In standby mode, the second switching circuit does not supply power to the encryption chip. Only when the host needs to access it will the second switching circuit supply power to the encryption chip to enable it to work normally. Then the host can access the encryption chip normally, which solves the problem of power consumption of the encryption chip in standby mode. Moreover, each time the encryption chip is powered on, it is equivalent to a reset, ensuring that the encryption chip works normally and solving the problem that the encryption chip may lock up and cause communication abnormalities and malfunctions during use.

[0021] To more clearly illustrate the structural features and effects of the present invention, a detailed description is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0022] Figure 1 This is a general control principle block diagram of an embodiment of the present utility model;

[0023] Figure 2 This is a partial circuit schematic diagram of an embodiment of the present invention (mainly showing the first switch circuit, the second switch circuit, the encryption chip, and the interface J2);

[0024] Figure 3 This is another partial circuit schematic diagram of an embodiment of the present invention (mainly showing the equalization charging circuit and the battery pack).

[0025] Explanation of icon numbers:

[0026] 11. Charging Management Circuit

[0027] 12. Lithium battery protection circuit

[0028] 13. Charging indicator circuit

[0029] 21. First switching circuit

[0030] 22. Second switching circuit

[0031] 30. Host

[0032] 40. Encryption chip. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] like Figures 1 to 3 As shown, a power-on reset circuit for the encryption chip of an energy-saving smart door lock is based on the host connecting to the encryption chip via an SCL clock line. The power-on reset circuit for the encryption chip of an energy-saving smart door lock includes a first switching circuit 21 and a second switching circuit 22.

[0035] The receiving terminals of the first switching circuit 21 and the second switching circuit 22 are used to connect to the positive terminal of the battery pack (i.e. Figure 2 and Figure 3 (Mid-B+ end);

[0036] The first switching circuit 21 is used to drive the second switching circuit 22 to switch on and off. The second switching circuit 22 is used to provide a power-on reset voltage to the encryption chip 40 when it is on or not to provide a power-on reset voltage to the encryption chip 40 when it is off. The input terminal of the first switching circuit 21 is used to connect to the SCL clock line to receive a low level or clock square wave signal.

[0037] When the host 30 does not access the encryption chip 40, the input of the first switch circuit 21 is at a low level, the first switch circuit 21 is cut off, thereby cutting off the second switch circuit 22 and the second switch circuit 22 does not provide the encryption chip 40 with the power-on reset voltage.

[0038] When the host 30 accesses the encryption chip 40, the input terminal of the first switching circuit 21 is a clock square wave signal, the first switching circuit 21 is turned on, thereby turning on the second switching circuit 22, which in turn provides the encryption chip 40 with a power-on reset voltage.

[0039] In this embodiment, the first switching circuit 21 includes a MOSFET Q5, a resistor R25, and a resistor R26.

[0040] The drain of MOSFET Q5 is used to connect to the positive terminal of the battery pack. The drain of MOSFET Q5 is also connected to the second switching circuit 22. The source of MOSFET Q5 is grounded. The gate of MOSFET Q5 is connected to one end of resistor R25. The other end of resistor R25 is connected to the SCL clock line to receive low level or clock square wave signals. Resistor R26 is connected between the gate and source of MOSFET Q5.

[0041] In this embodiment, the second switching circuit 22 includes a MOSFET Q6, a chip U3, a resistor R23, a capacitor C19, a capacitor C17, and a resistor R24.

[0042] The gate of MOSFET Q6 is connected to both the drain of MOSFET Q5 and one end of resistor R23. The other end of resistor R23 is used to connect to the positive terminal of the battery pack. The source of MOSFET Q6 and the input terminal (VIN pin) of chip U3 are connected to the other end of resistor R23. The drain of MOSFET Q6 is grounded through resistor R24. The capacitor C19 is connected in parallel across resistor R24.

[0043] The enable terminal of chip U3 is connected to the drain of MOSFET Q6. The output terminal (OUT pin) of chip U3 is used to connect to the power receiving terminal (VIN pin) of encryption chip 40 to output the corresponding power supply voltage to encryption chip 40. The ground terminal (VSS pin) of chip U3 is grounded. The output terminal of chip U3 is also grounded through capacitor C17.

[0044] In this embodiment, the battery pack includes two batteries connected in series. A balancing charging circuit is provided for the battery pack to charge the battery pack. The balancing charging circuit includes a charging interface J1, a charging indicator circuit 13, a lithium battery protection circuit 12 for connecting to the battery pack, and a charging management circuit 11 for boost charging, balancing current and connecting to the battery pack. The charging interface J1 is connected to the charging management circuit 11 through the charging indicator circuit 13.

[0045] The charging interface J1 is a Type-C terminal, which serves as the charging input interface. Pins A5 and B5 are used to configure the Type-C adapter to provide 5V 3A of power.

[0046] For the specific circuit structure and circuit principle of charging interface J1, charging indicator circuit 13, lithium battery protection circuit 12 and charging management circuit 11, please refer to the intelligent door lock equalization charging circuit with authorization announcement number CN220306969 U published on January 5, 2024. They will not be described in detail here.

[0047] In this embodiment, an interface J2 for discharging and communicating with the host 30 is also included. The interface J2 is communicatively connected to the host 30. The host 30 accesses the encryption chip 40 through pin 3 and the SCL clock line of the interface J2. At the same time, the host 30 is connected to the gate of the MOS transistor Q5 through pin 3, the SCL clock line, and resistor R25 of the interface J2.

[0048] like Figure 2 As shown, the working principle will be explained in general as follows:

[0049] The host 30 can only access the encryption chip 40 normally after the encryption chip 40 is powered on.

[0050] In standby mode, when the host 30 does not access the encryption chip 40, the SCL clock line is at a low level, MOSFETs Q5 and Q6 are both cut off, the enable terminal (EN pin) of chip U3 is at a low level, and the output terminal of chip U3 has no output, so there is no power supply to the encryption chip 40, thereby achieving energy saving.

[0051] When host 30 needs to access encryption chip 40, a clock square wave signal is present on the SCL clock line. Both MOSFETs Q5 and Q6 are turned on. The square wave output by MOSFET Q6 generates a clock square wave signal across resistor R24 ​​and capacitor C19. This clock square wave signal is received by the EN pin of chip U3, turning it on. Chip U3 then outputs 3.3V to the encryption chip 40, allowing host 30 to access the encryption chip 40 normally. The second switching circuit 22 only supplies power to the encryption chip 40 when host 30 accesses it, effectively resetting the encryption chip 40 once during host 30 access. This ensures that the encryption chip 40 (in this embodiment, when...) is powered on and reset. Figure 2 In the middle, the encryption chip 40 (chips U4 and U5) are working normally.

[0052] The key design feature of this invention lies in the cooperation of the first and second switching circuits. In standby mode, the second switching circuit does not supply power to the encryption chip. Only when the host needs to access it will the second switching circuit supply power to the encryption chip to enable it to work normally. This solves the problem of power consumption of the encryption chip in standby mode. Moreover, each time the encryption chip is powered on, it is equivalent to a reset, ensuring that the encryption chip works normally and solving the problem that the encryption chip may lock up and cause communication abnormalities and malfunctions during use.

[0053] The above description is merely a preferred embodiment of the present utility model and does not constitute any limitation on the technical scope of the present utility model. Therefore, any minor modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model shall still fall within the scope of the technical solution of the present utility model.

Claims

1. A power-on reset circuit for an encryption chip in an energy-saving smart door lock, characterized in that: The host is connected to the encryption chip via an SCL clock line. It includes a first switching circuit and a second switching circuit; The power receiving terminals of the first and second switching circuits are used to connect to the positive terminal of the battery pack. The first switching circuit is used to drive the second switching circuit to switch on and off. The second switching circuit is used to provide a power-on reset voltage to the encryption chip when it is on or not to provide a power-on reset voltage to the encryption chip when it is off. The input terminal of the first switching circuit is used to connect to the SCL clock line to receive a low-level or clock square wave signal. When the host does not access the encryption chip, the SCL clock line is at a low level, that is, the input of the first switching circuit is at a low level. The first switching circuit is cut off, which in turn cuts off the second switching circuit. Consequently, the second switching circuit does not provide the encryption chip with a power-on reset voltage. When the host accesses the encryption chip, there is a clock square wave signal on the SCL clock line, that is, the input terminal of the first switching circuit is a clock square wave signal. The first switching circuit is turned on, thereby turning on the second switching circuit, which in turn provides the encryption chip with a power-on reset voltage.

2. The power-on reset circuit for the encryption chip of the energy-saving smart door lock according to claim 1, characterized in that: The first switching circuit includes a MOSFET Q5. The drain of the MOSFET Q5 is used to connect to the positive terminal of the battery pack. The drain of the MOSFET Q5 is also connected to the second switching circuit. The source of the MOSFET Q5 is grounded. The gate of the MOSFET Q5 is used to connect to the SCL clock line to receive a low-level or clock square wave signal.

3. The power-on reset circuit for the encryption chip of the energy-saving smart door lock according to claim 2, characterized in that: The first switching circuit also includes resistors R25 and R26. The gate of MOSFET Q5 is connected to one end of resistor R25, and the other end of resistor R25 is used to connect to the SCL clock line. Resistor R26 is connected between the gate and source of MOSFET Q5.

4. The power-on reset circuit for the encryption chip of the energy-saving smart door lock according to claim 2, characterized in that: The second switching circuit includes a MOSFET Q6, a chip U3, a resistor R23, and a resistor R24; The gate of MOSFET Q6 is connected to both the drain of MOSFET Q5 and one end of resistor R23. The other end of resistor R23 is used to connect to the positive terminal of the battery pack. The source of MOSFET Q6 and the input terminal of chip U3 are both connected to the other end of resistor R23. The drain of MOSFET Q6 is grounded through resistor R24. The enable terminal of chip U3 is connected to the drain of MOSFET Q6. The output terminal of chip U3 is used to connect to the power receiving terminal of the encryption chip to output the corresponding power supply voltage to the encryption chip. The ground terminal of chip U3 is grounded.

5. The power-on reset circuit for the encryption chip of the energy-saving smart door lock according to claim 4, characterized in that: The second switching circuit also includes a capacitor C19, which is connected in parallel across the resistor R24.

6. The power-on reset circuit for the encryption chip of the energy-saving smart door lock according to claim 4, characterized in that: The second switching circuit also includes a capacitor C17, and the output terminal of the chip U3 is grounded through the capacitor C17.

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