Phase-locked loop circuit and image sensor
By introducing a detection and control circuit and a switching mechanism into the phase-locked loop (PLL) circuit, the problems of high power consumption and runaway caused by signal interference in traditional PLL circuits are solved, and a stable and low-power PLL circuit design is achieved.
Patent Information
- Application Number
- CN202520169717.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2035-01-23
AI Technical Summary
Traditional phase-locked loop (PLL) circuits suffer from high power consumption and loss of control under signal interference, resulting in unstable operation of the PLL.
A phase-locked loop circuit was designed, including a frequency and phase detector, a charge pump circuit, a switching circuit, an inductor-capacitor voltage-controlled oscillator, an automatic frequency control circuit, and a detection and control circuit. The frequency is adjusted by controlling the capacitance in calibration mode, and the automatic frequency control circuit is turned off after calibration to reduce power consumption and eliminate the influence of external signal disturbances.
It effectively reduces additional circuit power consumption and maintains the stability of the phase-locked loop circuit when subjected to external signal disturbances, quickly responding to signal changes and eliminating the effects of disturbances.
Smart Images
Figure CN223942694U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of image sensor technology, and particularly relates to a phase-locked loop circuit and an image sensor. Background Technology
[0002] Phase-locked loop (PLL) circuits are found in a variety of high-frequency applications, from simple clock cleanup circuits to local oscillators (LOs) used in high-performance radio communication links, as well as ultrafast switching frequency synthesizers in vector network analyzers (VNAs), image sensors, and more.
[0003] Phase-locked loop (PLL) circuits typically consist of a feedback loop comprised of a phase and frequency detector, a charge pump circuit, and a voltage-controlled oscillator (VCO). Compared to ring oscillators, inductor-capacitor VCOs offer better phase noise performance and are commonly used in jitter-sensitive circuits. Since the oscillation frequency range adjustable solely by the loop control voltage is relatively small, an automatic frequency control circuit is usually added to the PLL circuit to expand the oscillation frequency range and improve the frequency adjustment range.
[0004] The phase-locked loop (PLL) circuit with added automatic frequency control mainly includes a calibration phase and a fine-tuning phase after calibration. During calibration, the automatic frequency control circuit compares the frequency of the PLL output signal with the frequency of the clock reference signal and outputs a digital code signal, thereby changing the capacitance in the inductor-capacitor voltage-controlled oscillator (VCO) to make the output signal frequency close to the clock reference signal frequency. After calibration, the frequency and phase detector and charge pump circuit output an adjustment voltage and change the capacitance in the VCO, ultimately making the output signal frequency equal to the clock reference signal frequency.
[0005] Since the automatic frequency control circuit is still in normal working condition after calibration, the phase-locked loop circuit generates additional power consumption. Also, when the frequency of the output signal remains unchanged in the application scenario, external signal disturbances may cause changes in the digital code signal output by the automatic frequency control circuit, resulting in the phase-locked loop circuit being out of control and potentially causing subsequent circuits to malfunction. Utility Model Content
[0006] The purpose of this invention is to provide a phase-locked loop circuit that solves the problems of high power consumption and loss of control under signal interference in traditional phase-locked loop circuits with automatic frequency control.
[0007] A first aspect of this utility model provides a phase-locked loop circuit, comprising:
[0008] A frequency and phase detector is configured to detect the frequencies of a clock reference signal and the output signal of the phase-locked loop circuit, and generate a control signal.
[0009] A charge pump circuit, connected to the frequency and phase detector, is configured to receive the control signal and charge / discharge it, and output a first voltage signal that changes in relation to the control signal.
[0010] The switching circuit is connected to the charge pump circuit and the reference voltage terminal respectively, and is configured to switch the output of the voltage reference signal of the reference voltage terminal by a first switching signal, and to switch the output of the first voltage signal by a second switching signal.
[0011] An inductor-capacitor voltage-controlled oscillator is connected to the switching circuit. The inductor-capacitor voltage-controlled oscillator is configured to adjust the size of its internal capacitor according to the corresponding signal among the received voltage reference signal, the first voltage signal, and the digital code signal, so as to adjust the frequency and phase of the output signal of the phase-locked loop circuit.
[0012] The automatic frequency control circuit, connected to both the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured as follows:
[0013] In calibration mode, the first switching signal is output, and the frequencies of the clock reference signal and the output signal of the phase-locked loop circuit are detected, and the corresponding digital code signal is generated. After calibration, the second switching signal is switched to be output.
[0014] A detection control circuit, connected to the control terminal of the automatic frequency control circuit, is used to output a shutdown signal to control the automatic frequency control circuit to shut down when the second switching signal is detected.
[0015] Optionally, the phase-locked loop circuit further includes:
[0016] A latching circuit is connected between the automatic frequency control circuit and the inductor-capacitor voltage-controlled oscillator. The latching circuit is used to latch the digital code signal and output it to the inductor-capacitor voltage-controlled oscillator.
[0017] Optionally, the detection control circuit includes a first logic gate;
[0018] The first input terminal of the first logic gate is connected to the first output terminal of the automatic frequency control circuit, the second input terminal of the first logic gate is used to input an enable signal, and the output terminal of the first logic gate is connected to the control terminal of the automatic frequency control circuit.
[0019] Optionally, the latch circuit includes a second logic gate and a latch;
[0020] The first input terminal of the second logic gate is connected to the first output terminal of the automatic frequency control circuit. The second input terminal of the second logic gate is used to input the enable signal. The output terminal of the second logic gate is connected to the reset terminal of the latch. The set terminal of the latch is connected to the second output terminal of the automatic frequency control circuit. The output terminal of the latch is connected to the second input terminal of the inductor-capacitor voltage-controlled oscillator.
[0021] Optionally, the switching circuit includes a first switch and a second switch;
[0022] The first terminal of the first switch is connected to the reference voltage terminal, the second terminal of the first switch and the second terminal of the second switch are connected to the first input terminal of the inductor-capacitor voltage-controlled oscillator, the first terminal of the second switch is connected to the output terminal of the charge pump circuit, and the control terminal of the first switch and the control terminal of the second switch are connected to the first output terminal of the automatic frequency control circuit.
[0023] Optionally, the inductor-capacitor voltage-controlled oscillator includes an inductor, an adjustable capacitor unit, a capacitor array, a first switch, a second switch, and a third switch;
[0024] The inductor, the adjustable capacitor unit, and the capacitor array are connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator. The first terminal of the first switch, the control terminal of the second switch, and the first output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The first terminal of the second switch, the control terminal of the first switch, and the second output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The second terminal of the first switch, the second terminal of the second switch, and the first terminal of the third switch are connected. The second terminal of the third switch is grounded. The control terminal of the third switch is used to receive a reference voltage. The control terminal of the adjustable capacitor unit constitutes the first input terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the capacitor array constitutes the second input terminal of the inductor-capacitor voltage-controlled oscillator.
[0025] The adjustable capacitor unit is configured to switch the output capacitance of different sizes according to the voltage reference signal or the first voltage signal;
[0026] The capacitor array includes multiple capacitor units with preset capacitance values. The capacitor array is configured to switch different numbers of capacitor units connected between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator according to the digital code signal.
[0027] Optionally, the adjustable capacitor unit includes a first capacitor, a first adjustable capacitor, a second adjustable capacitor, and a second capacitor connected in series between the first output terminal and the second output terminal of the inductor-capacitor voltage-controlled oscillator.
[0028] The control terminals of the first and second adjustable capacitors are used to receive the voltage reference signal or the first voltage signal.
[0029] Optionally, the capacitor array includes multiple capacitor units connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator;
[0030] Each of the capacitor units includes a third capacitor, a fourth capacitor, a fourth switch, a fifth switch, and a sixth switch;
[0031] The first terminal of the third capacitor is connected to the first output terminal of the inductor-capacitor voltage-controlled oscillator. The second terminal of the third capacitor, the first terminal of the fourth switch, and the fifth switch are connected. The second terminal of the fourth switch, the first terminal of the fourth capacitor, and the first terminal of the sixth switch are connected. The second terminal of the fourth capacitor is connected to the second output terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the fourth switch is used to receive one bit of the digital code signal. The second terminals of the fifth and sixth switches are grounded. The control terminals of the fifth and sixth switches are connected and receive a digital signal with an opposite level to the control terminal of the fourth switch.
[0032] Optionally, the automatic frequency control circuit includes:
[0033] The first counter is used to periodically count the number of pulses of the clock reference signal within a preset time period and output a first count value;
[0034] The second counter is used to periodically count the number of pulses of the output signal of the phase-locked loop circuit within a preset time period and output a second count value.
[0035] A difference circuit is used to compare the first count value and the second count value, and output a difference signal;
[0036] A bit adjustment circuit, connected to the difference circuit, the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured to output a first switching signal in calibration mode, output a changing digital code signal when the difference signal is greater than a preset difference, and latch and output the digital code signal of the previous moment and the second switching signal when the difference signal is less than the preset difference.
[0037] A power switch is connected to the positive power supply terminal and the power supply terminals of the first counter, the second counter, the difference circuit, and the bit adjustment circuit, respectively. The power switch is configured to be triggered to turn off according to the shutdown signal, so as to control the automatic frequency control circuit to shut down.
[0038] A second aspect of this invention provides an image sensor, including a phase-locked loop circuit as described above.
[0039] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The above-mentioned phase-locked loop circuit includes a frequency and phase detector, a charge pump circuit, a switching circuit, an inductor-capacitor voltage-controlled oscillator, an automatic frequency control circuit, and a detection and control circuit. In calibration mode, the automatic frequency control circuit controls the switching circuit to output a voltage reference signal and an output digital code signal, thereby changing the capacitance value in the inductor-capacitor voltage-controlled oscillator and thus changing the frequency of the output signal of the phase-locked loop circuit. After calibration, the frequency and phase detector and the charge pump circuit output a changed first voltage signal, which changes the capacitance value of the inductor-capacitor voltage-controlled oscillator and the frequency of the output signal of the phase-locked loop circuit. After calibration mode is completed, the detection and control circuit outputs a shutdown signal to shut down the automatic frequency control circuit, reducing additional circuit power consumption. Furthermore, when there is external signal disturbance, since the automatic frequency control circuit is already shut down, the digital code signal input to the inductor-capacitor voltage-controlled oscillator will not change, eliminating the influence of disturbance. Attached Figure Description
[0040] Figure 1 A schematic diagram of the first structure of the phase-locked loop circuit provided in this embodiment of the present invention;
[0041] Figure 2 This is a schematic diagram of a second structure of a phase-locked loop circuit provided in an embodiment of the present invention;
[0042] Figure 3 A schematic diagram of a third structure of a phase-locked loop circuit provided in an embodiment of this utility model;
[0043] Figure 4 This is a schematic diagram of the fourth structure of the phase-locked loop circuit provided in the embodiment of this utility model;
[0044] Figure 5 A first circuit diagram of an inductor-capacitor voltage-controlled oscillator provided for an embodiment of this utility model;
[0045] Figure 6 A second circuit diagram of an inductor-capacitor voltage-controlled oscillator provided in an embodiment of this utility model;
[0046] Figure 7 A circuit diagram of a capacitor array provided in an embodiment of this utility model;
[0047] Figure 8 A schematic diagram of the automatic frequency control circuit provided in an embodiment of this utility model. Detailed Implementation
[0048] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.
[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0050] The first aspect of this utility model embodiment provides a phase-locked loop circuit, such as... Figure 1 As shown, in this embodiment, the phase-locked loop circuit includes:
[0051] The frequency and phase detector 10 is configured to detect the frequencies of the clock reference signal clk_ref and the output signal clk_o of the phase-locked loop circuit, and generate control signals.
[0052] The charge pump circuit 20, connected to the frequency and phase detector 10, is configured to receive control signals and charge and discharge, and output a first voltage signal Vout that changes in relation to the control signals.
[0053] The switching circuit 30, connected to the charge pump circuit 20 and the reference voltage terminal, is configured to switch the voltage reference signal vref_afc of the output reference voltage terminal by a first switching signal, and to switch the output first voltage signal Vout by a second switching signal.
[0054] The inductor-capacitor voltage-controlled oscillator 40 is connected to the switching circuit 30. The inductor-capacitor voltage-controlled oscillator 40 is configured to adjust the size of the internal capacitor according to the corresponding signals in the received voltage reference signal vref_afc, the first voltage signal Vout, and the digital code signal C_ctl, so as to adjust the frequency and phase of the output signal clk_o of the phase-locked loop circuit.
[0055] Automatic frequency control circuit 50, connected to switching circuit 30 and inductor-capacitor voltage-controlled oscillator 40 respectively, is configured as follows:
[0056] In calibration mode, the first switching signal is output, and the frequencies of the clock reference signal clk_ref and the output signal clk_o of the phase-locked loop circuit are detected, and a digital code signal C_ctl of the corresponding size is generated. After calibration, the second switching signal is output.
[0057] The detection control circuit 60 is connected to the control terminal of the automatic frequency control circuit 50, and is used to output a shutdown signal afc_pd to control the automatic frequency control circuit 50 to shut down when the second switching signal is detected.
[0058] In this embodiment, the first input terminal of the inductor-capacitor voltage-controlled oscillator 40 is connected to the output terminal of the switching circuit 30, the second input terminal of the inductor-capacitor voltage-controlled oscillator 40 is connected to the second output terminal of the automatic frequency control circuit 50, and the control terminal of the switching circuit 30 is connected to the first output terminal of the automatic frequency control circuit 50.
[0059] The switching circuit 30 can select the output voltage reference signal vref_afc or the first voltage signal Vout output by the charge pump circuit 20 under the control of the switching signal loop_ctl. The switching signal loop_ctl may include a first switching signal and a second switching signal, and the first switching signal and the second switching signal may be opposite level signals.
[0060] The frequency of the signal from the inductor-capacitor voltage-controlled oscillator 40 is: Where f is the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40, i.e., the frequency of the output signal clk_o of the phase-locked loop circuit; L is the inductance value inside the inductor-capacitor voltage-controlled oscillator 40, which can be selected as a fixed value or a variable. In this embodiment, the inductance value is a fixed value; C is the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40, which is a variable and is related to the magnitude of the second voltage signal Vctrl input to the first input terminal and the digital code signal C_ctl input to the first input terminal. When the second voltage signal Vctrl changes, the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40 changes positively or negatively, and correspondingly, the frequency of the output signal clk_o changes negatively with the capacitance. When the digital code signal C_ctl changes, the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40 changes positively or negatively, and correspondingly, the frequency of the output signal clk_o changes negatively with the capacitance. Therefore, the frequency of the phase-locked loop circuit can be changed by adjusting the capacitance value.
[0061] The phase-locked loop circuit operates in calibration mode and a fine-tuning mode following calibration mode. In calibration mode, the automatic frequency control circuit 50 first outputs a first switching signal. The first switching signal controls the switching circuit 30 to switch between the reference voltage terminal and the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The second voltage signal Vctrl input to the inductor-capacitor voltage-controlled oscillator 40 is the voltage reference signal vref_afc. The voltage reference signal vref_afc first adjusts the internal capacitance of the inductor-capacitor voltage-controlled oscillator 40 to the reference capacitance value corresponding to the voltage reference signal vref_afc, and adjusts the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the reference frequency. Then, the adjusted reference frequency is compared with the clock reference signal clk_ref. By comparing the two frequencies, the magnitude of the output digital code signal C_ctl is changed.
[0062] The changing digital code signal C_ctl is output to the inductor-capacitor voltage-controlled oscillator 40, and the capacitance of the inductor-capacitor voltage-controlled oscillator 40 is further changed, thereby changing the frequency of the output signal clk_o. Through the first loop composed of the automatic frequency control circuit 50 and the inductor-capacitor voltage-controlled oscillator 40, the frequency of the output signal clk_o gradually approaches the frequency of the clock reference signal clk_ref. When the frequency of the output signal clk_o is found to be close to the frequency of the clock reference signal clk_ref and differs by a preset difference, the automatic frequency control circuit 50 locks the currently output digital code signal C_ctl and switches to output a second switching signal. At this time, the calibration ends.
[0063] When the switching circuit 30 receives the second switching signal, it switches the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. At the same time, the detection and control circuit 60 detects the second switching signal, that is, it detects that the level of the first output terminal of the automatic frequency control circuit 50 has changed. The detection and control circuit 60 outputs a shutdown signal afc_pd to the automatic frequency control circuit 50, and the automatic frequency control circuit 50 shuts down and stops working.
[0064] In the fine-tuning mode after the calibration mode, the frequency and phase detector 10 further compares the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref, and outputs a changing control signal to the charge pump circuit 20. The charge pump circuit 20 charges or discharges, thereby outputting a changing first voltage signal Vout.
[0065] The frequency and phase detector 10 compares the rising edge of the output signal clk_o with the rising edge of the clock reference signal clk_ref, and obtains the first control signal and the second control signal based on the comparison of their frequency and phase difference. Specifically, in the phase-locked loop circuit, if the clock reference signal clk_ref has a rising edge but the output signal clk_o does not, the first control signal is high and the second control signal is low. If both the clock reference signal clk_ref and the output signal clk_o have a rising edge, the frequency and phase detector 10 simultaneously outputs the first and second control signals at low levels. If the clock reference signal clk_ref does not have a rising edge but the output signal clk_o has a rising edge, the first control signal is low and the second control signal is high.
[0066] The charge pump circuit 20 charges and discharges according to the high and low levels of the first control signal and the second control signal. When the first control signal is high and the second control signal is low, the charge pump circuit 20 charges, and the output first voltage signal Vout increases. When the first control signal is low and the second control signal is high, the charge pump circuit 20 discharges, and the output first voltage signal Vout decreases. When the first control signal and the second control signal are both high or low, the charge pump circuit 20 charges and discharges simultaneously, or is simultaneously cut off from charging and discharging. At this time, the charge pump circuit 20 outputs a constant first voltage signal Vout, which can be zero voltage or a preset voltage.
[0067] When the frequency of the output signal clk_o does not reach the frequency of the clock reference signal clk_ref, the first voltage signal Vout changes. Correspondingly, the capacitance of the inductor-capacitor voltage-controlled oscillator 40 changes, and the frequency of the output signal clk_o changes and gradually approaches the frequency of the clock reference signal clk_ref until the frequencies of the two are the same. At this time, the first control signal and the second control signal are at the same level, the frequency and phase detector 10 is reset, and the frequency discrimination and phase-locked loop operation is completed. At this time, the capacitance value of the inductor-capacitor voltage-controlled oscillator 40 is stable at the preset capacitance value.
[0068] After the calibration mode is completed, the detection control circuit 60 outputs a shutdown signal afc_pd to shut down the automatic frequency control circuit 50, reducing additional circuit power consumption. Furthermore, when there is an external signal disturbance, since the automatic frequency control circuit 50 is already shut down, the digital code signal C_ctl input to the inductor-capacitor voltage-controlled oscillator 40 will not change. The phase-locked loop circuit can quickly respond to signal disturbances and eliminate their effects through the frequency and phase detector 10 and the charge pump circuit 20.
[0069] Among them, the frequency and phase detector 10 can be composed of D flip-flops, logic gates and other structures, and the charge pump circuit 20 can be composed of current sources, controllable switches and energy storage elements.
[0070] The switching circuit 30 can be a corresponding switching switch, multi-channel selector, etc.; the inductor-capacitor voltage-controlled oscillator 40 can be an inductor, capacitor and corresponding oscillation circuit; the automatic frequency control circuit 50 can be a corresponding comparison circuit, logic circuit, etc.; and the detection control circuit 60 can be a corresponding level detection circuit, logic circuit, etc.
[0071] Furthermore, in order to maintain the output of the lock digital code signal C_ctl, in an optional embodiment, such as Figure 2 As shown, the phase-locked loop circuit also includes:
[0072] The latch circuit 70 is connected between the automatic frequency control circuit 50 and the inductor-capacitor voltage-controlled oscillator 40. The latch circuit 70 is used to latch the digital code signal C_ctl and output it to the inductor-capacitor voltage-controlled oscillator 40.
[0073] In this embodiment, in calibration mode, the automatic frequency control circuit 50 outputs a first switching signal to control the switching circuit 30 to connect the reference voltage terminal and the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The second voltage signal Vctrl input to the inductor-capacitor voltage-controlled oscillator 40 is a voltage reference signal vref_afc. The voltage reference signal vref_afc first adjusts the capacitor inside the inductor-capacitor voltage-controlled oscillator 40 to the reference capacitance value corresponding to the voltage reference signal vref_afc, and adjusts the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the reference frequency. Then, the adjusted reference frequency is compared with the clock reference signal clk_ref. By comparing the frequency magnitudes of the two, the magnitude of the output digital code signal C_ctl is changed.
[0074] The changing digital code signal C_ctl is output to the latch circuit 70. The latch circuit 70 transmits the digital code signal C_ctl to the inductor-capacitor voltage-controlled oscillator 40 and further changes the capacitance of the inductor-capacitor voltage-controlled oscillator 40, thereby changing the frequency of the output signal clk_o. Through the first loop composed of the automatic frequency control circuit 50 and the inductor-capacitor voltage-controlled oscillator 40, the frequency of the output signal clk_o gradually approaches the frequency of the clock reference signal clk_ref. When the frequency of the output signal clk_o is found to be close to the frequency of the clock reference signal clk_ref and differs by a preset difference, the automatic frequency control circuit 50 locks the currently output digital code signal C_ctl and switches to output a second switching signal. At this time, the calibration ends.
[0075] After calibration, when the switching circuit 30 receives the second switching signal, it switches the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. At the same time, the detection control circuit 60 detects the second switching signal, that is, it detects that the level of the first output terminal of the automatic frequency control circuit 50 has changed. The detection control signal outputs a shutdown signal afc_pd to the automatic frequency control circuit 50, and the automatic frequency control circuit 50 shuts down and stops working.
[0076] At the same time, the latch circuit 70 does not receive the changed digital code signal C_ctl. The latch circuit 70 latches the digital code signal C_ctl input at the previous moment, that is, it maintains the digital code signal C_ctl before the output automatic frequency control circuit 50 is turned off to the inductor-capacitor voltage-controlled oscillator 40. The capacitance of the capacitor unit 421 controlled by the digital code signal C_ctl remains unchanged.
[0077] In the fine-tuning mode following the calibration mode, the frequency and phase detector 10 further compares the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref, and outputs a changing control signal to the charge pump circuit 20. The charge pump circuit 20 charges or discharges, thereby outputting a changing first voltage signal Vout. The first voltage signal Vout changes the capacitance value of another capacitor unit 421 in the inductor-capacitor voltage-controlled oscillator 40, thereby changing the total capacitance value of the inductor-capacitor voltage-controlled oscillator 40 and the frequency of the output signal clk_o of the phase-locked loop circuit, until it reaches the frequency of the clock reference signal clk_ref.
[0078] After the calibration mode ends, the detection control circuit 60 outputs a shutdown signal afc_pd to shut down the automatic frequency control circuit 50, reducing additional circuit power consumption. Furthermore, when there is an external signal disturbance, since the automatic frequency control circuit 50 is already off and the latch circuit 70 latches the digital code signal C_ctl, the digital code signal C_ctl input to the inductor-capacitor voltage-controlled oscillator 40 will not change. The phase-locked loop circuit can quickly respond to signal disturbances and eliminate the effects of disturbances through the frequency and phase detector 10 and the charge pump circuit 20.
[0079] In another alternative embodiment, such as Figure 3 As shown, in order to increase the frequency of the loop output signal clk_o, the phase-locked loop circuit also includes:
[0080] Frequency divider 80 has its input terminal connected to the output terminal of inductor-capacitor voltage-controlled oscillator 40, and its output terminal connected to the input terminal of frequency and phase detector 10 and the input terminal of automatic frequency control circuit 50, respectively. Frequency divider 80 is configured to divide the output signal clk_o of inductor-capacitor voltage-controlled oscillator 40 and output the divided feedback signal clk_fb to frequency and phase detector 10 and automatic frequency control circuit 50.
[0081] In this embodiment, the automatic frequency control circuit 50 compares the frequency of the feedback signal clk_fb with the frequency of the clock reference signal clk_ref in calibration mode, and the frequency and phase detector 10 compares the frequency of the feedback signal clk_fb with the frequency of the clock reference signal clk_ref in fine-tuning mode. When the phase-locked loop circuit is locked, the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 is equal to the frequency of the clock reference signal clk_ref after being divided by the frequency divider 80. Therefore, the phase-locked loop circuit achieves the function of multiplying the frequency by N times. The final frequency of the phase-locked loop circuit is determined by the division ratio of the frequency divider 80.
[0082] The latch circuit 70 can adopt a corresponding latch, memory, or other structure. In an optional embodiment, such as... Figure 4 As shown, in an optional embodiment, the detection control circuit 60 includes a first logic gate U1;
[0083] The first input terminal of the first logic gate U1 is connected to the first output terminal of the automatic frequency control circuit 50, the second input terminal of the first logic gate U1 is used to input the enable signal EN, and the output terminal of the first logic gate U1 is connected to the control terminal of the automatic frequency control circuit 50.
[0084] The latch circuit 70 includes a second logic gate U2 and a latch 71;
[0085] The first input terminal of the second logic gate U2 is connected to the first output terminal of the automatic frequency control circuit 50. The second input terminal of the second logic gate U2 is used to input the enable signal EN. The output terminal of the second logic gate U2 is connected to the reset terminal of the latch 71. The set terminal of the latch 71 is connected to the second output terminal of the automatic frequency control circuit 50. The output terminal of the latch 71 is connected to the second input terminal of the inductor-capacitor voltage-controlled oscillator 40.
[0086] The switching circuit 30 includes a first switch S1 and a second switch S2;
[0087] The first terminal of the first switch S1 is connected to the reference voltage terminal. The second terminals of the first switch S1 and the second terminals of the second switch S2 are connected to the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The first terminal of the second switch S2 is connected to the output terminal of the charge pump circuit 20. The control terminals of the first switch S1 and the second switch S2 are connected to the first output terminal of the automatic frequency control circuit 50.
[0088] In this embodiment, in calibration mode, the automatic frequency control circuit 50 outputs a first switching signal, turns on the first switch S1, turns off the second switch S2, and connects the reference voltage terminal and the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The voltage reference signal vref_afc adjusts the capacitance inside the inductor-capacitor voltage-controlled oscillator 40 to the reference capacitance value corresponding to the voltage reference signal vref_afc, and adjusts the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the reference frequency. At the same time, the first logic gate U1 performs logical operations on the enable signal EN and the first switching signal, and maintains the output on signal to the automatic frequency control circuit 50. The automatic frequency control circuit 50 compares the adjusted reference frequency with the clock reference signal clk_ref, and changes the magnitude of the output digital code signal C_ctl by comparing the two frequencies.
[0089] The second logic gate U2 performs logical operations on the enable signal EN and the first switching signal, and outputs an enable signal to control the latch 71 to switch to the jog state. The latch 71 transmits the input digital code signal C_ctl to the inductor-capacitor voltage-controlled oscillator 40, and further changes the capacitance of the inductor-capacitor voltage-controlled oscillator 40, thereby changing the frequency of the output signal clk_o. When the frequency of the output signal clk_o is found to be close to the frequency of the clock reference signal clk_ref and differs by a preset difference, the automatic frequency control circuit 50 locks the currently output digital code signal C_ctl and switches to output the second switching signal. At this time, the calibration ends.
[0090] After calibration, when the switching circuit 30 receives the second switching signal, it switches the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. At the same time, the first logic gate U1 switches the output of the shutdown signal afc_pd to the automatic frequency control circuit 50, and the automatic frequency control circuit 50 shuts down and stops working.
[0091] At the same time, the second logic gate U2 switches the output shutdown signal afc_pd to latch 71. Latch 71 latches the digital code signal C_ctl input at the previous moment, that is, it maintains the digital code signal C_ctl before the output automatic frequency control circuit 50 is turned off to the inductor-capacitor voltage-controlled oscillator 40. The capacitance of the capacitor unit 421 controlled by the digital code signal C_ctl remains unchanged.
[0092] After the calibration mode ends, the first logic gate U1 outputs the shutdown signal afc_pd to shut down the automatic frequency control circuit 50, reducing additional circuit power consumption. Furthermore, when there is an external signal disturbance, since the automatic frequency control circuit 50 is already off and the latch 71 latches the digital code signal C_ctl, the digital code signal C_ctl input to the inductor-capacitor voltage-controlled oscillator 40 will not change. The phase-locked loop circuit can quickly respond to signal disturbances and eliminate the effects of disturbances through the frequency and phase detector 10 and the charge pump circuit 20.
[0093] The first logic gate U1 and the second logic gate U2 can be corresponding AND gates, OR gates, etc. In an optional embodiment, the first logic gate U1 and the second logic gate U2 are AND gates, the enable signal EN is high level, the first switching signal is high level, in the calibration mode, the first logic gate U1 outputs a high level enable signal to the automatic frequency control circuit 50, the second logic gate U2 outputs a high level enable signal to the latch 71, and after the calibration is completed, the first logic gate U1 outputs a low level disable signal afc_pd to the automatic frequency control circuit 50, and the second logic gate U2 outputs a low level disable signal afc_pd to the latch 71.
[0094] Furthermore, when different frequencies need to be output, i.e. when the frequency of the clock reference signal clk_ref changes, the level of the enable signal EN can be changed to enable the first logic gate U1 and the second logic gate U2 to output an on signal. At this time, the automatic frequency control circuit 50 can again detect and compare the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref. When the difference between the two frequencies is greater than the preset difference, the magnitude of the output digital code signal C_ctl is switched, and the latch circuit 70 can continue to transmit the digital code signal C_ctl output by the automatic frequency control circuit 50 to the inductor-capacitor voltage-controlled oscillator 40, thereby enabling the automatic frequency control circuit 50 to work in calibration mode.
[0095] The digital code signal C_ctl is a multi-bit binary digital signal, such as a four-bit binary digital signal, like 1000, 1100, 1110, 1101, etc. When the difference between the frequency of the output signal clk_o and the frequency of the clock reference signal clk_ref is greater than a preset difference, the digital code signal C_ctl can change the value of the corresponding bit of the digital code signal C_ctl in a preset order, for example, changing sequentially according to 1000, 1001, 1010...1101, 1110.
[0096] The first switch S1 and the second switch S2 can be switching devices of opposite switch types. In an optional embodiment, the first switch S1 is an N-channel transistor and the second switch S2 is a P-channel transistor. When a high-level first switching signal is output, the first switch S1 is turned on and the second switch S2 is turned off. When a low-level second switching signal is output, the first switch S1 is turned off and the second switch S2 is turned on.
[0097] In an optional embodiment, the capacitor control logic corresponding to the digital code signal C_ctl and the second voltage signal Vctrl is as follows: Figure 5 As shown, the inductor-capacitor voltage-controlled oscillator 40 includes an inductor L1, an adjustable capacitor unit 41, a capacitor array 42, a first switch M1, a second switch M2, and a third switch M3.
[0098] Inductor L1, adjustable capacitor unit 41, and capacitor array 42 are connected in parallel between the first output terminal out_p and the second output terminal out_n of inductor-capacitor voltage-controlled oscillator 40. The first terminal of the first switch M1, the control terminal of the second switch M2, and the first output terminal out_p of the inductor-capacitor voltage-controlled oscillator 40 are connected. The first terminal of the second switch M2, the control terminal of the first switch M1, and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40 are connected. The second terminal of the first switch M1, the second terminal of the second switch M2, and the first terminal of the third switch M3 are connected. The second terminal of the third switch M3 is grounded. The control terminal of the third switch M3 is used to receive the reference voltage Vbias. The control terminal of the adjustable capacitor unit 41 constitutes the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The control terminal of the capacitor array 42 constitutes the second input terminal of the inductor-capacitor voltage-controlled oscillator 40.
[0099] The adjustable capacitor unit 41 is configured to switch the output capacitor of different sizes according to the voltage reference signal vref_afc or the first voltage signal Vout;
[0100] Capacitor array 42, such as Figure 6 As shown, a capacitor array 42 includes multiple capacitor units 421 with preset capacitance values, and is configured to switch different numbers of capacitor units 421 connected between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40 according to the digital code signal C_ctl.
[0101] In this embodiment, the adjustable capacitor unit 41 and the capacitor array 42 are connected in parallel to form an equivalent capacitor unit 421. The equivalent capacitor unit 421, the inductor, and multiple switching transistors form an LC oscillator, the oscillation frequency of which is determined by the inductance of the inductor L1 and the capacitance of the equivalent capacitor unit 421.
[0102] In calibration mode, the adjustable capacitor unit 41 receives the voltage reference signal vref_afc and adjusts it to the first capacitance value corresponding to the voltage reference signal vref_afc, thereby switching the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the first frequency.
[0103] The automatic frequency control circuit 50 compares the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref, and outputs a changing digital code signal C_ctl to the inductor-capacitor voltage-controlled oscillator 40. When the digital code signal C_ctl changes, different capacitor units 421 in the capacitor array 42 can be connected in series and parallel to the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40. For example, assuming there are four capacitor units 421 connected in parallel, each capacitor unit 421 has a preset capacitance value, and the capacitance values of each capacitor unit 421 can be equal or unequal. When the digital code signal C_ctl of 1000 is received, the first capacitor unit 421 turns on and connects to the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, while the second to fourth capacitor units 421 turn off. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor. Alternatively, when the digital code signal C_ctl of 1001 is received, the first capacitor unit 421 and the fourth capacitor unit 421 are turned on and connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, while the second capacitor unit 421 and the third capacitor unit 421 are turned off. At this time, the output capacitance value of the capacitor array 42 is the equivalent capacitance value of the parallel connection of the first preset capacitance value corresponding to the first capacitor unit 421 and the fourth preset capacitance value corresponding to the fourth capacitor unit 421. By changing the digital code signal C_ctl, the equivalent capacitance value of the capacitor array 42 can be changed, thereby changing the capacitance value of the equivalent capacitor unit 421 and the oscillation frequency of the inductor-capacitor voltage-controlled oscillator 40, that is, changing the frequency of the output signal clk_o of the phase-locked loop circuit until it approaches the frequency of the clock reference signal clk_ref.
[0104] Then, after the calibration mode ends, the capacitor array 42 maintains the current capacitance value, the adjustable capacitor unit 41 receives the first voltage signal Vout output by the charge pump circuit 20, and changes the internal capacitance to the second capacitance value according to the first voltage signal Vout. Under the loop control of the frequency and phase detector 10, the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40, the first voltage signal Vout gradually approaches the preset voltage, thereby adjusting the frequency of the output signal clk_o to be equal to the frequency of the clock reference signal clk_ref.
[0105] The adjustable capacitor unit 41 can be composed of multiple switching devices and multiple capacitor units 421, or it can be an adjustable capacitor. In an optional embodiment, such as... Figure 6 As shown, the adjustable capacitor unit 41 includes a first capacitor C1, a first adjustable capacitor CX1, a second adjustable capacitor CX2, and a second capacitor C2 connected in series between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40.
[0106] The control terminals of the first adjustable capacitor CX1 and the second adjustable capacitor CX2 are used to receive the voltage reference signal vref_afc or the first voltage signal Vout.
[0107] In this embodiment, the capacitance value of the adjustable capacitor unit 41 is equal to the series equivalent capacitance value of the first capacitor C1, the second capacitor C2, the first adjustable capacitor CX1, and the second adjustable capacitor CX2. When the first adjustable capacitor CX1 and the second adjustable capacitor CX2 receive voltage reference signals vref_afc or the first voltage signal Vout of different magnitudes, their capacitance values change accordingly, thereby changing the series equivalent capacitance value.
[0108] In practical circuit applications, adjustable capacitors can be classified into surface-mount adjustable capacitors and through-hole adjustable capacitors according to their packaging method, and into ceramic adjustable capacitors, PVC adjustable capacitors, and air adjustable capacitors according to their manufacturing materials.
[0109] The capacitor units 421 in the capacitor array 42 can be connected in series and parallel, and the capacitor units 421 can adopt corresponding selection switches and capacitors. In an optional embodiment, such as... Figure 7 As shown, the capacitor array 42 includes multiple capacitor units 421 connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40;
[0110] Each capacitor unit 421 includes a third capacitor C3, a fourth capacitor C4, a fourth switch M4, a fifth switch M5, and a sixth switch M6;
[0111] The first terminal of the third capacitor C3 is connected to the first output terminal of the inductor-capacitor voltage-controlled oscillator 40. The second terminal of the third capacitor C3, the first terminal of the fourth switch M4, and the fifth switch M5 are connected. The second terminal of the fourth switch M4, the first terminal of the fourth capacitor C4, and the first terminal of the sixth switch M6 are connected. The second terminal of the fourth capacitor C4 is connected to the second output terminal of the inductor-capacitor voltage-controlled oscillator 40. The control terminal of the fourth switch M4 is used to receive one bit of the digital code signal C_ctl. The second terminals of the fifth switch M5 and the sixth switch M6 are grounded. The control terminals of the fifth switch M5 and the sixth switch M6 are connected and receive a digital signal with an opposite level to the control terminal of the fourth switch M4.
[0112] In this embodiment, the maximum capacitance of each capacitor unit 421 is the total capacitance of the third capacitor C3 and the fourth capacitor C4. The capacitance of the third capacitor C3 in each capacitor unit 421 may be equal or unequal, and the capacitance of the fourth capacitor C4 in each capacitor unit 421 may be equal or unequal.
[0113] Assuming the array comprises four parallel capacitor units 421, when a digital code signal C_ctl of 1000 is received, the fourth switch M4 of the first capacitor unit 421 is turned on, and the fifth switch M5 and the sixth switch M6 of the first capacitor unit 421 are turned off. The third capacitor C3 and the fourth capacitor C4 of the first capacitor unit 421 are connected in series and then in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40. The fourth switch M4 of the second to fourth capacitor units 421 is turned off, and the fifth switch M5 and the sixth switch M6 of the second to fourth capacitor units 421 are turned on. The second to fourth capacitor units 421 have no equivalent capacitance output. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor unit 421.
[0114] Alternatively, when the digital code signal C_ctl of 1001 is received, the fourth switch M4 of the first capacitor unit 421 and the fourth capacitor unit 421 is turned on, the fifth switch M5 and the sixth switch M6 of the first capacitor unit 421 and the fourth capacitor unit 421 are turned off, the third capacitor C3 and the fourth capacitor C4 of the first capacitor unit 421 and the fourth capacitor unit 421 are connected in series and then connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, the fourth switch M4 of the second capacitor unit 421 and the third capacitor unit 421 is turned off, the fifth switch M5 and the sixth switch M6 of the second capacitor unit 421 and the third capacitor unit 421 are turned on, and the second capacitor unit 421 and the third capacitor unit 421 have no equivalent capacitance output. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor unit 421 and the fourth capacitor unit 421.
[0115] By changing the digital code signal C_ctl, the number of capacitor units 421 connected in parallel can be changed, thereby changing the equivalent capacitance of the capacitor array 42 and the oscillation frequency of the inductor-capacitor voltage-controlled oscillator 40, that is, changing the frequency of the output signal clk_o of the phase-locked loop circuit until it approaches the frequency of the clock reference signal clk_ref.
[0116] The automatic frequency control circuit 50 can employ corresponding digital circuits, logic circuits, etc., as shown in an optional embodiment, such as... Figure 8As shown, the automatic frequency control circuit 50 includes:
[0117] The first counter 51 is used to periodically count the number of pulses of the clock reference signal clk_ref within a preset time period and output the first count value;
[0118] The second counter 52 is used to periodically count the number of pulses of the output signal clk_o of the phase-locked loop circuit within a preset time, and output the second count value;
[0119] The difference circuit 53 is used to compare the first count value and the second count value and output the difference signal;
[0120] The bit adjustment circuit 54 is connected to the difference circuit 53, the switching circuit 30 and the inductor-capacitor voltage-controlled oscillator 40. It is configured to output a first switching signal in calibration mode, output a changing digital code signal C_ctl when the difference signal is greater than a preset difference, and latch the digital code signal C_ctl of the previous moment and output a second switching signal when the difference signal is less than a preset difference.
[0121] The power switch 55 is connected to the positive power supply terminal VDD and the power supply terminals of the first counter 51, the second counter 52, the difference circuit 53, and the bit adjustment circuit 54, respectively. The power switch 55 is configured to be triggered to turn off according to the shutdown signal afc_pd, so as to control the automatic frequency control circuit 50 to turn off.
[0122] In this embodiment, during the initial calibration state, the power switch 55 is initially in the ON state, i.e., it is triggered to conduct upon receiving a high-level signal, and transmits the operating power to each circuit module in the automatic frequency control circuit 50. The bit adjustment circuit 54 outputs a first switching signal to the switching circuit 30. The switching circuit 30 outputs a voltage reference signal vref_afc to the inductor-capacitor voltage-controlled oscillator 40, and changes the frequency of the output signal clk_o. The first counter 51 periodically counts the pulses of the clock reference signal clk_ref, and the second counter 52 periodically counts the pulse count of the output signal clk_o. The higher the frequency of the output signal clk_o, the more pulses per unit time. The difference circuit 53 compares the difference between the two pulse counts and obtains the difference signal.
[0123] In calibration mode, the bit adjustment circuit 54 adjusts the output of the digital code signal C_ctl according to the magnitude of the difference signal. When the difference between the first count value and the second count value is large, that is, when the difference signal is greater than the preset difference, the bit adjustment circuit 54 outputs the changing digital code signal C_ctl. When the frequency of the output signal clk_o is close to the frequency of the clock reference signal clk_ref and the second count value is close to the first count value, the difference signal is less than the preset difference. At this time, the calibration mode ends, and the bit adjustment circuit 54 selects to latch the output of the digital code signal C_ctl from the previous moment. Simultaneously, the second switching signal, which is low-level, is switched out. After the detection and control circuit 60 detects the second switching signal, it outputs a shutdown signal afc_pd to the power switch 55, thereby cutting off the power supply to each circuit module of the automatic frequency control circuit 50. The automatic frequency control circuit 50 stops working, and the first output terminal of the bit adjustment circuit 54 remains low-level. It also maintains the connection between the control switching circuit 30 and the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. The frequency and phase detector 10, the charge pump circuit 20, and the inductor-capacitor voltage-controlled oscillator 40 complete the subsequent frequency adjustment work until the frequency of the output signal clk_o reaches the frequency of the clock reference signal clk_ref, and the bit adjustment circuit 54 cuts off the output digital code signal C_ctl. The latch circuit 70 latches the digital code signal C_ctl and outputs it to the inductor-capacitor voltage-controlled oscillator 40.
[0124] The difference circuit 53 can be a subtractor, a flip-flop, or other structure, and adjusts the output of the digital code signal C_ctl according to the difference.
[0125] The bit adjustment circuit 54 can adopt a corresponding digital control logic circuit, which may include a corresponding digital circuit, analog-to-digital conversion circuit, and digital-to-analog conversion circuit, etc.
[0126] The power switch 55 can be a switching device with controlled on / off switching, such as an NMOS transistor or an NPN transistor.
[0127] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The above-mentioned phase-locked loop circuit includes a frequency and phase detector 10, a charge pump circuit 20, a switching circuit 30, an inductor-capacitor voltage-controlled oscillator 40, an automatic frequency control circuit 50, and a detection and control circuit 60. In calibration mode, the automatic frequency control circuit 50 controls the switching circuit 30 to output a voltage reference signal vref_afc and an output digital code signal C_ctl, thereby changing the capacitance value in the inductor-capacitor voltage-controlled oscillator 40, and thus changing the frequency value of the output signal clk_o of the phase-locked loop circuit. After calibration is completed... Subsequently, the frequency and phase detector 10 and the charge pump circuit 20 output a changing first voltage signal Vout, which changes the capacitance of the inductor-capacitor voltage-controlled oscillator 40 and the frequency of the output signal clk_o of the phase-locked loop circuit. After the calibration mode ends, the detection control circuit 60 outputs a shutdown signal afc_pd to shut down the automatic frequency control circuit 50, reducing additional circuit power consumption. Furthermore, when there is external signal disturbance, since the automatic frequency control circuit 50 is already shut down, the digital code signal C_ctl input to the inductor-capacitor voltage-controlled oscillator 40 will not change, thus eliminating the influence of disturbance.
[0128] A second aspect of this utility model provides an image sensor, which includes a phase-locked loop (PLL) circuit. The specific structure of the PLL circuit is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here. The PLL circuit, as a high-speed clock generator, provides clock signals to the image sensor to meet the operating requirements of each module.
[0129] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.
Claims
1. A phase-locked loop circuit, characterized in that, include: A frequency and phase detector is configured to detect the frequencies of a clock reference signal and the output signal of the phase-locked loop circuit, and generate a control signal. A charge pump circuit, connected to the frequency and phase detector, is configured to receive the control signal and charge / discharge it, and output a first voltage signal that changes in relation to the control signal. The switching circuit is connected to the charge pump circuit and the reference voltage terminal respectively, and is configured to switch the output of the voltage reference signal of the reference voltage terminal by a first switching signal, and to switch the output of the first voltage signal by a second switching signal. An inductor-capacitor voltage-controlled oscillator is connected to the switching circuit. The inductor-capacitor voltage-controlled oscillator is configured to adjust the size of its internal capacitor according to the corresponding signal among the received voltage reference signal, the first voltage signal, and the digital code signal, so as to adjust the frequency and phase of the output signal of the phase-locked loop circuit. The automatic frequency control circuit, connected to both the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured as follows: In calibration mode, the first switching signal is output, and the frequencies of the clock reference signal and the output signal of the phase-locked loop circuit are detected, and the corresponding digital code signal is generated. After calibration, the second switching signal is switched to be output. A detection control circuit, connected to the control terminal of the automatic frequency control circuit, is used to output a shutdown signal to control the automatic frequency control circuit to shut down when the second switching signal is detected.
2. The phase-locked loop circuit as described in claim 1, characterized in that, The phase-locked loop circuit also includes: A latching circuit is connected between the automatic frequency control circuit and the inductor-capacitor voltage-controlled oscillator. The latching circuit is used to latch the digital code signal and output it to the inductor-capacitor voltage-controlled oscillator.
3. The phase-locked loop circuit as described in claim 2, characterized in that, The detection control circuit includes a first logic gate; The first input terminal of the first logic gate is connected to the first output terminal of the automatic frequency control circuit, the second input terminal of the first logic gate is used to input an enable signal, and the output terminal of the first logic gate is connected to the control terminal of the automatic frequency control circuit.
4. The phase-locked loop circuit as described in claim 3, characterized in that, The latch circuit includes a second logic gate and a latch; The first input terminal of the second logic gate is connected to the first output terminal of the automatic frequency control circuit. The second input terminal of the second logic gate is used to input the enable signal. The output terminal of the second logic gate is connected to the reset terminal of the latch. The set terminal of the latch is connected to the second output terminal of the automatic frequency control circuit. The output terminal of the latch is connected to the second input terminal of the inductor-capacitor voltage-controlled oscillator.
5. The phase-locked loop circuit as described in any one of claims 1 to 4, characterized in that, The switching circuit includes a first switch and a second switch; The first terminal of the first switch is connected to the reference voltage terminal, the second terminal of the first switch and the second terminal of the second switch are connected to the first input terminal of the inductor-capacitor voltage-controlled oscillator, the first terminal of the second switch is connected to the output terminal of the charge pump circuit, and the control terminal of the first switch and the control terminal of the second switch are connected to the first output terminal of the automatic frequency control circuit.
6. The phase-locked loop circuit as described in any one of claims 1 to 4, characterized in that, The inductor-capacitor voltage-controlled oscillator includes an inductor, an adjustable capacitor unit, a capacitor array, a first switch, a second switch, and a third switch. The inductor, the adjustable capacitor unit, and the capacitor array are connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator. The first terminal of the first switch, the control terminal of the second switch, and the first output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The first terminal of the second switch, the control terminal of the first switch, and the second output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The second terminal of the first switch, the second terminal of the second switch, and the first terminal of the third switch are connected. The second terminal of the third switch is grounded. The control terminal of the third switch is used to receive a reference voltage. The control terminal of the adjustable capacitor unit constitutes the first input terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the capacitor array constitutes the second input terminal of the inductor-capacitor voltage-controlled oscillator. The adjustable capacitor unit is configured to switch the output capacitance of different sizes according to the voltage reference signal or the first voltage signal; The capacitor array includes multiple capacitor units with preset capacitance values. The capacitor array is configured to switch different numbers of capacitor units connected between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator according to the digital code signal.
7. The phase-locked loop circuit as described in claim 6, characterized in that, The adjustable capacitor unit includes a first capacitor, a first adjustable capacitor, a second adjustable capacitor, and a second capacitor connected in series between the first output terminal and the second output terminal of the inductor-capacitor voltage-controlled oscillator. The control terminals of the first and second adjustable capacitors are used to receive the voltage reference signal or the first voltage signal.
8. The phase-locked loop circuit as described in claim 6, characterized in that, The capacitor array includes multiple capacitor units connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator. Each of the capacitor units includes a third capacitor, a fourth capacitor, a fourth switch, a fifth switch, and a sixth switch; The first terminal of the third capacitor is connected to the first output terminal of the inductor-capacitor voltage-controlled oscillator. The second terminal of the third capacitor, the first terminal of the fourth switch, and the fifth switch are connected. The second terminal of the fourth switch, the first terminal of the fourth capacitor, and the first terminal of the sixth switch are connected. The second terminal of the fourth capacitor is connected to the second output terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the fourth switch is used to receive one bit of the digital code signal. The second terminals of the fifth and sixth switches are grounded. The control terminals of the fifth and sixth switches are connected and receive a digital signal with an opposite level to the control terminal of the fourth switch.
9. The phase-locked loop circuit as described in any one of claims 1 to 4, characterized in that, The automatic frequency control circuit includes: The first counter is used to periodically count the number of pulses of the clock reference signal within a preset time period and output a first count value; The second counter is used to periodically count the number of pulses of the output signal of the phase-locked loop circuit within a preset time period and output a second count value. A difference circuit is used to compare the first count value and the second count value, and output a difference signal; A bit adjustment circuit, connected to the difference circuit, the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured to output a first switching signal in calibration mode, output a changing digital code signal when the difference signal is greater than a preset difference, and latch and output the digital code signal of the previous moment and the second switching signal when the difference signal is less than the preset difference. A power switch is connected to the positive power supply terminal and the power supply terminals of the first counter, the second counter, the difference circuit, and the bit adjustment circuit, respectively. The power switch is configured to be triggered to turn off according to the shutdown signal, so as to control the automatic frequency control circuit to shut down.
10. An image sensor, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1 to 9.
Citation Information
Cited By
An ultra-wideband high-precision instantaneous frequency measurement circuit and method
CN122330504A