Patterned composite substrate and LED chip
By fabricating a patterned composite substrate on a sapphire substrate of GaN-based LEDs and using alternating SiO2 layers to change the direction of light propagation, the problem of low light extraction efficiency was solved, resulting in higher luminous efficiency and device stability.
Patent Information
- Application Number
- CN202423243258.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2034-12-27
AI Technical Summary
Traditional GaN-based LED manufacturing processes face challenges in light extraction efficiency, especially due to total internal reflection caused by the refractive index difference between the sapphire substrate and the GaN layer, which prevents light from being effectively emitted, affecting luminous efficiency and device reliability.
A patterned composite substrate is used, including a patterned base layer and a composite layer. The patterned base layer has a recessed structure, and the composite layer is filled with alternating first SiO2 layers and second SiO2 layers to change the direction of light propagation, reduce total internal reflection, improve light emission efficiency, and form a heat conduction path.
It significantly improves light extraction efficiency, reduces chip operating temperature, enhances device reliability and stability, extends lifespan, and reduces the risk of substrate breakage.
Smart Images
Figure CN223943112U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a patterned composite substrate and an LED chip. Background Technology
[0002] In the field of modern optoelectronics, gallium nitride (GaN)-based light-emitting diodes (LEDs) have attracted much attention due to their advantages such as high brightness, low power consumption, and long lifespan, and are widely used in lighting, displays, and various indicators. However, with the rapid development of technology and the continuous increase in application demands, traditional GaN-based LED manufacturing processes face many challenges in terms of light extraction efficiency. GaN material is grown on a sapphire substrate (Al2O3). Due to the large difference in refractive index between the two, when light propagates within the GaN layer and reaches the interface with the sapphire substrate, total internal reflection is very likely to occur. This results in a large amount of light being trapped inside the chip and unable to be effectively emitted, severely limiting the luminous efficiency of the LED.
[0003] In existing technologies, a patterned sapphire substrate is fabricated by depositing a SiO2 thin film on a sapphire substrate using plasma-enhanced chemical vapor deposition (PECVD), followed by pre- and post-lithography and dry etching techniques to improve light extraction efficiency. The resulting patterned sapphire substrate includes recessed structures and raised SiO2 layers. However, the recessed structures in the patterned sapphire substrate are composed of air, which has a significant refractive index difference from sapphire. Light is still prone to total internal reflection at the interface of the recessed structures, thus limiting the improvement in the device's light extraction performance. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide a patterned composite substrate and an LED chip, which can increase light reflection, improve the light extraction efficiency of LED epitaxial wafers, reduce the temperature of the chip during operation, and improve the reliability and stability of the device.
[0005] To solve the above-mentioned technical problems, the first aspect of this utility model provides a patterned composite substrate, including a patterned base layer and a composite layer disposed on the patterned base layer;
[0006] The patterned substrate layer includes a sapphire substrate and a plurality of recessed structures provided on the surface of the sapphire substrate, wherein the recessed structures are non-penetrating on the sapphire substrate;
[0007] The composite layer includes a first SiO2 layer and a second SiO2 layer arranged in a periodic alternation. The first SiO2 layer is disposed on the surface of the sapphire substrate, and the second SiO2 layer fills the recessed structure. The first SiO2 layer and the second SiO2 layer are connected to each other.
[0008] As an improvement to the above scheme, the thickness ratio of the first SiO2 layer to the patterned substrate layer is 1:(0.9~2);
[0009] The thickness ratio of the second SiO2 layer to the patterned substrate layer is 1:(2.5~4).
[0010] As an improvement to the above scheme, the distribution density of the first SiO2 layer is 5×10⁻⁶. 6 pcs / cm 2 ~8×10 7 pcs / cm 2 ;
[0011] The distribution density of the second SiO2 layer is 5×10 6 pcs / cm 2 ~8×10 7 pcs / cm 2 .
[0012] As an improvement to the above scheme, the width of the second SiO2 layer is 750nm to 850nm;
[0013] The thickness of the second SiO2 layer is 600nm to 1000nm.
[0014] As an improvement to the above scheme, the thickness of the first SiO2 layer is 1800nm to 3000nm;
[0015] The first SiO2 layer has a bottom surface with a width of 2900 nm to 3200 nm.
[0016] As an improvement to the above scheme, the sidewall of the first SiO2 layer and the bottom of the first SiO2 layer have a first tilt angle, the first tilt angle being 55° to 75°.
[0017] As an improvement to the above scheme, the sidewall of the second SiO2 layer and the bottom of the second SiO2 layer have a second tilt angle, the second tilt angle being 100° to 110°.
[0018] As an improvement to the above scheme, the shape of the first SiO2 layer is conical, pyramidal, quasi-conical, or quasi-pyramidal;
[0019] The shape of the second SiO2 layer is frustum-shaped, truncated pyramid-shaped, frustum-like, or truncated pyramid-like.
[0020] As an improvement to the above scheme, the first SiO2 layer is distributed on the patterned composite substrate in one of the following ways: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasi-crystalline arrangement, and random arrangement.
[0021] The second SiO2 layer is distributed on the patterned composite substrate in one of the following ways: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasi-crystalline arrangement, or random arrangement.
[0022] A second aspect of this invention also provides an LED chip, including the patterned composite substrate.
[0023] Implementing this utility model has the following beneficial effects:
[0024] The patterned composite substrate of this invention includes a patterned base layer and a composite layer disposed on the patterned base layer. The patterned base layer includes a sapphire substrate and a plurality of recessed structures disposed on the surface of the sapphire substrate, the recessed structures being non-penetrating on the sapphire substrate. The composite layer includes a first SiO2 layer and a second SiO2 layer arranged in a periodically alternating manner. The first SiO2 layer is disposed on the surface of the sapphire substrate, and the second SiO2 layer fills the recessed structures. The first SiO2 layer and the second SiO2 layer are connected, which not only changes the direction of light propagation, reduces total internal reflection, and improves light emission efficiency, but also forms an effective heat conduction path, helping to reduce the temperature of the chip during operation, improve the reliability and stability of the device, and extend the lifespan of the device. In addition, it can also maintain the integrity of the sapphire substrate, making the substrate less prone to cracking during subsequent processing, packaging, and use, especially when subjected to external forces or thermal stress. Attached Figure Description
[0025] Figure 1 This utility model provides a schematic diagram of the structure of a patterned composite substrate;
[0026] Figure 2 This utility model provides a schematic diagram of a graphical base layer structure;
[0027] Figure 3 : Figure 1 A local method diagram of region A in the middle.
[0028] Reference numerals: 1-patterned substrate layer; 11-recessed structure; 2-composite layer; 21-first SiO2 layer; 22-second SiO2 layer. Detailed Implementation
[0029] To make the objectives, technical solutions and advantages of this utility model clearer, specific embodiments will be described in further detail below.
[0030] In the description of this application, it is necessary to understand that the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", "inner", and "outer" are based on the orientation or positional relationship shown in the accompanying drawings. The purpose is only to facilitate the description of this utility model and simplify the description, and is not intended to indicate or imply that the component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model.
[0031] To address the aforementioned problems, the first aspect of this utility model provides a patterned composite substrate, please refer to [link / reference]. Figure 1 It includes a patterned base layer 1 and a composite layer 2 disposed on the patterned base layer 1. The composite layer 2 disposed on the patterned base layer 1 can change the propagation direction of light, enhance the reflection ability of light, reduce total internal reflection of light, and improve the light emission efficiency.
[0032] Please refer to Figure 2 The patterned substrate 1 includes a sapphire substrate (not shown in the figure) and a plurality of recessed structures 11 provided on the surface of the sapphire substrate, which provide a position for the second SiO2 layer 22 and facilitate the formation of the patterned substrate 1. The recessed structures 11 are non-penetrating on the sapphire substrate. After filling the second SiO2 layer 22, multiple local refractive index change regions are formed, which effectively changes the light propagation path and improves the light extraction efficiency. Moreover, it can also maintain the integrity of the sapphire substrate. In subsequent processing, packaging and use, the substrate is less likely to crack or other problems, especially when subjected to external force or thermal stress.
[0033] The composite layer 2 includes a first SiO2 layer 21 and a second SiO2 layer 22 arranged in a periodic alternation. The first SiO2 layer 21 is disposed on the surface of the sapphire substrate, and the second SiO2 layer 22 fills the recessed structure 11. The first SiO2 layer 21 and the second SiO2 layer 22 are connected. The refractive index of SiO2 is between that of air and sapphire. The connection of the first SiO2 layer 21 and the second SiO2 layer 22 forms a continuous optical medium, allowing more light that would otherwise be trapped inside the sapphire due to total internal reflection to change its propagation direction through the refraction of SiO2, significantly improving light extraction efficiency. More importantly, it enables more precise modulation of the photon propagation direction, allowing more light to couple into the escape cones on the upper and lower surfaces of the chip, further improving the device's luminous efficiency and forming an effective heat conduction path, which helps to reduce the chip's operating temperature, improve the device's reliability and stability, and extend its lifespan. If a second SiO2 layer 22 is not provided in the recessed structure 11, more light will be unable to escape smoothly after total internal reflection inside the sapphire substrate. Moreover, under some harsh environmental conditions, such as high humidity or corrosive gas environments, chemical reactions may occur at multiple recessed structures 11, causing a decrease in the performance and reliability of the LED epitaxial wafer.
[0034] Preferably, the distribution density of the first SiO2 layer 21 is 5 × 10⁻⁶. 6 pcs / cm 2 ~8×10 7 pcs / cm 2 The distribution density of the second SiO2 layer 22 is 5×10⁻⁶. 6 pcs / cm 2 ~8×10 7 pcs / cm 2 If the distribution density of the first SiO2 layer 21 and / or the second SiO2 layer 22 is too high, it will cause multiple scatterings of light within the substrate and occupy more surface space, hindering current expansion and thus reducing light extraction efficiency. It will also make the epitaxial layer growth surface too rough, increasing the growth difficulty. Conversely, when the distribution density is low, it has little impact on the heat dissipation channels of the sapphire substrate, which is beneficial for heat dissipation. However, the light emission angle is relatively concentrated, which may lead to uneven light emission. Optionally, the distribution of the first SiO2 layer 21 on the patterned composite substrate is one of the following: rectangular array arrangement, hexagonal close-packed arrangement, aperiodic quasicrystalline arrangement, or random arrangement; the distribution of the second SiO2 layer 22 on the patterned composite substrate is one of the following: rectangular array arrangement, hexagonal close-packed arrangement, aperiodic quasicrystalline arrangement, or random arrangement.
[0035] Furthermore, the thickness ratio of the first SiO2 layer 21 to the patterned substrate layer 1 is 1:(0.9~2), and the thickness ratio of the second SiO2 layer 22 to the patterned substrate layer 1 is 1:(2.5~4). While optimizing the light propagation path, this promotes the uniform distribution of current on the substrate and improves the light emission uniformity of the LED chip. If the thickness of the first SiO2 layer 21 or the second SiO2 layer 22 is large, excessive scattering will occur at the first SiO2 layer 21 or the second SiO2 layer 22, leading to increased light loss. It may also cause the current to accumulate near the first SiO2 layer 21 or the second SiO2 layer 22, increasing the local current density and causing problems such as local overheating. If the thickness of the first SiO2 layer 21 or the second SiO2 layer 22 is small, it will limit the improvement effect of light extraction efficiency.
[0036] The shapes of the first SiO2 layer 21 and the second SiO2 layer 22 in composite layer 2 affect the reflection and refraction paths of light and the distribution of current on the substrate surface. (See also...) Figure 3 The sidewalls and bottom of the first SiO2 layer 21 have a first tilt angle θ1, which is 55° to 75°. The sidewalls and bottom of the second SiO2 layer 22 have a second tilt angle θ2, which is 100° to 110°. This patterned composite substrate provides a unique template for the epitaxial growth of GaN material, guiding the GaN crystal to grow along a specific crystal orientation, reducing crystal defects, improving crystal quality, and thus improving carrier transport and recombination characteristics, promoting luminous efficiency, and ultimately enhancing the overall performance of the device. Optionally, the first SiO2 layer 21 is conical, pyramidal, quasi-conical, or quasi-pyramidal, and the second SiO2 layer 22 is frustum-shaped, truncated cone-shaped, quasi-frustum-shaped, or truncated cone-shaped.
[0037] In some specific and preferred embodiments, the thickness H1 of the first SiO2 layer 21 is 1800nm to 3000nm, exemplarily 1800nm, 2000nm, 2200nm, 2400nm, 2600nm, 2800nm, and 3000nm, but not limited thereto; the first SiO2 layer 21 has a bottom surface, the width W1 of which is 2900nm to 3200nm, exemplarily 2900nm, 2950nm, 3000nm, and 3050nm. The thickness H2 of the second SiO2 layer 22 is 750nm to 850nm, exemplarily 750nm, 775nm, 800nm, 825nm, or 850nm, but not limited to these values; the thickness H2 of the second SiO2 layer 22 is 600nm to 1000nm, exemplarily 600nm, 700nm, 800nm, 900nm, or 1000nm, but not limited to these values. It should be noted that the top width W2 of the second SiO2 layer 22 is the diameter of the upper bottom surface of the frustum-like structure that contacts the first SiO2 layer 21, or the side length of the upper bottom surface of the frustum-like structure that contacts the first SiO2 layer 21.
[0038] The height, dimensions, shape, and position of the lower and upper surfaces of the composite layer 2 can all be controlled by appropriately adjusting the etching conditions and mask of the photolithography process. In some embodiments, the patterned composite substrate disclosed in this invention is prepared by the following method:
[0039] (1) Forming a first photolithography pattern on a sapphire substrate;
[0040] Specifically, photolithography or imprinting can be performed on the sapphire substrate to form a mask for etching the sapphire substrate:
[0041] The photolithography process includes: coating a photoresist onto a sapphire substrate; exposing the photoresist to light; and finally developing the photoresist.
[0042] The photoresist is spin-coated using a spin coater at a speed of 2000 rpm to 3500 rpm, with the photoresist thickness controlled at 1.5 μm to 2.5 μm and the viscosity at 16 cp to 56 cp. The baking temperature is 80℃ to 140℃, and the baking time is 60 s to 150 s. The exposed sapphire substrate with photoresist is then developed with a developer for 30 s to 80 s. In some embodiments, multiple cylindrical patterns are formed after development, with a pattern period of 2.9 μm to 3.2 μm, a diameter of 1.8 μm to 2.5 μm, and a height of 1.5 μm to 3.0 μm.
[0043] The imprinting process includes: coating a photoresist onto a sapphire substrate; applying pressure to the photoresist to imprint the desired pattern.
[0044] In this process, a spin coater is used to coat the photoresist at a spin speed of 1800 r / min to 3500 r / min, controlling the photoresist thickness to be 0.7 μm to 1.2 μm. The baking temperature is 80℃ to 140℃, and the baking time is 60 s to 100 s. In some embodiments, multiple cylindrical patterns are formed after imprinting, with a pattern period of 2.9 μm to 3.2 μm, a diameter of 1.8 μm to 2.5 μm, and a height of 1.5 μm to 3.0 μm. In other embodiments, multiple frustum-shaped patterns are formed after imprinting, with an upper base width of 1.7 μm to 2.1 μm, a lower base width of 1.8 μm to 2.5 μm, and a height of 1.5 μm to 3.0 μm.
[0045] (2) The sapphire substrate after photolithography is etched to form multiple recessed structures 11, and a patterned base layer 1 is obtained;
[0046] The photolithographically etched gemstone substrate is then subjected to segmented etching in an etching machine. Etching parameters such as etching gas, etching gas flow rate, and radio frequency power can be flexibly adjusted according to the specific etching objective. Specifically, this includes:
[0047] (21) Perform the first stage of etching until the photoresist is removed and a recessed structure 11 is initially formed;
[0048] (22) The initially formed recessed structure 11 is etched so that the depth and width of the recessed structure 11 reach the preset values. In some embodiments, after etching, the opening depth of the sapphire substrate is 600nm to 1000nm and the width is 750nm to 850nm.
[0049] (3) Deposit a SiO2 layer on the patterned substrate 1;
[0050] Specifically, the patterned substrate 1 is placed in an enhanced plasma chemical vapor deposition (PECVD) apparatus. The chamber pressure is controlled to be 1500 Pa to 3000 Pa, the radio frequency power to be 500 W to 2000 W, and the chamber temperature to be 250 °C to 350 °C. SiH4 (gas purity of 99.999%), N2O, and N2 are introduced, with SiH4:N2O:C2F6 = 1:(25 to 1):60. The apparatus generates plasma through glow discharge in the SiH4 and N2O gases, causing SiO2 to fill the recessed structure 11, forming a second SiO2 layer 22. A SiO2 thin film with a thickness of 1.8 μm to 3.0 μm is formed on the surface of the patterned substrate 1.
[0051] (4) Form a second photolithography pattern on the SiO2 layer;
[0052] Specifically, the SiO2 layer can be photolithographically etched or imprinted to form a mask for etching the SiO2 layer.
[0053] The photolithography process includes: coating a photoresist onto a sapphire substrate; exposing the photoresist to light; and finally developing the photoresist.
[0054] The process involves spin-coating photoresist using a spin coater at a speed of 2000 rpm to 3500 rpm, controlling the photoresist thickness to be 1.5 μm to 2.5 μm, the viscosity to be 16 cp to 46 cp, and baking at 80℃ to 140℃ for 60 to 150 seconds. The exposed sapphire substrate with photoresist is then developed using a developer for 30 to 80 seconds. After development, multiple cylindrical patterns are formed, with a pattern period of 2.9 μm to 3.2 μm, a diameter of 1.8 μm to 2.5 μm, and a height of 1.5 μm to 3.0 μm.
[0055] The imprinting process includes: coating a photoresist onto a sapphire substrate; applying pressure to the photoresist to imprint the desired pattern.
[0056] The photoresist was spin-coated using a spin coater at a speed of 2000 rpm to 3500 rpm, with the photoresist thickness controlled between 0.7 μm and 1.2 μm. The baking temperature was between 80℃ and 140℃, and the baking time was between 60 and 100 seconds. After imprinting, multiple cylindrical or frustum-shaped patterns were formed, with a pattern period of 2.9 μm to 3.2 μm. The diameter of the cylindrical patterns was 1.8 μm to 2.5 μm, and the height was 1.5 μm to 3.0 μm. The upper base width of the frustum-shaped patterns was 1.7 μm to 2.1 μm, the lower base width was 1.8 μm to 2.5 μm, and the height was 1.5 μm to 3.0 μm.
[0057] (5) Etch the photolithographically etched sapphire substrate to form a first SiO2 layer 21, and connect the first SiO2 layer 21 and the second SiO2 layer 22 to form a composite layer 2.
[0058] The photolithographically etched gemstone substrate is then etched in segments in an etching machine. Etching parameters such as etching gas, etching gas flow rate, and radio frequency power can be flexibly adjusted according to different etching purposes.
[0059] Accordingly, this utility model also discloses an LED chip, including the above-mentioned patterned composite substrate.
[0060] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications are also considered to be within the protection scope of this utility model.
Claims
1. A patterned composite substrate, characterized in that, It includes a graphical base layer and a composite layer disposed on the graphical base layer; The patterned substrate layer includes a sapphire substrate and a plurality of recessed structures provided on the surface of the sapphire substrate, wherein the recessed structures are non-penetrating on the sapphire substrate; The composite layer includes a first SiO2 layer and a second SiO2 layer arranged in a periodic alternation. The first SiO2 layer is disposed on the surface of the sapphire substrate, and the second SiO2 layer fills the recessed structure. The first SiO2 layer and the second SiO2 layer are connected to each other.
2. The patterned composite substrate as described in claim 1, characterized in that, The thickness ratio of the first SiO2 layer to the patterned substrate layer is 1:(0.9~2); The thickness ratio of the second SiO2 layer to the patterned substrate layer is 1:(2.5~4).
3. The patterned composite substrate as described in claim 1, characterized in that, The distribution density of the first SiO2 layer is 5×10 6 pcs / cm 2 ~8×10 7 pcs / cm 2 ; The distribution density of the second SiO2 layer is 5×10 6 pcs / cm 2 ~8×10 7 pcs / cm 2 .
4. The patterned composite substrate according to any one of claims 1-3, characterized in that, The width of the second SiO2 layer is 750nm to 850nm; The thickness of the second SiO2 layer is 600nm to 1000nm.
5. The patterned composite substrate according to any one of claims 1-3, characterized in that, The thickness of the first SiO2 layer is 1800 nm to 3000 nm; The first SiO2 layer has a bottom surface with a width of 2900 nm to 3200 nm.
6. The patterned composite substrate as described in claim 1, characterized in that, The sidewalls of the first SiO2 layer and the bottom of the first SiO2 layer have a first tilt angle, which is 55° to 75°.
7. The patterned composite substrate as described in claim 1, characterized in that, The sidewalls of the second SiO2 layer and the bottom of the second SiO2 layer have a second tilt angle, which is 100° to 110°.
8. The patterned composite substrate as described in claim 1, characterized in that, The shape of the first SiO2 layer is conical, pyramidal, quasi-conical, or quasi-pyramidal; The shape of the second SiO2 layer is frustum-shaped, truncated pyramid-shaped, frustum-like, or truncated pyramid-like.
9. The patterned composite substrate as described in claim 1, characterized in that, The first SiO2 layer is distributed on the patterned composite substrate in one of the following ways: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasi-crystalline arrangement, or random arrangement. The second SiO2 layer is distributed on the patterned composite substrate in one of the following ways: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasi-crystalline arrangement, or random arrangement.
10. An LED chip, characterized in that, Includes the patterned composite substrate as described in any one of claims 1 to 9.