Patterned sapphire composite substrate and LED epitaxial wafer

Abstract

The utility model discloses a patterned sapphire composite substrate and an LED epitaxial wafer. The patterned sapphire composite substrate comprises a sapphire substrate and a plurality of patterned structures distributed on the sapphire substrate. Each patterned structure comprises a sapphire base and a silicon dioxide layer stacked on the sapphire base, the size of the top of the sapphire base is larger than or equal to the size of the bottom of the silicon dioxide layer, the height of each patterned structure ranges from 0.8 micrometer to 2 micrometers, and the thickness of each patterned structure ranges from 1 micrometer to 2 micrometers. The ratio of the height of the silicon dioxide layer to the height of the sapphire base is 1: (0.06-0.18). By adopting the patterned sapphire composite substrate provided by the utility model, the luminous efficiency of an LED epitaxial wafer can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially to a patterned sapphire composite substrate and LED epitaxial wafer. BACKGROUND

[0002] Gallium nitride (GaN) is used as the epitaxial material of LED, and is mainly epitaxially grown on SiC, Si and sapphire and other hetero-substrates, but the hetero-substrate and GaN epitaxial material have a large lattice mismatch and thermal mismatch, which causes the quality of GaN epitaxial material to decrease. The patterned sapphire substrate (PSS) can reduce the dislocation density of GaN epitaxial layer through the pattern array, relax the stress generated in the process of hetero-epitaxial growth, and also can enhance the scattering of light and improve the light extraction efficiency of LED. However, the refractive index of sapphire is not much different from that of GaN material, which is not conducive to further improving the light extraction efficiency of LED, and the etching of sapphire substrate has the disadvantages of slow etching rate and difficult to control uniformity. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide a patterned sapphire composite substrate and LED epitaxial wafer, which can improve the light extraction efficiency of LED epitaxial wafer by using the patterned sapphire composite substrate provided by the utility model.

[0004] In order to solve the above technical problems, the utility model discloses a kind of patterned sapphire composite substrates, including sapphire substrate and multiple patterned structures distributed on the sapphire substrate;The patterned structure includes sapphire pedestal and silicon dioxide layer stacked on the sapphire pedestal, the top size of the sapphire pedestal is greater than or equal to the bottom size of the silicon dioxide layer, the height of each patterned structure is 0.8 μm ~ 2 μm, wherein the height ratio of the silicon dioxide layer and the height of the sapphire pedestal is 1:(0.06 ~ 0.18).

[0005] As an improvement of the above scheme, the height ratio of the silicon dioxide layer and the height of the sapphire pedestal is 1:(0.08 ~ 0.14).

[0006] As an improvement of the above scheme, the bottom size of the sapphire pedestal is 2.5 μm ~ 3.5 μm, and the bottom distance between adjacent two sapphire pedestals is 0.2 μm ~ 0.5 μm.

[0007] As an improvement of the above scheme, the sidewall of the sapphire pedestal has a first inclination angle with the bottom of the sapphire pedestal, and the first inclination angle is 70 ° ~ 85 °.

[0008] As the improvement of the above scheme, the bottom edge of the silicon dioxide layer has a preset distance from the top edge of the sapphire base, and the ratio of the preset distance to the bottom size of the sapphire base is 1:(150-300).

[0009] As the improvement of the above scheme, the sidewall of the silicon dioxide layer has a second inclination angle with the bottom of the silicon dioxide layer, and the second inclination angle is 60-75 degrees.

[0010] As the improvement of the above scheme, the sidewall of the silicon dioxide layer is an outward convex curved surface, and the convex height of the sidewall of the silicon dioxide layer is 20-180 nm.

[0011] As the improvement of the above scheme, the sapphire base has a shape of a circular truncated cone or a prismatic truncated cone, and the silicon dioxide layer has a shape of one or more of a circular truncated cone, a prismatic truncated cone, a circular cone, and a prismatic cone.

[0012] As the improvement of the above scheme, the distribution mode of the patterned structure on the sapphire base is one of a rectangular array arrangement, a hexagonal closest packing arrangement, a non-periodic quasi-crystal arrangement, and a random arrangement.

[0013] The utility model discloses still a kind of LED epitaxial wafer, including above-mentioned patterned sapphire composite substrate, and epitaxial structure stacked on the patterned sapphire composite substrate.

[0014] The utility model discloses, with following beneficial effect: the patterned sapphire composite substrate of embodiment provided by the utility model includes sapphire base and silicon dioxide layer, and the setting of silicon dioxide layer can significantly improve the etching efficiency of patterned structure, and the silicon dioxide layer of low refractive index can further improve LED light efficiency. By limiting the height ratio of sapphire base and silicon dioxide layer, while guaranteeing the size of patterned structure, sapphire material is fully exposed, and subsequent GaN epitaxial structure is conveniently grown in high quality. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is the structure schematic diagram of patterned sapphire composite substrate provided by an embodiment of the utility model;

[0016] Figure 2 It is the structure schematic diagram of patterned sapphire composite substrate provided by another embodiment of the utility model;

[0017] Figure 3 It is the structure schematic diagram of patterned sapphire composite substrate provided by another embodiment of the utility model. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of this utility model clearer, the following will describe this utility model in further detail with reference to the accompanying drawings. It is hereby declared that the terms "up," "down," "left," "right," "front," "back," "inner," and "outer," etc., appearing or about to appear in this document, are based solely on the accompanying drawings and are not intended to specifically limit this utility model.

[0019] like Figure 1 As shown, this embodiment of the present invention provides a patterned sapphire composite substrate, including a sapphire substrate 1 and a plurality of patterned structures 2 distributed on the sapphire substrate 1; the patterned structure 2 includes a sapphire base 21 and a silicon dioxide layer 22 stacked on the sapphire base 21, the top dimension of the sapphire base 21 is greater than or equal to the bottom dimension of the silicon dioxide layer 22, and the height H1 of each patterned structure 2 is 0.8μm to 2μm, wherein the ratio of the height H2 of the silicon dioxide layer 22 to the height H3 of the sapphire base 21 is 1:(0.06 to 0.18).

[0020] By fabricating patterned structures on a sapphire substrate with a silicon dioxide layer, the quality of GaN epitaxial material grown on it can be effectively improved. The patterned substrate induces dislocation bending during GaN epitaxial growth, thereby reducing the dislocation density of the GaN film. The low refractive index of silicon dioxide can also increase LED brightness by increasing reflection and scattering. The sapphire substrate 21 ensures the exposure of the sapphire base surface, which provides a nucleation region for GaN epitaxial growth, ensuring high-quality growth. Controlling the ratio of the height H2 of the silicon dioxide layer 22 to the height H3 of the sapphire substrate 21 ensures that the silicon dioxide layer 22 maintains the volume of the patterned structure 2, meeting light reflection requirements and improving light extraction efficiency. The sapphire substrate 21, located at the bottom of the patterned structure 2, prevents light from escaping from the bottom, increasing light extraction and improving light extraction efficiency.

[0021] In a preferred embodiment, the ratio of the height H2 of the silicon dioxide layer 22 to the height H3 of the sapphire base 21 is 1:(0.08 to 0.14), and exemplary ratios are 1:0.09, 1:0.1, 1:0.11, 1:0.12 or 1:0.13, but are not limited thereto.

[0022] The shape of the patterned structure directly affects the growth quality of the epitaxial layer. The bottom dimension D1 of the sapphire substrate 21 is 2.5 μm to 3.5 μm, exemplarily 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, or 3.4 μm, but not limited to these. The bottom spacing L1 between two adjacent sapphire substrates is 0.2 μm to 0.5 μm, exemplarily 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or 0.45 μm, but not limited to these. It is understood that the arrangement of the patterned structure can be one of the following: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasicrystalline arrangement, or random arrangement. Specifically, the shape of the sapphire substrate can be frustum-like or frustum-like. The bottom and top of the frustum-shaped sapphire base 21 are both circular, and the bottom dimension D1 of the sapphire base 21 is the diameter of the bottom circle; the bottom and top of the frustum-shaped sapphire base 21 are both polygonal, and the bottom dimension D1 of the sapphire base 21 is the diameter of the circumcircle of the bottom polygon.

[0023] The sidewalls and bottom of the sapphire substrate 21 have a first tilt angle θ1, which is 70° to 85°, exemplarily 72°, 74°, 78°, 80°, or 82°, but is not limited thereto. The sidewalls and bottom of the silicon dioxide layer 22 have a second tilt angle θ2, which is 60° to 75°, exemplarily 62°, 64°, 68°, 70°, or 72°, but is not limited thereto. The patterned structure 2 has relatively smooth sidewalls, allowing for a smooth upward transition when the epitaxial structure grows to this point, reducing epitaxial defects, improving crystal quality, reducing leakage channels in the LED chip, and improving antistatic capabilities.

[0024] like Figure 2 As shown, in a preferred embodiment, in each patterned structure 2, the bottom edge of the silicon dioxide layer 22 and the top edge of the sapphire base 21 are at a predetermined distance L2. The ratio of the predetermined distance L2 to the bottom dimension D1 of the sapphire base 21 is 1:(150-300), exemplarily 1:180, 1:200, 1:220, 1:240, or 1:280, but not limited thereto. Increasing the number of light-reflecting surfaces can enhance light scattering, allowing light emitted from the active layer to be reflected after passing through the substrate, thus increasing the probability of light emission. Specifically, the shape of the silicon dioxide layer 22 can be one or more of the following: frustum-like, pyramidal, conical, or pyramidal.

[0025] like Figure 3As shown, in a preferred embodiment, the sidewalls of the silicon dioxide layer 22 are convex arc surfaces. Compared to a silicon dioxide layer 22 with planar sidewalls, growing epitaxial structures on a silicon dioxide layer 22 with convex arc surfaces allows for better lateral epitaxial growth, further reducing the dislocation density and stress of the GaN epitaxial structure and improving the crystal quality of the epitaxial material. Simultaneously, the convex arc surface further enhances the reflection, diffraction, and scattering of light generated in the LED active region, further improving the LED's light extraction efficiency. The convex height of the sidewalls has a significant impact on the light extraction efficiency. In one embodiment, the convex height R1 of the sidewalls of the silicon dioxide layer 22 is 20nm to 180nm, exemplarily 30nm, 50nm, 100nm, 120nm, or 150nm, but is not limited to these values. The convex height R1 of the sidewalls is the distance between the tangent of the sidewall arc and the sidewall itself. By setting an appropriate height for the protrusions on the sidewalls, a suitable scattering effect can be achieved on the output light of the LED active area, improving the effective scattering area of ​​the microstructure for the emitted light, reducing total internal reflection of the emitted light, and obtaining a better light output effect.

[0026] The height, bottom and top surface dimensions, shape, and position of the patterned structure 2 can all be controlled by appropriately adjusting the etching conditions and mask of the photolithography process. In one embodiment, the patterned sapphire composite substrate disclosed in this utility model embodiment is prepared by the following method:

[0027] S1. Deposit a silicon dioxide thin film on a sapphire substrate.

[0028] Specifically, the sapphire substrate is placed in a PECVD apparatus with a chamber pressure of 1500 Pa to 3000 Pa, an RF power of 500 W to 2000 W, and a chamber temperature of 250 °C to 350 °C. SiH4, N2O, and N2 are introduced, with SiH4 gas purity of 100% and a SiH4:N2O ratio of 1:25 to 1:60. The SiH4 and N2O gases undergo a glow discharge to form plasma, depositing a 1.5 μm to 3.0 μm SiO2 thin film.

[0029] S2. A photoresist layer is formed on a silicon dioxide thin film.

[0030] Specifically, a spin coater is used to coat the photoresist at a spin speed of 2000 r / min to 3500 r / min, a photoresist layer thickness of 1.5 μm to 2.5 μm, a photoresist viscosity of 16 CP to 46 CP, a baking temperature of 80℃ to 140℃, and a baking time of 60 s to 100 s.

[0031] S3, Forming a photoresist mask.

[0032] In one embodiment, the photoresist mask is formed using the following method:

[0033] S31. Expose and develop the substrate with photoresist.

[0034] Specifically, a photolithography machine is used to expose a substrate containing photoresist. After exposure, the substrate is developed with a developer for 30 to 70 seconds. After development, a cylindrical photoresist mask pattern is formed, with a pattern period of 2.9 μm to 3.2 μm, a diameter of 1.8 μm to 2.5 μm, and a height of 1.5 μm to 3 μm.

[0035] In one embodiment, the photoresist mask is formed using the following method:

[0036] S32. Perform nanoimprinting on the substrate with photoresist.

[0037] Specifically, a photoresist is processed using an imprinting machine to imprint cylindrical photoresist mask patterns with a period of 2.9μm–3.2μm, a diameter of 1.8μm–2.5μm, and a height of 1.5μm–3μm. A frustum-shaped photoresist mask pattern is also imprinted with a period of 2.9μm–3.2μm, an upper base width of 1.7μm–2.1μm, a lower base width of 1.8μm–2.5μm, and a height of 1.5μm–3μm.

[0038] S4. Etch the sapphire substrate with the photoresist mask formed.

[0039] Specifically, the sapphire substrate, after photolithography, is etched in segments in an etching machine.

[0040] S41. Perform the first stage etching. The etching gases for the first stage etching are BCl3 and N2. The parameters for the first stage etching are: BCl3 flow rate of 80 sccm to 130 sccm, N2 flow rate of 7 sccm to 17 sccm, pressure of 2 mTorr to 4 mTorr, upper RF power of 1000 W to 2300 W, lower RF power of 600 W to 800 W, and etching time of 3 min to 10 min. Vertical etching yields a patterned silicon dioxide layer.

[0041] S42. Perform the second stage etching. The etching gas for the second stage etching is BCl3. The parameters for the second stage etching are: BCl3 gas flow rate of 80 sccm to 130 sccm, pressure of 2 mTorr to 4 mTorr, upper RF power of 1000 W to 2000 W, lower RF power of 300 W to 800 W, and etching time of 8 min to 18 min, to obtain the sapphire substrate.

[0042] This utility model also discloses an LED epitaxial wafer, including the above-mentioned patterned sapphire composite substrate and an epitaxial structure stacked on the patterned sapphire composite substrate.

[0043] The above description is the preferred embodiment of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications are also considered to be within the protection scope of this utility model.

Claims

1. A patterned sapphire composite substrate, characterized in that, The invention includes a sapphire substrate and multiple patterned structures distributed on the sapphire substrate; each patterned structure includes a sapphire base and a silicon dioxide layer stacked on the sapphire base, wherein the top dimension of the sapphire base is greater than or equal to the bottom dimension of the silicon dioxide layer, and the height of each patterned structure is 0.8 μm to 2 μm, wherein the ratio of the height of the silicon dioxide layer to the height of the sapphire base is 1:(0.06 to 0.18).

2. The patterned sapphire composite substrate as described in claim 1, characterized in that, The ratio of the height of the silicon dioxide layer to the height of the sapphire base is 1:(0.08~0.14).

3. The patterned sapphire composite substrate as described in claim 1, characterized in that, The bottom dimension of the sapphire base is 2.5μm to 3.5μm, and the bottom distance between two adjacent sapphire bases is 0.2μm to 0.5μm.

4. The patterned sapphire composite substrate as described in claim 1, characterized in that, The sidewall of the sapphire base and the bottom of the sapphire base have a first tilt angle of 70° to 85°.

5. The patterned sapphire composite substrate as described in claim 1, characterized in that, In each of the patterned structures, the bottom edge of the silicon dioxide layer is at a predetermined distance from the top edge of the sapphire base, and the ratio of the predetermined distance to the bottom dimension of the sapphire base is 1:(150~300).

6. The patterned sapphire composite substrate as described in claim 1, characterized in that, The sidewalls of the silicon dioxide layer and the bottom of the silicon dioxide layer have a second tilt angle of 60° to 75°.

7. The patterned sapphire composite substrate as described in claim 1, characterized in that, The sidewall of the silicon dioxide layer is a convex arc surface, and the convex height of the sidewall of the silicon dioxide layer is 20nm to 180nm.

8. The patterned sapphire composite substrate as described in claim 1, characterized in that, The sapphire base is shaped like a frustum or a pyramid; the silicon dioxide layer is shaped like one or more of the following: frustum, pyramid, cone, and pyramid.

9. The patterned sapphire composite substrate as described in claim 1, characterized in that, The patterned structure is distributed on the sapphire substrate in one of the following ways: rectangular array arrangement, hexagonal close-packed arrangement, non-periodic quasi-crystal arrangement, or random arrangement.

10. An LED epitaxial wafer, characterized in that, It includes the patterned sapphire composite substrate as described in any one of claims 1 to 9, and the epitaxial structure stacked on the patterned sapphire composite substrate.

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