Ultrasonic signal peak value measuring and adjusting circuit

By employing circuit combinations such as a reference voltage generation circuit in the ultrasonic water meter, the gain is dynamically adjusted to stabilize the signal amplitude, solving the problem of inaccurate measurement in traditional ultrasonic water meters under complex working conditions, and achieving low-cost, high-reliability flow measurement.

CN223954958UActive Publication Date: 2026-02-27WEIHAI BOYANG ELECTRONICS
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Patent Information

Application Number
CN202520740925.3
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-04-18
Publication Date
2026-02-27
Estimated Expiration
2035-04-18

AI Technical Summary

Technical Problem

Traditional ultrasonic water meters are difficult to adapt to changes in the amplitude of ultrasonic echo signals under complex operating conditions, resulting in inaccurate flow measurement and poor long-term stability, and existing products are also expensive.

Method used

The system employs a reference voltage generation circuit, an adjustable gain amplification circuit, an ultrasonic signal positive and negative half-cycle judgment circuit, a signal follower circuit, a fast charging circuit, and a voltage discharge circuit. It uses a low-cost microcontroller to achieve peak measurement and adjustment of ultrasonic signals, dynamically adjusts the gain to stabilize the signal amplitude, and avoids the use of expensive high-speed ADC acquisition chips.

Benefits of technology

It improves the accuracy and reliability of flow measurement, reduces circuit costs, and ensures the long-term stable operation of ultrasonic water meters.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model relates to the technical field of ultrasonic flow measurement, in particular to an ultrasonic flow measuring device which can convert peak voltage of a high-frequency ultrasonic echo signal into a low-frequency voltage signal, achieve self-adaptive adjustment of the ultrasonic echo signal, ensure that the amplitude of the ultrasonic echo signal is stable and the signal is not distorted, and improve the measuring accuracy. According to the ultrasonic signal peak value measuring and adjusting circuit, the accuracy and reliability of flow measurement are improved, and long-term stable operation of an ultrasonic water meter is ensured. The device is provided with a reference voltage generation circuit, an adjustable gain amplification circuit, an ultrasonic signal positive and negative half-cycle judgment circuit, an ultrasonic signal positive and negative half-cycle selection circuit, a signal follower circuit, a rapid charging circuit, a voltage discharge circuit and a single-chip microcomputer. The ultrasonic water meter has the advantages of being low in cost, reasonable in structure, stable in ultrasonic echo signal amplitude, free of signal distortion, capable of improving accuracy and reliability of flow measurement, capable of guaranteeing long-term stable operation and the like.
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Description

TECHNICAL FIELD

[0001] The utility model relates to ultrasonic flow measurement technical field especially relates to a kind of peak voltage of high-frequency ultrasonic echo signal can be converted into low-frequency voltage signal, realize the self-adapting adjustment of ultrasonic echo signal, ensure that ultrasonic echo signal amplitude is stable, signal is not distorted, to improve the accuracy and reliability of flow measurement, to ensure the long-term stable operation of ultrasonic water meter of ultrasonic signal peak measurement and adjusting circuit. BACKGROUND

[0002] Ultrasonic water meter uses time difference method principle, measures the difference between the time of ultrasonic signal propagation in water downstream and upstream to measure flow, with high accuracy, large range ratio, small pressure loss, no moving parts and other advantages.Ultrasonic signal processing is the core technology of ultrasonic water meter, when ultrasonic echo signal exceeds threshold, zero-crossing detection is carried out on echo signal, so as to measure the propagation time of ultrasonic signal.In the use process of ultrasonic water meter, various factors will cause the change of ultrasonic echo signal amplitude, for example: the content of gas bubble or suspended particle in water, sensor surface scale, sensor aging, fluid flow rate change, battery voltage drop, etc.If the amplitude of ultrasonic echo signal changes, the zero-crossing point of echo signal will change, thereby affecting the accuracy of time measurement, even appearing skip wave phenomenon, leading to measurement failure.

[0003] The processing of ultrasonic echo signal in traditional method is relatively simple, generally using no gain original signal or fixed gain signal, which is difficult to adapt to the change of ultrasonic echo signal amplitude caused by complex working conditions, and cannot guarantee the accuracy and long-term stable operation of ultrasonic water meter flow measurement.In addition, existing products in the same field often need high-priced high-speed ADC acquisition chip to realize data acquisition, resulting in high product cost. SUMMARY

[0004] In view of the deficiencies of traditional method, the utility model provides an ultrasonic signal peak measurement and adjusting circuit to solve the problems in the background art.

[0005] The technical scheme adopted by the utility model is:

[0006] The utility model discloses an ultrasonic signal peak value measurement and regulation circuit, its characterized in that, be equipped with reference voltage generation circuit, adjustable gain amplifier circuit, ultrasonic signal positive and negative half cycle judgment circuit, ultrasonic signal positive and negative half cycle selection circuit, signal follower circuit, fast charging circuit, voltage bleeder circuit and singlechip, wherein the signal output end of reference voltage generation circuit sends reference voltage signal into adjustable gain amplifier circuit, ultrasonic signal positive and negative half cycle selection circuit respectively, adjustable gain amplifier circuit, ultrasonic signal positive and negative half cycle judgment circuit, ultrasonic signal positive and negative half cycle selection circuit, signal follower circuit, fast charging circuit, voltage bleeder circuit are connected in proper order, and singlechip is connected with adjustable gain amplifier circuit, fast charging circuit and voltage bleeder circuit.

[0007] In the utility model, the ultrasonic echo signal is sent into the signal input end of adjustable gain amplifier circuit, and the signal after the processing of adjustable gain amplifier circuit is sent into ultrasonic signal positive and negative half cycle judgment circuit, and the ultrasonic signal positive and negative half cycle judgment circuit outputs the ultrasonic signal positive and negative half cycle judgment result to ultrasonic signal positive and negative half cycle selection circuit, and the ultrasonic signal positive and negative half cycle selection circuit outputs the positive half cycle waveform signal of ultrasonic signal, and under the action of signal follower circuit, drives fast charging circuit to output the peak voltage of ultrasonic signal, and the singlechip with built-in A / D converter reads the peak voltage output by fast charging circuit to complete sampling.

[0008] The reference voltage generation circuit includes resistance R2, resistance R3 and capacitor C2, wherein one end of resistance R2 is connected with one end of resistance R3, one end of capacitor C2, the same phase input end of operational amplifier U1A and the 3rd pin (analog switch B1 end) of analog switch U4, the other end of resistance R2 is connected with +3.3V power supply, the other end of resistance R3 is connected with GND, the other end of capacitor C2 is connected with GND, the output voltage VREF+ of reference voltage generation circuit 1 is 1.65V, which is used as the signal reference voltage of adjustable gain amplifier circuit and the reference voltage of ultrasonic signal negative half cycle.

[0009] The adjustable gain amplification circuit adopts low-power high-bandwidth operational amplifier U1 and digital potentiometer U2, the digital potentiometer U2 has SPI serial interface, the single-chip microcomputer 8 controls the output resistance of the digital potentiometer U2 through the SPI interface, and then adjusts the signal gain, the signal gain adjustment range is 1-11, the model of U1 can select MAX4453, and the model of U2 can select MCP41010; further, the adjustable gain amplification circuit 2 includes operational amplifier U1A, digital potentiometer U2, resistance R1, resistance R4, capacitor C1, capacitor C3 and capacitor C4, wherein one end of the capacitor C1 is connected with an input ultrasonic echo signal SIGNAL, the other end of the capacitor C1 is connected with one end of the resistance R1, the same phase input end of the operational amplifier U1A is connected with one end of the resistance R2, one end of the resistance R3, one end of the capacitor C2 and the 3rd pin (analog switch B1 end) of the analog switch U4, the opposite phase input end of the operational amplifier U1A is connected with the other end of the resistance R1 and the 7th pin (potentiometer B end) of the digital potentiometer U2, the output end of the operational amplifier U1A is connected with one end of the resistance R4, one end of the resistance R5, one end of the resistance R6 and the 1st pin (analog switch B2 end) of the analog switch U4, the positive power supply end of the operational amplifier U1A is connected with +3.3V power supply and one end of the capacitor C3, the other end of the capacitor C3 is connected with GND, the negative power supply end of the operational amplifier U1A is connected with GND, the other end of the resistance R4 is connected with the 5th pin (potentiometer A end) of the digital potentiometer U2 and the 6th pin (potentiometer W end) of the digital potentiometer U2, the 1st pin (chip selection CS end) of the digital potentiometer U2 is connected with the signal CPU-CS of the single-chip microcomputer 8, the 2nd pin (serial clock SCK end) of the digital potentiometer U2 is connected with the signal CPU-SCK of the single-chip microcomputer 8, the 3rd pin (serial data SI end) of the digital potentiometer U2 is connected with the signal CPU-SI of the single-chip microcomputer 8, the 8th pin of the digital potentiometer U2 is connected with +3.3V power supply and one end of the capacitor C4, the 4th pin of the digital potentiometer U2 is connected with GND, and the other end of the capacitor C4 is connected with GND.

[0010] The utility model discloses a ultrasonic signal positive and negative half cycle judgment circuit adopts low -power consumption high -speed comparator U3, and the comparator U3 exports high level signal when ultrasonic signal positive half cycle, and the comparator U3 exports low level signal when ultrasonic signal negative half cycle, further, the ultrasonic signal positive and negative half cycle judgment circuit 3 includes comparator U3, resistance R5, resistance R6, electric capacity C5, electric capacity C6, wherein the comparator U3 same phase input end connects resistance R5 other end, and the comparator U3 opposite phase input end connects resistance R6 other end, electric capacity C5 one end, and electric capacity C5 other end connects GND, and the comparator U3 output end connects analog switch U4 6th pin (control input S end), and the comparator U3 positive power supply end connects + 3.3V power supply, electric capacity C6 one end, and electric capacity C6 other end connects GND, and the comparator U3 negative power supply end connects GND, and resistance R5 one end connects resistance R6 one end, resistance R4 one end, operational amplifier U1A output end, analog switch U4 1st pin (analog switch B2 end).

[0011] The utility model discloses a ultrasonic signal positive and negative half cycle selection circuit 4 adopts SPDT analog switch U4, and the comparator U3 output end controls analog switch U4 to select different signal source, and analog switch U4 exports the positive half cycle waveform of ultrasonic signal, wherein U3 model can be MAX987, and U4's model can be 74LVC1G3157, further, the ultrasonic signal positive and negative half cycle selection circuit 4 includes analog switch U4, electric capacity C7, wherein analog switch U4 4th pin (analog switch A end) connects operational amplifier U1B same phase input end, and analog switch U4 3rd pin (analog switch B1 end) connects operational amplifier U1A same phase input end, resistance R2 one end, resistance R3 one end, electric capacity C2 one end, and analog switch U4 1st pin (analog switch B2 end) connects operational amplifier U1A output end, resistance R4 one end, resistance R5 one end, resistance R6 one end, and analog switch U4 6th pin (control input S end) connects comparator U3 output end, and analog switch U4 5th pin connects + 3.3V power supply, electric capacity C7 one end, and electric capacity C7 other end connects GND, and analog switch U4 2nd pin connects GND.

[0012] The utility model discloses a signal follower circuit includes operational amplifier U1B, wherein operational amplifier U1B same phase input end connects analog switch U4 4th pin (analog switch A end), and operational amplifier U1B opposite phase input end connects operational amplifier U1B output end, triode Q1 base.

[0013] The utility model discloses a quick charging circuit including triode Q1, triode Q2, resistance R7, resistance R8, resistance R9, resistance R10, electric capacity C8, electric capacity C9, wherein triode Q1 base connects operational amplifier U1B reverse phase input end, operational amplifier U1B output end, triode Q1 collector connects triode Q2 base, resistance R8 one end, triode Q1 emitter connects resistance R9 one end, electric capacity C9 one end, triode Q2 collector, resistance R10 one end, resistance R11 one end, triode Q2 emitter connects resistance R7 one end, resistance R8 other end, electric capacity C8 one end, resistance R7 other end connects + 3.3V power supply, electric capacity C8 other end connects GND, resistance R9 other end connects GND, electric capacity C9 other end connects GND, resistance R10 other end connects singlechip 8 signal CPU-ADC, quick charging circuit 6 adopts the signal follower circuit that operational amplifier U1B constitutes, and NPN triode Q1 and PNP triode Q2 constitute compound triode amplifier, and the positive half cycle of ultrasonic signal is driven compound triode amplifier to electric capacity C9 quick charging through signal follower, obtains ultrasonic signal peak voltage, and singlechip 8 of built-in A / D converter reads peak voltage through signal CPU-ADC.

[0014] The utility model discloses a voltage discharge circuit adopts N channel MOSFET tube Q3 as the controller, realizes the big current quick discharge of peak value maintaining voltage through singlechip signal CPU-CLR, further, voltage discharge circuit 7 includes resistance R11, MOSFET tube Q3, wherein resistance R11 one end connects triode Q1 emitter, triode Q2 collector, resistance R9 one end, electric capacity C9 one end, resistance R10 one end, resistance R11 other end connects MOSFET tube Q3 drain, MOSFET tube Q3 source connects GND, MOSFET tube Q3 grid connects singlechip 8 signal CPU-CLR.

[0015] The utility model converts the peak voltage of high frequency ultrasonic echo signal into low frequency voltage signal, can realize ultrasonic signal peak value measurement with low cost singlechip, reduces the requirement to device performance, avoids using high price high speed ADC collection chip, reduces the cost of whole circuit, realizes the self -adaptation adjustment of ultrasonic echo signal through the gain of digital potentiometer to the dynamic adjustment operational amplifier, guarantees ultrasonic echo signal amplitude stability, signal is not distorted, thereby improves the accuracy and reliability of flow measurement, and further ensures the long -term stable operation of ultrasonic water meter. ACCURACY

[0016] ATTACH Figure 1 It is the structure diagram of the utility model.

[0017] ATTACH Figure 2 It is an embodiment circuit principle diagram of the utility model.

[0018] Reference voltage generating circuit 1, adjustable gain amplifier circuit 2, ultrasonic signal positive and negative half cycle judgment circuit 3, ultrasonic signal positive and negative half cycle selection circuit 4, signal follower circuit 5, fast charging circuit 6, voltage discharge circuit 7, single-chip microcomputer 8. DETAILED DESCRIPTION

[0019] The utility model will be further explained in connection with the drawings and examples.

[0020] As shown in the accompanying Figure 1 The utility model discloses an ultrasonic signal peak value measurement and regulation circuit, is equipped with reference voltage generating circuit 1, adjustable gain amplifier circuit 2, ultrasonic signal positive and negative half cycle judgment circuit 3, ultrasonic signal positive and negative half cycle selection circuit 4, signal follower circuit 5, fast charging circuit 6, voltage discharge circuit 7 and single-chip microcomputer 8, wherein the signal output end of reference voltage generating circuit 1 sends reference voltage signal into adjustable gain amplifier circuit 2, ultrasonic signal positive and negative half cycle selection circuit 4 respectively, adjustable gain amplifier circuit 2, ultrasonic signal positive and negative half cycle judgment circuit 3, ultrasonic signal positive and negative half cycle selection circuit 4, signal follower circuit 5, fast charging circuit 6, voltage discharge circuit 7 are connected in proper order, and single-chip microcomputer 8 is connected with adjustable gain amplifier circuit 2, fast charging circuit 6 and voltage discharge circuit 7.

[0021] In the utility model, the ultrasonic echo signal is sent into the signal input end of adjustable gain amplifier circuit 2, and the signal handled after adjustable gain amplifier circuit 2 is sent into ultrasonic signal positive and negative half cycle judgment circuit 3, and ultrasonic signal positive and negative half cycle judgment circuit 3 exports ultrasonic signal positive and negative half cycle judgment result to ultrasonic signal positive and negative half cycle selection circuit 4, and ultrasonic signal positive and negative half cycle selection circuit 4 exports the positive half cycle waveform signal of ultrasonic signal, and under the action of signal follower circuit 5, drives fast charging circuit 6 to export ultrasonic signal peak voltage, and single-chip microcomputer 8 with built-in A / D converter reads the peak voltage exported by fast charging circuit 6 to complete sampling.

[0022] The output voltage VREF+ of reference voltage generating circuit 1 in the utility model is 1.65V, which is used as the signal reference voltage of adjustable gain amplifier circuit 2 and simultaneously as the reference voltage of ultrasonic signal negative half cycle.

[0023] Adjustable gain amplifier circuit 2 in the utility model adopts low-power high-bandwidth operational amplifier U1 and digital potentiometer U2, digital potentiometer U2 has SPI serial interface, and single-chip microcomputer 8 controls the output resistance of digital potentiometer U2 through SPI interface, and then adjusts signal gain, and the signal gain adjustment range is 1~11, and the model of U1 can select MAX4453, and the model of U2 can select MCP41010.

[0024] The ultrasonic signal positive and negative half cycle judgment circuit 3 adopts a low-power high-speed comparator U3, the comparator U3 outputs a high-level signal when the ultrasonic signal positive half cycle, and outputs a low-level signal when the ultrasonic signal negative half cycle.

[0025] The ultrasonic signal positive and negative half cycle selection circuit 4 adopts a SPDT analog switch U4, the comparator U3 output end controls the analog switch U4 to select different signal sources, and the analog switch U4 outputs the positive half cycle waveform of the ultrasonic signal, wherein the model number of the comparator U3 can be MAX987, and the model number of the analog switch U4 can be 74LVC1G3157.

[0026] The signal follower circuit 5 includes an operational amplifier U1B, wherein the operational amplifier U1B is connected with the fourth pin (analog switch A end) of the analog switch U4 at the same phase input end, and is connected with the output end of the operational amplifier U1B and the base of the triode Q1 at the inverse phase input end.

[0027] The fast charging circuit 6 is formed by the operational amplifier U1B, and the NPN triode Q1 and the PNP triode Q2 form a composite triode amplifier, the positive half cycle waveform of the ultrasonic signal is driven by the signal follower circuit 5 to charge the capacitor C9 quickly, the peak voltage of the ultrasonic signal is obtained, and the single-chip microcomputer 8 with a built-in A / D converter reads the peak voltage through the signal CPU-ADC.

[0028] The voltage discharge circuit 7 adopts an N-channel MOSFET tube Q3 as a control device, and realizes the large-current fast discharge of the peak holding voltage through the signal CPU-CLR of the single-chip microcomputer 8. Embodiment

[0029] As shown in the accompanying drawings, Figure 2 The ultrasonic signal peak value measurement and adjustment circuit is provided with a reference voltage generation circuit 1, an adjustable gain amplification circuit 2, an ultrasonic signal positive and negative half cycle judgment circuit 3, an ultrasonic signal positive and negative half cycle selection circuit 4, a signal follower circuit 5, a fast charging circuit 6, a voltage discharge circuit 7 and a single-chip microcomputer 8, wherein each functional circuit adopts the following circuit structure:

[0030] The reference voltage generation circuit 1 includes a resistor R2, a resistor R3 and a capacitor C2, wherein one end of the resistor R2 is connected with one end of the resistor R3, one end of the capacitor C2, the same phase input end of the operational amplifier U1A and the third pin (analog switch B1 end) of the analog switch U4, the other end of the resistor R2 is connected with a +3.3V power supply, the other end of the resistor R3 is connected with GND, and the other end of the capacitor C2 is connected with GND.

[0031] The adjustable gain amplifier circuit 2 includes operational amplifier U1A, digital potentiometer U2, resistor R1, resistor R4, capacitor C1, capacitor C3, capacitor C4, wherein one end of capacitor C1 is connected to input ultrasonic echo signal SIGNAL, the other end of capacitor C1 is connected to one end of resistor R1, the same phase input end of operational amplifier U1A is connected to one end of resistor R2, one end of resistor R3, one end of capacitor C2, the 3rd pin of analog switch U4 (analog switch B1 end), the inverse input end of operational amplifier U1A is connected to the other end of resistor R1, the 7th pin of digital potentiometer U2 (potentiometer B end), the output end of operational amplifier U1A is connected to one end of resistor R4, one end of resistor R5, one end of resistor R6, the 1st pin of analog switch U4 (analog switch B2 end), the positive power supply end of operational amplifier U1A is connected to +3.3V power supply, one end of capacitor C3, the other end of capacitor C3 is connected to GND, the negative power supply end of operational amplifier U1A is connected to GND, the other end of resistor R4 is connected to the 5th pin of digital potentiometer U2 (potentiometer A end), the 6th pin of digital potentiometer U2 (potentiometer W end), the 1st pin of digital potentiometer U2 (chip selection CS end) is connected to single-chip microcomputer 8 signal CPU-CS, the 2nd pin of digital potentiometer U2 (serial clock SCK end) is connected to single-chip microcomputer 8 signal CPU-SCK, the 3rd pin of digital potentiometer U2 (serial data SI end) is connected to single-chip microcomputer 8 signal CPU-SI, the 8th pin of digital potentiometer U2 is connected to +3.3V power supply, one end of capacitor C4, the 4th pin of digital potentiometer U2 is connected to GND, the other end of capacitor C4 is connected to GND;

[0032] The ultrasonic signal positive and negative half cycle judgment circuit 3 includes comparator U3, resistor R5, resistor R6, capacitor C5, capacitor C6, wherein the same phase input end of comparator U3 is connected to the other end of resistor R5, the inverse input end of comparator U3 is connected to the other end of resistor R6, one end of capacitor C5, the other end of capacitor C5 is connected to GND, the output end of comparator U3 is connected to the 6th pin of analog switch U4 (control input S end), the positive power supply end of comparator U3 is connected to +3.3V power supply, one end of capacitor C6, the other end of capacitor C6 is connected to GND, the negative power supply end of comparator U3 is connected to GND, one end of resistor R5 is connected to one end of resistor R6, one end of resistor R4, the output end of operational amplifier U1A, the 1st pin of analog switch U4 (analog switch B2 end);

[0033] The ultrasonic signal positive and negative half cycle selection circuit 4 includes analog switch U4, capacitor C7, wherein the fourth pin (analog switch A end) of analog switch U4 is connected to the non-inverting input terminal of operational amplifier U1B, the third pin (analog switch B1 end) of analog switch U4 is connected to the non-inverting input terminal of operational amplifier U1A, one end of resistor R2, one end of resistor R3, one end of capacitor C2, the first pin (analog switch B2 end) of analog switch U4 is connected to the output terminal of operational amplifier U1A, one end of resistor R4, one end of resistor R5, one end of resistor R6, the sixth pin (control input S end) of analog switch U4 is connected to the output terminal of comparator U3, the fifth pin of analog switch U4 is connected to +3.3V power supply and one end of capacitor C7, the other end of capacitor C7 is connected to GND, and the second pin of analog switch U4 is connected to GND;

[0034] The signal follower circuit 5 includes operational amplifier U1B, wherein the non-inverting input terminal of operational amplifier U1B is connected to the fourth pin (analog switch A end) of analog switch U4, and the inverting input terminal of operational amplifier U1B is connected to the output terminal of operational amplifier U1B and the base of triode Q1.

[0035] The fast charging circuit 6 includes triode Q1, triode Q2, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C8 and capacitor C9, wherein the base of triode Q1 is connected to the inverting input terminal of operational amplifier U1B and the output terminal of operational amplifier U1B, the collector of triode Q1 is connected to the base of triode Q2 and one end of resistor R8, the emitter of triode Q1 is connected to one end of resistor R9, one end of capacitor C9, the collector of triode Q2, one end of resistor R10 and one end of resistor R11, the emitter of triode Q2 is connected to one end of resistor R7, the other end of resistor R8 and one end of capacitor C8, the other end of resistor R7 is connected to +3.3V power supply, the other end of capacitor C8 is connected to GND, the other end of resistor R9 is connected to GND, the other end of capacitor C9 is connected to GND, and the other end of resistor R10 is connected to the signal CPU-ADC of single-chip microcomputer 8.

[0036] The voltage discharge circuit 7 includes resistor R11 and MOSFET tube Q3, wherein one end of resistor R11 is connected to the emitter of triode Q1, the collector of triode Q2, one end of resistor R9, one end of capacitor C9 and one end of resistor R10, the other end of resistor R11 is connected to the drain of MOSFET tube Q3, the source of MOSFET tube Q3 is connected to GND, and the gate of MOSFET tube Q3 is connected to the signal CPU-CLR of single-chip microcomputer 8.

[0037] During operation, the ultrasonic echo signal SIGNAL enters the adjustable gain amplification circuit composed of the operational amplifier U1A and the digital potentiometer U2 through the coupling capacitor C1, the signal reference voltage VREF+ of the operational amplifier U1A is 1.65V, the digital potentiometer U2 has an SPI serial interface, the single-chip microcomputer 8 controls the output resistance of the digital potentiometer U2 through the SPI interface, thereby adjusting the signal gain, realizing the adaptive adjustment of the ultrasonic echo signal, ensuring the stability of the ultrasonic echo signal amplitude, the comparator U3 is used for judging the positive and negative half cycles of the ultrasonic signal, the output signal of the comparator U3 controls the SPDT analog switch U4 to select different signal sources, the analog switch U4 outputs the positive half cycle waveform of the ultrasonic signal, the operational amplifier U1B constitutes a signal follower, the NPN transistor Q1 and the PNP transistor Q2 constitute a composite transistor amplifier, the positive half cycle waveform of the ultrasonic signal drives the composite transistor amplifier to rapidly charge the capacitor C9 through the signal follower, the peak voltage of the ultrasonic signal is obtained, the single-chip microcomputer 8 with a built-in A / D converter reads the peak voltage through the signal CPU-ADC, after sampling is completed, the single-chip microcomputer 8 controls the N-channel MOSFET Q3 to realize the rapid discharge of the peak voltage through the signal CPU-CLR.

[0038] Compared with the prior art, the ultrasonic signal peak value measurement can be realized by using a low-cost single-chip microcomputer, the requirement for the performance of the device is reduced, the use of high-price high-speed ADC acquisition chips is avoided, the cost of the entire circuit is reduced, the gain of the operational amplifier is dynamically adjusted through the digital potentiometer, the adaptive adjustment of the ultrasonic echo signal is realized, the stability of the ultrasonic echo signal amplitude is ensured, the signal is not distorted, the accuracy and reliability of the flow measurement are improved, and the long-term stable operation of the ultrasonic water meter is ensured.

Claims

1. An ultrasonic signal peak measurement and conditioning circuit, comprising: The reference voltage generating circuit 1, the adjustable gain amplification circuit, the ultrasonic signal positive and negative half cycle judgment circuit, the ultrasonic signal positive and negative half cycle selection circuit, the signal follower circuit, the fast charging circuit, the voltage discharge circuit and the single-chip microcomputer are provided, wherein the signal output end of the reference voltage generating circuit sends the reference voltage signals into the adjustable gain amplification circuit and the ultrasonic signal positive and negative half cycle selection circuit, the adjustable gain amplification circuit, the ultrasonic signal positive and negative half cycle judgment circuit, the ultrasonic signal positive and negative half cycle selection circuit, the signal follower circuit, the fast charging circuit and the voltage discharge circuit are sequentially connected, and the single-chip microcomputer is connected with the adjustable gain amplification circuit, the fast charging circuit and the voltage discharge circuit.

2. An ultrasonic signal peak measuring and regulating circuit according to claim 1, wherein, The ultrasonic echo signal is sent into the signal input end of the adjustable gain amplification circuit, the signal processed by the adjustable gain amplification circuit is sent into the ultrasonic signal positive and negative half cycle judgment circuit, the ultrasonic signal positive and negative half cycle judgment circuit outputs the ultrasonic signal positive and negative half cycle judgment result to the ultrasonic signal positive and negative half cycle selection circuit, the ultrasonic signal positive and negative half cycle selection circuit outputs the positive half cycle waveform signal of the ultrasonic signal, and under the action of the signal follower circuit, the fast charging circuit outputs the peak voltage of the ultrasonic signal, and the single-chip microcomputer with the built-in A / D converter reads the peak voltage output by the fast charging circuit to complete sampling.

3. The ultrasonic signal peak measuring and regulating circuit according to claim 1, wherein, The reference voltage generating circuit comprises a resistor R2, a resistor R3 and a capacitor C2, wherein one end of the resistor R2 is connected with one end of the resistor R3, one end of the capacitor C2, the same-phase input end of an operational amplifier U1A and the third pin of an analog switch U4, the other end of the resistor R2 is connected with a +3.3V power supply, the other end of the resistor R3 is connected with GND, the other end of the capacitor C2 is connected with GND, the output voltage VREF+ of the reference voltage generating circuit 1 is 1.65V, which is used as the signal reference voltage of the adjustable gain amplification circuit and the reference voltage of the negative half cycle of the ultrasonic signal.

4. The ultrasonic signal peak measuring and regulating circuit according to claim 1, wherein, The adjustable gain amplification circuit adopts a low-power high-bandwidth operational amplifier U1 and a digital potentiometer U2, the digital potentiometer U2 has an SPI serial interface, the single-chip microcomputer controls the output resistance of the digital potentiometer U2 through the SPI interface, thereby adjusting the signal gain, and the signal gain adjustment range is 1-11.

5. The ultrasonic signal peak measuring and regulating circuit according to claim 1, wherein, The ultrasonic signal positive and negative half cycle judgment circuit adopts a low-power high-speed comparator U3, the comparator U3 outputs a high-level signal when the ultrasonic signal is in the positive half cycle, and outputs a low-level signal when the ultrasonic signal is in the negative half cycle.

6. An ultrasonic signal peak measuring and regulating circuit according to claim 5, wherein, The ultrasonic signal positive and negative half cycle judgment circuit comprises the comparator U3, a resistor R5, a resistor R6, a capacitor C5 and a capacitor C6, wherein the same-phase input end of the comparator U3 is connected with the other end of the resistor R5, the opposite-phase input end of the comparator U3 is connected with the other end of the resistor R6 and one end of the capacitor C5, the other end of the capacitor C5 is connected with GND, the output end of the comparator U3 is connected with the sixth pin of the analog switch U4, the positive power supply end of the comparator U3 is connected with a +3.3V power supply and one end of the capacitor C6, the other end of the capacitor C6 is connected with GND, the negative power supply end of the comparator U3 is connected with GND, and one end of the resistor R5 is connected with one end of the resistor R6, one end of the resistor R4, the output end of the operational amplifier U1A and the first pin of the analog switch U4.

7. The ultrasonic signal peak measuring and regulating circuit according to claim 5, wherein, The ultrasonic signal positive and negative half cycle selection circuit adopts SPDT analog switch U4, the comparator U3 output end controls analog switch U4 to select different signal sources, and the analog switch U4 outputs the positive half cycle waveform of the ultrasonic signal.

8. The ultrasonic signal peak measuring and regulating circuit according to claim 7, wherein, The signal follower circuit includes operational amplifier U1B, wherein the operational amplifier U1B same phase input end is connected with the fourth pin of analog switch U4, the operational amplifier U1B opposite phase input end is connected with the output end of operational amplifier U1B and the base of triode Q1.

9. The ultrasonic signal peak measuring and regulating circuit according to claim 8, wherein, The fast charging circuit includes triode Q1, triode Q2, resistance R7, resistance R8, resistance R9, resistance R10, capacitor C8 and capacitor C9, wherein the base of triode Q1 is connected with the opposite phase input end of operational amplifier U1B and the output end of operational amplifier U1B, the collector of triode Q1 is connected with the base of triode Q2 and one end of resistance R8, the emitter of triode Q1 is connected with one end of resistance R9, one end of capacitor C9, the collector of triode Q2, one end of resistance R10 and one end of resistance R11, the emitter of triode Q2 is connected with one end of resistance R7, the other end of resistance R8 and one end of capacitor C8, the other end of resistance R7 is connected with +3.3V power supply, the other end of capacitor C8 is connected with GND, the other end of resistance R9 is connected with GND, the other end of capacitor C9 is connected with GND, and the other end of resistance R10 is connected with single-chip microcomputer signal CPU-ADC.

10. The ultrasonic signal peak measuring and regulating circuit according to claim 9, wherein, The voltage discharge circuit includes resistance R11 and MOSFET tube Q3, wherein one end of resistance R11 is connected with the emitter of triode Q1, the collector of triode Q2, one end of resistance R9, one end of capacitor C9 and one end of resistance R10, the other end of resistance R11 is connected with the drain of MOSFET tube Q3, the source of MOSFET tube Q3 is connected with GND, and the gate of MOSFET tube Q3 is connected with single-chip microcomputer signal CPU-CLR.