Chip stacking packaging structure

Abstract

The utility model relates to an electromagnetic shielding packaging structure which comprises a lead frame, the lead frame comprises a pin area, and the pin area comprises a first pin and a second pin which is bent upwards; the first chip and the second chip are stacked above the lead frame, the first chip is electrically connected with the first pin, and the second chip stacked above the first chip is fixed and electrically connected with the second pin; the plastic package structure covers the lead frame, the first chip and the second chip; and the bottom of the chip stacking packaging structure exposes the bottom surface of the first pin and the bottom surface of the second pin. According to the invention, chip stacking packaging is realized based on the first pins and the second pins of different heights of the lead frame, the cost is low, the process is simple, and more packaging unit integration requirements and application scene expansion are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a chip stack packaging structure. BACKGROUND

[0002] With the rapid development of the semiconductor industry, a new chip design method of chiplet technology has emerged, which packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips becomes higher and higher, the number of chips integrated in a single package has increased significantly. The existing 2.5D packaging technology is to package multiple small chips into a packaging structure to improve the packaging integration.

[0003] However, the existing 2.5D packaging is mainly based on packaging on a substrate, and the lead frame has a low interconnection density, so its application in 2.5D packaging is less. Therefore, how to provide a packaging integration based on a lead frame to meet the needs of more packaging unit integration and the expansion of application scenarios is a technical problem to be solved at present. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a chip stack packaging structure based on a lead frame to realize chip stack packaging with low cost.

[0005] To this end, an embodiment of the present application provides a chip stack packaging structure, characterized in that it comprises:

[0006] a lead frame, the lead frame comprising a pin area, the pin area comprising a first pin and a second pin bent upward;

[0007] a first chip and a second chip stacked above the lead frame, wherein the first chip is electrically connected to the first pin, and the second chip stacked above the first chip is fixed to and electrically connected to the second pin;

[0008] a plastic packaging structure covering the lead frame, the first chip and the second chip;

[0009] The bottom of the chip stack packaging structure exposes the bottom surface of the first pin and the bottom surface of the second pin.

[0010] As an optional embodiment, the exposed bottom surface of the first pin serves as an output pin of the first chip, and the exposed bottom surface of the second pin serves as an output pin of the second chip.

[0011] As an optional embodiment, part of the first pin and the second pin are connected, and the bottom surface of the first pin and the bottom surface of the second pin exposed at the bottom of the chip stack package structure are an integral structure, which simultaneously serves as the output pin of the first chip and the second chip.

[0012] As an optional embodiment, the lead frame further comprises an island region, the pin region is located around the island region, the first chip is located on the surface of the island region, and a bonding wire is bonded between the surface of the first chip and the first pin; the functional surface of the second chip stacked above the first chip is fixed and electrically connected to the top of the second pin.

[0013] As an optional embodiment, the bottom surface of the first chip is fixed and electrically connected to the upper surface of the first pin; the functional surface of the second chip stacked above the first chip is fixed and electrically connected to the top of the second pin which is bent upward.

[0014] As an optional embodiment, the pin region comprises a first pin, a second pin bent upward, and a pin region main structure, the pin region main structure is connected to the first pin and the second pin respectively, and the first pin and the second pin are isolated, the first pin and the second pin are located on one side of the pin region main structure close to the island region, when the chip stack package structure is cut to form a discrete chip package structure, the pin region main structure and part of the first pin and part of the second pin are cut off, and the remaining first pin and second pin are independently arranged.

[0015] As an optional embodiment, the second pin is an L-shaped pin comprising a bottom pin portion and a vertical bending portion connected in sequence, the bottom surface of the bottom pin portion is located in the same plane as the bottom surface of the first pin, and the top surface of the vertical bending portion is higher than the bottom pin portion.

[0016] As an optional embodiment, part of the bottom pin portion of the second pin is connected to the first pin adjacent thereto, and the bottom surface of the bottom pin portion and the bottom surface of the first pin are an integral structure, which simultaneously serves as the output pin of the first chip and the second chip.

[0017] As an optional embodiment, the top surface of the vertical bending portion is higher than the height of the bonding wire.

[0018] As an optional embodiment, the partial area of the bottom pin part of the second pin and the partial area of the first pin are located in the corresponding cutting area of the discrete chip package structure, so that the first pin and the second pin of the cut discrete chip package structure are electrically isolated, and the back surface of the discrete chip package structure exposes the bottom surface of the first pin and the bottom surface of the second pin.

[0019] As an optional embodiment, the first pin and the second pin are arranged at intervals.

[0020] As an optional embodiment, the lead frame is formed by a stamping process.

[0021] As an optional embodiment, the second pin is arranged on two sides or four sides of the first chip, and the first pin is arranged on two sides or four sides of the first chip.

[0022] As an optional embodiment, the size of the second chip is greater than the size of the first chip.

[0023] The technical solution of the present application has the following advantages:

[0024] The chip stack package structure disclosed in the present application comprises a lead frame, the lead frame comprises a pin area, the pin area comprises a first pin and a second pin bent upward; a first chip and a second chip are arranged on the lead frame in a stack, wherein the first chip is electrically connected with the first pin, and the second chip arranged on the first chip in a stack is fixed and electrically connected with the second pin; a plastic package structure covers the lead frame, the first chip and the second chip; the bottom of the chip stack package structure exposes the bottom surface of the first pin and the bottom surface of the second pin. The first pin and the second pin of different heights based on the lead frame realize chip stack packaging, which is low in cost, simple in process, and meets the integration demand of more packaging units and the expansion of application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The cross-sectional structure diagram of the chip stack package structure of an embodiment;

[0026] Figure 2 The top view structure diagram of the lead frame of the chip stack package structure of an embodiment;

[0027] Figure 3 The side view structure diagram of the lead frame of Figure 2 ;

[0028] Figure 4 The schematic diagram of the bonding wire on the lead frame of Figure 2 ;

[0029] Figure 5 is a top view structural schematic diagram of a chip stack packaging structure according to an embodiment;

[0030] Figure 6 is a cross-sectional structural schematic diagram of a chip stack packaging structure according to another embodiment. DETAILED DESCRIPTION

[0031] The specific embodiments of the present application will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present application, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples which should not limit the protection scope of the present application herein. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in the actual manufacture.

[0032] The chip stack packaging structure according to the embodiments of the present application is first provided, and the manufacturing direction will be described in detail below with reference to the drawings.

[0033] First, referring to Figures 1-5 , the chip stack packaging structure comprises:

[0034] a lead frame 100, the lead frame 100 comprises a base island region 10 and a pin region around the base island region, the pin region comprises a first pin 20 and a second pin 30 bent upward;

[0035] a first chip 15 and a second chip 55 stacked above the lead frame 100, wherein the first chip 15 is arranged on the upper surface of the base island region 10 and is electrically connected with the first pin 20 through a bonding wire 23, and the second chip 55 stacked above the first chip 15 is fixed and electrically connected with the second pin 30 bent upward;

[0036] a plastic encapsulation structure 50 covering the lead frame 100, the first chip 15 and the second chip 55;

[0037] The bottom of the chip stack packaging structure exposes the bottom surface of the first pin 20 and the bottom surface of the second pin 30, the exposed bottom surface of the first pin 20 serves as the output pin of the first chip 15, and the exposed bottom surface of the second pin 30 serves as the output pin of the second chip 55, which is used for electrically connecting with external circuits.

[0038] Specifically, please refer to Figure 2 and Figure 3 , Figure 2 is a top view structural schematic diagram of a lead frame of a chip stack packaging structure, Figure 3 is a side view structural schematic diagram of the lead frame of Figure 2 ,

[0039] The lead frame 100 comprises a base island region 10 and a pin region located around the base island region, the base island region 10 is connected with the pin region through connecting portions located at four corners, the pin region comprises first pins and upwardly bent second pins, in the embodiment, the pin region is located around the base island region, and the first pins and the second pins are also located around the base island region.

[0040] In other embodiments, the pin region can also be located only on two sides of the base island region, and the first pins and the second pins are also located only on the two sides of the base island region.

[0041] In the embodiment, the first pins and the second pins are arranged in intervals, and the number of the first pins and the second pins can be adjusted as required. For example, one first pin and one second pin are arranged in intervals, or a plurality of first pins and one second pin are arranged in intervals, or a plurality of first pins and a plurality of second pins are arranged in intervals, etc. Since the first pins 20 serve as output pins of the first chip 15 and the second pins 30 serve as output pins of the second chip 55, different numbers of the first pins and the second pins can be arranged according to the number of pins required by the first chip 15 and the second chip 55.

[0042] In other embodiments, the first pins are arranged on both sides of the first direction of the first chip, and the second pins are arranged on both sides of the second direction of the first chip, the first chip is electrically connected to the outside through the first pins on the two sides, and the second chip is electrically connected to the outside through the second pins on the other two sides.

[0043] In the embodiment, the size of the second chip is greater than that of the first chip, and the second chip and the first chip can be a chip or a chip package structure, and the chip package structure can comprise one or more chips.

[0044] In the embodiment, please refer to Figure 2 , the pin region comprises first pins 20, upwardly bent second pins 30 and a pin region main structure 28, the pin region main structure 28 is connected with the first pins 20 and the second pins 30 respectively, the first pins 20 and the second pins 30 are arranged in isolation, and the first pins 20 and the second pins 30 are arranged on one side of the pin region main structure close to the base island region, part of the second pin region and part of the first pin region are located in the cutting region corresponding to the discrete chip package structure, and when the chip stack package structure is cut along the cutting line 27 to form the discrete chip package structure, the pin region main structure and part of the first pins and part of the second pins are cut off, so that the second pins and the first pins of the discrete chip package structure after cutting are electrically isolated, and the bottom surfaces of the first pins and the second pins are exposed on the back of the discrete chip package structure.

[0045] In the present embodiment, please refer to Figure 1 , Figure 4 and Figure 5 , the first chip 15 surface of the base island region 10 surface and the first pin 20 of the lead frame are bonded with a wire 23, and the first pin 20 is partially cut in the subsequent process, and the remaining first pin 20 serves as the output pin of the first chip in the finally formed discrete chip package structure.

[0046] In the present embodiment, please refer to Figure 1 and Figure 3 , the upwardly bent second pin 30 is an L-shaped pin, including a bottom pin portion and a vertical bending portion connected in sequence, the bottom pin portion is connected with the pin region main structure 28, the bottom surface of the bottom pin portion is located in the same plane as the bottom surface of the first pin 20, and the top surface of the vertical bending portion is higher than the bottom pin portion. The top surface of the vertical bending portion is fixed and electrically connected to the functional surface of the second chip 55 through a soldering structure. In the subsequent process, the bottom pin portion of the second pin 30 is partially cut, and the remaining second pin 30 serves as the output pin of the second chip in the finally formed discrete chip package structure. The present application realizes chip stack packaging based on the first pin and the second pin of different heights of the lead frame, has low cost, simple process, and meets the integration demand of more packaging units and the expansion of application scenarios.

[0047] In an embodiment, the bottom pin portion of part of the second pin 30 is connected with the first pin 20 adjacent thereto, and the bottom surface of the bottom pin portion of the second pin 30 and the bottom surface of the first pin 20 are an integral structure, which simultaneously serves as the output pin of the first chip 20 and the second chip 30.

[0048] In the present embodiment, by reasonably controlling the height of the vertical bending portion, the top surface of the vertical bending portion is higher than the height of the wire 23 on the surface of the first chip, so that the first chip and the second chip arranged in stack do not contact.

[0049] In the present embodiment, the lead frame 100 is formed by a metal stamping process, that is, the first pin and the upwardly bent second pin are formed by a stamping process. In other embodiments, the lead frame can also be formed by other suitable processes, such as a metal casting process.

[0050] In an embodiment, the material of the lead frame 100 is copper alloy or iron-nickel alloy. In a specific embodiment, the copper alloy can be copper-iron alloy, copper-nickel-silicon alloy, copper-chromium alloy or copper-nickel-tin alloy. The lead frame 100 has good heat conduction and electrical conductivity, low thermal expansion coefficient, sufficient strength and high deformation resistance.

[0051] In this embodiment, the material of the molding layer 50 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, etc., and the forming process can be injection molding or transfer molding.

[0052] The molding compound 50 covers the lead frame 100, the first chip 15, and the second chip 55. The bottom surface of the first pin 20 and the bottom surface of the second pin 30 are exposed at the bottom of the molding compound 50. The exposed bottom surface of the first pin 20 serves as the output pin of the first chip 15, and the exposed bottom surface of the second pin 30 serves as the output pin of the second chip 55, for electrical connection to external circuits.

[0053] In other embodiments, after the discrete chip package structure is formed by cutting, some adjacent first pins 20 and second pins 30 are still connected. That is, the bottom surface of the first pin 20 and the bottom surface of the second pin 30 exposed at the bottom of the molding layer 50 are an integral structure, which simultaneously serves as the output pins of the first chip 15 and the second chip 55.

[0054] In another embodiment, please refer to Figure 6 The lead frame may include only the pin area, excluding the middle base island area. The pin area includes a first pin 20 and an upwardly bent second pin 30. The bottom surface of the first chip 15 is fixed and electrically connected to the surface of the first pin 20 by a welding structure. The functional surface of the second chip 55, which is stacked on top of the first chip 15, is fixed and electrically connected to the top of the upwardly bent second pin 30 by a welding structure.

[0055] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A chip stack package structure, characterized by, The chip stack package structure comprises: a lead frame, the lead frame comprising a pin area, the pin area comprising a first pin and a second pin bent upward; a first chip and a second chip stacked above the lead frame, wherein the first chip is electrically connected with the first pin, and the second chip stacked above the first chip is fixed and electrically connected with the second pin; a plastic package structure covering the lead frame, the first chip and the second chip; the bottom surface of the exposed first pin and the bottom surface of the exposed second pin are exposed at the bottom of the chip stack package structure.

2. The chip stack package structure of claim 1, wherein, The exposed bottom surface of the first pin serves as the output pin of the first chip, and the exposed bottom surface of the second pin serves as the output pin of the second chip.

3. The chip stack package structure of claim 1, wherein, Part of the first pin and the second pin are connected, and the exposed bottom surface of the first pin and the bottom surface of the second pin at the bottom of the chip stack package structure are an integral structure, which simultaneously serves as the output pin of the first chip and the second chip.

4. The chip stack package structure of claim 1, wherein, The lead frame further comprises an island area, the pin area is located around the island area, the first chip is located on the surface of the island area, and a bonding wire is bonded between the surface of the first chip and the first pin; the functional surface of the second chip stacked above the first chip is fixed and electrically connected with the top of the second pin.

5. The chip stack package structure of claim 1, wherein, The bottom surface of the first chip is fixed and electrically connected with the upper surface of the first pin. The functional surface of the second chip stacked above the first chip is fixed and electrically connected with the top of the second pin bent upward.

6. The chip stack package structure of claim 4, wherein, The pin area comprises a first pin, a second pin bent upward and a pin area main structure, the pin area main structure is connected with the first pin and the second pin respectively, and the first pin and the second pin are isolated, the first pin and the second pin are located on one side of the pin area main structure close to the island area, and when the chip stack package structure is cut to form a discrete chip package structure, the pin area main structure and part of the first pin and part of the second pin are cut off, so that the remaining first pin and second pin are arranged separately.

7. The chip stack package structure of claim 1, wherein, The second pin is an L-shaped pin comprising a bottom pin portion and a vertical bending portion connected in sequence, the bottom surface of the bottom pin portion is located in the same plane as the bottom surface of the first pin, and the top surface of the vertical bending portion is higher than the bottom pin portion.

8. The chip stack package structure of claim 7, wherein, The bottom pin portion of part of the second pin is connected with the adjacent first pin, and the bottom surface of the bottom pin portion and the bottom surface of the first pin are an integral structure.

9. The chip stack package structure of claim 4, wherein, The second pin is an L-shaped pin comprising a bottom pin portion and a vertical bending portion connected in sequence, the bottom surface of the bottom pin portion is located in the same plane as the bottom surface of the first pin, and the top surface of the vertical bending portion is higher than the bottom pin portion, and the top surface of the vertical bending portion is higher than the height of the bonding wire.

10. The chip stack package structure of claim 7, wherein, Part of the bottom pin part of the second pin and part of the first pin are located in the corresponding cutting area of the discrete chip package structure, so that the second pin and the first pin of the discrete chip package structure after cutting are electrically isolated, and the back surface of the discrete chip package structure exposes the bottom surface of the first pin and the bottom surface of the second pin.

11. The chip stack package structure of claim 1, wherein, The first pin and the second pin are arranged in a spaced manner.

12. The chip stack package structure of claim 1, wherein, The lead frame is formed by a stamping process.

13. The chip stack package structure of claim 1, wherein, The second pin is arranged on two sides or four sides of the first chip, and the first pin is arranged on two sides or four sides of the first chip.

14. The chip stack package structure of claim 1, wherein, The size of the second chip is greater than the size of the first chip.

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