GOA circuit, array substrate and display panel

Abstract

The utility model provides a GOA circuit, and an array substrate and a display panel comprising the GOA circuit. The GOA circuit comprises multiple stages of GOA units which are in cascade connection; the clock signal line is used for inputting a clock signal to each GOA unit; the multiple reset voltage lines at least comprise a first reset voltage line (VSS1) and a second reset voltage line (VSS2), the GOA units are arranged between the first reset voltage line and the second reset voltage line, and the first reset voltage line and the second reset voltage line are made of different metal layers respectively. Each metal pattern layer is formed by using an independent photomask. According to the GOA circuit, the array substrate and the display panel, the damage to the photomask due to the fact that a large amount of static electricity is gathered on the photomask can be inhibited.

Description

Technical Field

[0001] This application relates to the field of display panel manufacturing technology, and in particular to a GOA circuit, an array substrate, and a display panel. Background Technology

[0002] In display panel manufacturing technology, exposure technology is a crucial technique that transfers circuit patterns onto a substrate to form integrated circuits. However, during the exposure process, defects in the photomask pattern layout can lead to electrostatic discharge (ESD), damaging the photomask, increasing operating costs, and reducing product yield. Therefore, electrostatic discharge protection technology plays a vital role in display panel manufacturing. Current technologies primarily aim to reduce the impact of ESD on the photomask by improving its design and manufacturing process. For example, the anti-static capability can be improved by changing the material or structure of the photomask. Furthermore, optimizing exposure equipment parameters, such as exposure time and intensity, can also reduce ESD generation. While existing technologies can reduce the impact of ESD on the photomask to some extent, they often require higher manufacturing costs, posing a significant burden for large-scale production companies. Moreover, existing technologies may not effectively address ESD issues with complex photomask pattern layouts, such as multiple VSSs (Video Screens) coexisting. Utility Model Content

[0003] This invention addresses the aforementioned problems. Its purpose is to provide a GOA circuit, array substrate, and display panel that can reduce the impact of electrostatic discharge on the photomask and minimize electrostatic discharge when multiple VSSs coexist.

[0004] The first aspect of this utility model provides a GOA circuit, which includes: a multi-stage cascaded GOA unit; a clock signal line for inputting a clock signal to each of the GOA units; and a plurality of reset voltage lines, including at least a first reset voltage line (VSS1) and a second reset voltage line (VSS2), each of the GOA units being disposed between the first reset voltage line and the second reset voltage line, wherein the first reset voltage line and the second reset voltage line are respectively made using different metal layers, and each of the metal layers is formed using an independent photomask.

[0005] A second aspect of this invention provides an array substrate including a display area and the aforementioned GOA circuit formed outside the display area.

[0006] A third aspect of this invention provides a display panel comprising a color filter substrate and the aforementioned array substrate.

[0007] According to one aspect of the present invention, a GOA circuit, an array substrate, and a display panel are provided to suppress the excessive accumulation of static electricity on a photomask, thereby preventing damage to the photomask. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the GOA circuit of this utility model.

[0009] Figure 2 This is a schematic diagram of the layer of the reset voltage line VSS according to the first embodiment of this utility model.

[0010] Figure 3 This is a schematic diagram of the layer of the reset voltage line VSS according to the second embodiment of this utility model.

[0011] Figure 4 This is a schematic diagram of the layer of the reset voltage line VSS according to the third embodiment of this utility model. Detailed Implementation

[0012] [First Implementation Method]

[0013] This application provides a display panel, which includes an array substrate 1 and a color filter substrate (not shown). (Refer to...) Figures 1-4 The array substrate 1 includes a display area 100 and a GOA (Gate Driven on Array) circuit 200 formed on the outer periphery of the display area 100. The GOA circuit 200 has a similar structure and principle to existing GOA circuits and will not be described in detail here. The display panel can be driven by a single-sided method with the GOA circuit 200 disposed on one side of the display area 100, or it can be driven by a dual-sided method or other methods; this application does not specifically limit this.

[0014] The display area 100 contains multiple pixels arranged in rows and columns. The GOA circuit 200 includes: multiple cascaded GOA units 11; a clock signal line CLK connected to each GOA unit 11, which inputs a clock signal as a control signal to each GOA unit 11; a first reset voltage line VSS1 and a second reset voltage line VSS2. Each GOA unit 11 is disposed between the first reset voltage line VSS1 and the second reset voltage line VSS2. The first reset voltage line VSS1 is located at the input terminal of the GOA unit 11 and is electrically connected to the transistor TFT1 of each GOA unit 11. The second reset voltage line VSS2 is located at the output terminal of the GOA unit 11 and is electrically connected to the transistor TFT2 of each GOA unit 11. The multiple GOA units 11 are sequentially designated GOA1, GOA2, GOA3…, GOAN from the 1st to the Nth stage, and output signals Gout1, Gout2, Gout3…, GoutN respectively.

[0015] refer to Figure 2 , Figure 2 This is a schematic diagram of the VSS layer of the GOA circuit 200 according to the first embodiment of this utility model. The first reset voltage line VSS1 is drawn using a first type of metal layer, and the second reset voltage line VSS2 is drawn using a second type of metal layer; alternatively, the first reset voltage line VSS1 can be drawn using a second type of metal layer, and the second reset voltage line VSS2 can be drawn using a first type of metal layer, meaning the metal layers are interchangeable. When forming the reset voltage lines VSS, different metal layers are etched sequentially using different photomasks to form each reset voltage line VSS. As a result, only one VSS graphic layout exists on a single photomask used to draw the VSS metal layer.

[0016] When the number of VSS is greater than 2, VSS1, VSS2, VSS3, etc. are all drawn using different metal layers. For example, VSS1 is drawn using the first type of metal layer, VSS2 is drawn using the second type of metal layer, and VSS3 is drawn using the third type of metal layer.

[0017] As is well known to those skilled in the art, the longer the VSS reset voltage line is, the easier it is for it to accumulate charge, thereby inducing static electricity at the end of the line or with adjacent lines, which can damage the photomask.

[0018] This embodiment uses different metal coatings to form each reset voltage line (VSS). Therefore, different metal layers are etched sequentially using different photomasks. During the exposure etching process, only one VSS pattern layout for drawing the metal layer exists on a single photomask, reducing the length of the reset voltage line (VSS) layout on the photomask and preventing excessive static electricity buildup that could damage it. This embodiment does not require changes to the photomask material or structure, nor does it require optimization of the lithography equipment parameters, thus avoiding increased display panel manufacturing costs. Furthermore, the VSS configuration in this embodiment does not affect the photomask performance, effectively solving the electrostatic discharge problem while ensuring lithography quality.

[0019] [Second Implementation]

[0020] refer to Figure 3 , Figure 3This is a schematic diagram of the VSS layer of the GOA circuit 200 according to the second embodiment of this utility model. The difference between the VSS layer layout in the second embodiment and the first embodiment is that when the number of VSSs is ≥2, and both VSS1 and VSS2 are drawn using the same metal layer, one of the VSSs is transformed into a main body plus segmented layout. That is, at least one segment is inserted in the middle of the VSS line, dividing the VSS line into a main body and a segmented part. The main body and the segmented part are connected through contact holes, and the length of the segmented part is less than the length of the main body excluding the segmented part. Figure 3 In the example, VSS1 and VSS2 are drawn using a first-class metal layer, while segment P1 in VSS1 is drawn using a second-class metal layer. Alternatively, in other examples, segment P1 can also be drawn using other types of metal coatings, as long as they differ from the first-class metal. Furthermore, in other examples, segment P1 can also be located in VSS2 or other VSSs, and multiple segments can be set; no specific limitations are imposed here.

[0021] This embodiment reduces the length of the reset voltage line (VSS) on the photomask during the exposure etching process by segmenting it with different metal layers. This prevents excessive static electricity buildup on the photomask, which could damage it. This embodiment does not require changes to the photomask material or structure, nor does it require optimization of the lithography equipment parameters, thus avoiding increased display panel manufacturing costs. Furthermore, this VSS configuration does not affect the photomask's performance, effectively solving the electrostatic discharge problem while ensuring lithography quality.

[0022] [Third Implementation Method]

[0023] refer to Figure 4 , Figure 4 This is a schematic diagram of the VSS layer of the GOA circuit 200 according to the third embodiment of this utility model.

[0024] In an LCD panel, taking a 4K resolution of 3840*2160 as an example, the panel has 2160 levels of GOA (Getting Area of ​​the View). Generally, these 2160 levels are arranged in a periodic repetition pattern. The repetition period is related to the number of clock signal lines (CLK). When the number of clock signal lines is 8, the GOA will cycle 270 times in 8-level increments. It can be understood that the number of GOA units in one cycle is not limited to this and can be other numbers. Figure 4 The example described is based on the GOA definition, which uses 8 levels as a cycle.

[0025] In this embodiment, when the number of VSSs is ≥2, and both VSS1 and VSS2 are drawn using the same metal layer, one of the VSSs is transformed into a layout of main body plus segments. That is, a segment using a different metal layer than the main body is inserted in the middle of the main body of the VSS line, and the main body and the segment are connected through contact holes. Figure 4 In the example, VSS1 and VSS2 are drawn using a second-class metal layer, while the segment P1 in VSS1 is drawn using a first-class metal layer. The number of GCKs is 8, and the GOA cycle is 8 levels. Assuming the total length of the VSS within this cycle is Y, the length of the main body is A, the length of the segment is B, and the minimum trace width is X, the main body and segments must satisfy the following relationship: Y = A + B, and always A > B ≥ X. The segment layer appears at least once within a GOA cycle. The total length of the VSS is Y; by setting B ≥ X, the segment length is not less than the minimum trace width within the GOA, ensuring that the two main body segments A separated by the segmentation are at a certain distance, preventing induction between adjacent main bodies and thus avoiding static electricity. Furthermore, since the segment layer appears at least once within a GOA cycle, for the full-level GOA, segmentation is set 270 times, thereby reducing the overall layout length of the reset voltage line VSS on its photomask, preventing a large accumulation of static electricity on the photomask and thus avoiding damage to the photomask. This embodiment does not require changes to the material or structure of the photomask or optimization of the lithography equipment parameters, thus avoiding increased display panel manufacturing costs. Furthermore, the VSS setting in this embodiment does not affect the photomask performance, effectively solving the electrostatic discharge problem while ensuring lithography quality. Additionally, the length and number of segments can be arbitrarily set as long as they do not affect the target driving capability of the GOA. The trace width of the segments can be determined through simulation calculations based on the target impedance.

[0026] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A GOA circuit, characterized by, The GOA unit comprises: a plurality of GOA units connected in cascade; a clock signal line for inputting a clock signal to each of the GOA units; and a plurality of reset voltage lines, at least including a first reset voltage line (VSS1) and a second reset voltage line (VSS2), each of the GOA units being arranged between the first reset voltage line and the second reset voltage line, the first reset voltage line and the second reset voltage line are respectively made of different metal layers, and each of the metal layers is formed by using an independent mask. When the number of reset voltage lines is greater than or equal to 3, the plurality of reset voltage lines (VSS1, VSS2, VSS3,...) are respectively made of mutually different metal layers.

2. The GOA circuit according to claim 1, wherein: The first reset voltage line is located at an input end of the GOA unit and is electrically connected to a first transistor of each GOA unit, and the second reset voltage line is located at an output end of the GOA unit and is electrically connected to a second transistor of each GOA unit.

3. The GOA circuit according to claim 1, wherein: The GOA unit comprises:

4. A GOA circuit, characterized in that, a plurality of GOA units connected in cascade; a clock signal line for inputting a clock signal to each of the GOA units; and a plurality of reset voltage lines, at least including a first reset voltage line (VSS1) and a second reset voltage line (VSS2), each of the GOA units being arranged between the first reset voltage line and the second reset voltage line, at least one segment is further arranged on the plurality of reset voltage lines, a part of the reset voltage line other than the segment is a main body, the main body is formed by using a first type of metal layer, and the segment is formed by using a second type of metal layer different from the first type of metal layer, the main body and the segment are electrically connected through a contact hole, and the length of the segment is less than the length of the main body. The first reset voltage line is located at an input end of the GOA unit and is electrically connected to a first transistor of each GOA unit, and the second reset voltage line is located at an output end of the GOA unit and is electrically connected to a second transistor of each GOA unit. A plurality of segments are arranged on the plurality of reset voltage lines.

5. The GOA circuit according to claim 4, wherein The GOA units are periodically and repeatedly arranged, a predetermined number of the GOA units being one period, at least one segment being included in each period, and each period satisfying: the length Y of the reset voltage line = the length A of the main body + the length B of the segment, and A > B ≥ the minimum wiring width X of the reset voltage line.

6. The GOA circuit according to claim 4, wherein The GOA circuit comprises a display area and a GOA circuit according to any one of claims 1 to 7 formed outside the display area.

7. The GOA circuit according to claim 4, wherein The GOA circuit is arranged on one side or both sides of the display area.

8. An array substrate, characterized by, The array substrate according to claim 8 or 9 is provided with a color film substrate.

9. The array substrate of claim 8, wherein, ​ 10. A display panel, characterized by, ​

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