Solar cell
By optimizing the width ratio of the back grid lines to the grid line area and the thickness of the doped polycrystalline silicon layer in solar cells, combined with passivation and antireflection layers, the difficulties in local alignment and parasitic absorption in cell design were solved, thereby improving cell efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-03-03
AI Technical Summary
In the design and manufacturing process of existing solar cells, the width and thickness of the doped polycrystalline silicon layer and the width of the grid lines affect the cell efficiency. Problems such as local alignment difficulties, poor carrier transport capacity and high parasitic absorption exist, resulting in poor cell performance.
Design a solar cell structure in which the width of the back grid line is 1/5 to 1/18 of the width of the grid line area, the thickness of the doped polycrystalline silicon layer is 70nm to 200nm, and no tunneling layer or doped polycrystalline silicon layer is set in the non-grid line area. Combine the back passivation layer and anti-reflection layer to optimize the cell parameters to achieve the optimal balance.
By optimizing parameter design, parasitic absorption was reduced, carrier transport capability was improved, the risk of local alignment misalignment was avoided, and battery efficiency was optimized.
Smart Images
Figure CN223968154U_ABST
Abstract
Description
[0001] This application claims priority to Chinese Patent Application No. 202422950846.3, filed on November 29, 2024, entitled "A Solar Cell", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This utility model relates to the field of photovoltaic technology, and in particular to a solar cell. Background Technology
[0003] The core of Polyfin technology lies in the fact that only the gate line region has a doped polysilicon layer, while the non-gate line region has no doped polysilicon layer. This design can greatly reduce parasitic absorption and recombination of charge carriers in the gate line region, thereby improving the efficiency of the battery.
[0004] Due to the use of local passivation contacts, the efficiency of the battery is mainly affected by the width and thickness of the doped polycrystalline silicon layer and the width of the grid lines: (1) A schematic diagram of the structure of a normal battery cell is shown below. Figure 1 and Figure 2 As shown. The doped polysilicon layer 17 is too narrow (e.g. Figure 3 (2) If the doped polysilicon layer is too narrow, it will have poor carrier transport capacity; if it is too wide, it will have high parasitic absorption, which will affect the battery efficiency. (3) As the thickness of the doped polysilicon layer increases, on the one hand, the recombination current density decreases, which means that the recombination loss of the doped polysilicon layer is smaller; on the other hand, the short-circuit current decreases, which means that parasitic absorption increases, both of which will affect the battery efficiency.
[0005] The parameters mentioned above have both beneficial and detrimental effects on battery performance. Therefore, when designing and manufacturing solar cells, it is necessary to comprehensively consider the impact of each parameter on battery performance in order to achieve the optimal balance of battery performance and thus obtain the best battery efficiency. Utility Model Content
[0006] In view of this, the purpose of this utility model is to provide a solar cell for obtaining optimal battery efficiency.
[0007] To address the aforementioned technical problems, this utility model provides a solar cell, comprising: a substrate; the back side of the substrate includes a grid line region and a non-grid line region; the grid line region is provided with a back grid line and at least one set of functional layers disposed along the thickness direction of the substrate itself, the set of functional layers including a tunneling layer and a doped polycrystalline silicon layer; the back grid line is inserted into the functional layers and contacts the doped polycrystalline silicon layer near the substrate; the non-grid line region does not have the tunneling layer and the doped polycrystalline silicon layer disposed thereon;
[0008] The ratio of the width of the back gate line to the width of the gate line region is 1 / 5 to 1 / 18, including the values at both ends; the total thickness of the doped polysilicon layer is 70nm to 200nm, including the values at both ends.
[0009] Optionally, the ratio of the width of the back grid line to the width of the grid line region is 1 / 7 to 1 / 13, including the values at both ends.
[0010] Optionally, the width of the gate line region is 200μm to 700μm, including the values at both ends.
[0011] Optionally, the width of the back grid line is 30μm to 50μm, including the values at both ends.
[0012] Optionally, the spacing of the back grid lines is 1000μm to 1500μm, including the values at both ends.
[0013] Optionally, the width of the non-gateline region is 500μm to 1000μm, including the values at both ends.
[0014] Optionally, the substrate height of the non-gate line region is lower than the substrate height of the gate line region, thus creating a height difference;
[0015] Tower bases are formed in the gate line region, the non-gate line region, and the side surface of the substrate; the width of the tower base in the non-gate line region of the substrate is greater than the width of the tower base on the side surface of the substrate, and the width of the tower base on the side surface of the substrate is greater than the width of the tower base in the gate line region of the substrate.
[0016] Optionally, the doped polysilicon layer in the functional layer away from the substrate has a back passivation layer on the surface away from the tunneling layer and on the non-gate area; the back gate line penetrates the back passivation layer along the thickness direction and contacts the doped polysilicon layer.
[0017] Optionally, a back anti-reflection layer is disposed on the surface of the back passivation layer away from the substrate; the back gate line passes through the back anti-reflection layer and the back passivation layer sequentially along the thickness direction and contacts the doped polysilicon layer.
[0018] Optionally, an emitter and a front gate line are sequentially disposed on the front side of the substrate along the thickness direction; a front passivation layer is disposed on the surface of the emitter away from the substrate; a front anti-reflection layer is disposed on the surface of the front passivation layer away from the emitter; the front gate line sequentially penetrates the front anti-reflection layer and the front passivation layer along the thickness direction and contacts the emitter.
[0019] As can be seen, the solar cell provided by this utility model includes: a substrate; the back side of the substrate includes a grid line region and a non-grid line region; the grid line region is provided with a back grid line and at least one set of functional layers disposed along the thickness direction of the substrate itself, the set of functional layers including a tunneling layer and a doped polycrystalline silicon layer; the back grid line is inserted into the functional layer and contacts the doped polycrystalline silicon layer close to the substrate; the non-grid line region is not provided with the tunneling layer and the doped polycrystalline silicon layer; the ratio of the width of the back grid line to the width of the grid line region is 1 / 5 to 1 / 18, including the values at both ends; the total thickness of the doped polycrystalline silicon layer is 70nm to 200nm, including the values at both ends. After comprehensively considering the influence of various parameters on battery performance, this invention determines that when the ratio of the width of the back grid line to the width of the grid line area is 1 / 5 to 1 / 18, including the values at both ends; and the thickness of the doped polycrystalline silicon layer is 70nm to 200nm, including the values at both ends, the overall electrical performance parameters of the battery reach their best. This achieves the optimal balance of battery performance while avoiding the risk of local misalignment, thus obtaining the best battery efficiency. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of the entire structure of a normal solar cell;
[0022] Figure 2 This is a schematic diagram of a partial structure of a normal solar cell;
[0023] Figure 3 This is a schematic diagram of a partial structure of a solar cell with alignment misalignment.
[0024] Figure 4 A schematic diagram of the structure of a solar cell provided in an embodiment of this utility model;
[0025] Figure 5A partial structural schematic diagram of a solar cell provided in an embodiment of this utility model;
[0026] Figure 6 This is a schematic diagram showing the relationship between electrical performance parameters and the thickness of the doped polycrystalline silicon layer.
[0027] The annotations in the attached figures are explained as follows:
[0028] 11-Substrate; 111-Gate line region; 112-Non-gate line region; 12-Emitter; 13-Front-side passivation layer; 14-Front-side anti-reflection layer; 15-Front-side gate line; 16-Tunneling layer; 17-Doped polysilicon layer; 18-Back-side passivation layer; 19-Back-side anti-reflection layer; 20-Back-side gate line. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0030] Please refer to Figure 4 and Figure 5 , Figure 4 A schematic diagram of the structure of a solar cell provided in an embodiment of this utility model; Figure 5 This is a partial structural diagram of a solar cell provided in an embodiment of the present invention. The solar cell provided in this embodiment may include: a substrate 11; the back side of the substrate 11 includes a grid line region 111 and a non-grid line region 112; the grid line region 111 is provided with a back grid line 20 and at least one set of functional layers disposed along the thickness direction of the substrate 11 itself, the set of functional layers including a tunneling layer 16 and a doped polycrystalline silicon layer 17; the back grid line 20 is inserted into the functional layers and contacts the doped polycrystalline silicon layer 17 near the substrate 11; the non-grid line region 112 is not provided with a tunneling layer 16 and a doped polycrystalline silicon layer 17;
[0031] The ratio of the width of the back gate line 20 to the width of the gate line region 111 is 1 / 5 to 1 / 18, including the values at both ends; the total thickness of the doped polysilicon layer 17 is 70nm to 200nm, including the values at both ends.
[0032] It should be noted that, in this embodiment, the width of the back grid line 20 represents the maximum width of the back grid line 20 perpendicular to the thickness direction. This maximum width is proportional to the width of the grid line region 111, ranging from 1 / 5 to 1 / 18, and includes the values at both ends. For example, when the back grid line 20 adopts... Figure 4 In the structure shown, the width of the back gate line 20 gradually decreases from the doped polysilicon layer 17 towards the surface. In this embodiment, the maximum width of the back gate line 20 perpendicular to the thickness direction is the width of the back gate line 20 near the doped polysilicon layer 17. The ratio of this width to the width of the gate line region 111 is 1 / 5 to 1 / 18, including the values at both ends. In this embodiment, the width of the gate line region 111 is consistent with the width of the tunneling layer 16 and the doped polysilicon layer 17. Preferably, the ratio of the width of the back gate line 20 to the width of the gate line region 111 is 1 / 7 to 1 / 13, including the values at both ends.
[0033] It should be noted that doped polysilicon has high parasitic absorption of light, which reduces the photoelectric conversion current density of the battery. By (1) designing the non-gate region 112 to be undoped polysilicon, parasitic absorption is greatly reduced, thereby improving battery efficiency. By (2) designing the gate region 111 to be thickly doped polysilicon, the back gate line 20 can be effectively blocked from burning through the doped polysilicon layer 17, thus achieving tunneling transport and reducing the recombination of carriers in the gate region 111, thereby achieving the goal of improving battery efficiency.
[0034] It should be noted that in this embodiment, the back grid line 20 is a grid line that collapses after sintering. In the actual preparation process of the back grid line 20, the paste is first printed onto the grid line area 111 using a printing screen, and then the printed paste is sintered to form the final back grid line 20. The grid line obtained after sintering is wider than the grid line before sintering.
[0035] This embodiment does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, an N-type substrate or a P-type substrate. This embodiment also does not limit the specific type of substrate 11; substrate 11 can be, but is not limited to, a silicon substrate. It should be noted that silicon is a common material in the prior art, and this embodiment does not limit the internal composition of substrate 11, but directly uses a silicon substrate made of existing materials.
[0036] Furthermore, in order to improve the light trapping effect of the front side of the substrate 11, the front side of the substrate 11 in this embodiment may have a pyramidal textured surface.
[0037] This embodiment does not limit the specific type of tunneling layer 16. Tunneling layer 16 may include, but is not limited to, a silicon oxide layer. It should be noted that silicon oxide layer is a common material in the prior art. This embodiment does not limit the internal composition of tunneling layer 16, but directly uses a film layer made of existing materials as tunneling layer 16.
[0038] This embodiment does not limit the specific type of the doped polysilicon layer 17. The specific type of the doped polysilicon layer 17 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the doped polysilicon layer 17 can be an N-type doped polysilicon layer; when the substrate 11 is a P-type substrate, the doped polysilicon layer 17 can be a P-type doped polysilicon layer. The N-type doped polysilicon layer contains N-type impurities, and the P-type doped polysilicon layer contains P-type impurities.
[0039] This embodiment does not limit the specific number of tunneling layers 16 and doped polysilicon layers 17. For example: (1) a set of functional layers can be provided in the gate line region 111, with tunneling layers 16 and doped polysilicon layers 17 arranged sequentially along the thickness direction of the substrate 11; (2) two sets of functional layers can be provided in the gate line region 111, with a first tunneling layer, a first doped polysilicon layer, a second tunneling layer, and a second doped polysilicon layer arranged sequentially along the thickness direction of the substrate 11. It should be noted that the latter can effectively prevent the back gate line 20 from burning through the doped polysilicon layer 17, thereby achieving tunneling transport, which reduces the recombination of carriers in the gate line region 111 and achieves the purpose of improving battery efficiency.
[0040] This embodiment does not limit the specific width of the tunneling layer 16 and the doped polysilicon layer 17 (i.e., the specific width of the gate line region 111). For example, the width of the gate line region can be 200μm to 700μm, including the values at both ends. It should be noted that the width of the gate line region will affect the local alignment of the back gate line 20. In this embodiment, the width of the gate line region is within the above range, which can effectively avoid the risk of local alignment misalignment.
[0041] This embodiment does not limit the specific type of the back grid line 20. The back grid line 20 can be, but is not limited to, a metal grid line. It should be noted that metal is a common material in the prior art. This embodiment does not limit the internal composition of the back grid line 20, but directly uses a metal grid line made of existing materials as the back grid line 20.
[0042] This embodiment does not limit the specific width of the back-side gate line 20. For example, the width of the back-side gate line 20 can be 30μm to 50μm, including the values at both ends. This embodiment does not limit the specific spacing of the back-side gate line 20. For example, the spacing of the back-side gate line 20 can be 1000μm to 1500μm, including the values at both ends. This embodiment does not limit the specific width of the non-gate line region 112. For example, the width of the non-gate line region 112 can be 500μm to 1000μm, including the values at both ends.
[0043] Furthermore, to improve the passivation effect, in this embodiment, the doped polysilicon layer 17 in the functional layer facing away from the substrate 11 has a back passivation layer 18 on the surface facing away from the tunneling layer 16 and in the non-gate line region 112. The back gate line 20 penetrates the back passivation layer 18 along the thickness direction and contacts the doped polysilicon layer 17. This embodiment does not limit the specific type of the back passivation layer 18; the back passivation layer 18 may include, but is not limited to, an aluminum oxide layer. It should be noted that the aluminum oxide layer is a common material in the prior art. This embodiment does not limit the internal composition of the back passivation layer 18, but directly uses a film layer made of existing materials as the back passivation layer 18.
[0044] Furthermore, to reduce light reflection, in this embodiment, a back anti-reflection layer 19 can be disposed on the surface of the back passivation layer 18 facing away from the substrate 11; the back gate line 20 sequentially penetrates the back anti-reflection layer 19 and the back passivation layer 18 along the thickness direction and contacts the doped polysilicon layer 17. It should be noted that in this structure, in this embodiment, the gate line region 111 is sequentially disposed with a tunneling layer 16, a doped polysilicon layer 17, a back passivation layer 18, a back anti-reflection layer 19, and a back gate line 20 along the thickness direction; the non-gate line region 112 is sequentially disposed with a back passivation layer 18 and a back anti-reflection layer 19 along the thickness direction. This embodiment does not limit the specific type of the back anti-reflection layer 19; the back anti-reflection layer 19 may include, but is not limited to, a silicon nitride layer. It should be noted that silicon nitride is a common material in the prior art, and this embodiment does not limit the internal composition of the back anti-reflection layer 19, but directly uses a film layer made of existing materials as the back anti-reflection layer 19.
[0045] This embodiment does not limit the specific structure of the front side of the substrate 11. The specific structure of the front side of the substrate 11 can be determined according to the specific type of solar cell. For example, when the solar cell is a TOPCon (Tunnel Oxide Passivating Contact) cell, the front side of the substrate 11 can be provided with an emitter 12 and a front grid line 15 sequentially along the thickness direction. This embodiment does not limit the specific type of the emitter 12. The specific type of the emitter 12 can be determined according to the specific type of the substrate 11. For example, when the substrate 11 is an N-type substrate, the emitter 12 can be a P-type emitter; when the substrate 11 is a P-type substrate, the emitter 12 can be an N-type emitter. The P-type emitter contains P-type impurities, and the N-type emitter contains N-type impurities. This embodiment does not limit the specific type of the front grid line 15. The front grid line 15 can be, but is not limited to, a metal grid line. It should be noted that metal is a common material in the prior art. This embodiment does not limit the internal composition of the front grid line 15, but directly uses a metal grid line made of existing materials as the front grid line 15.
[0046] Furthermore, to improve the passivation effect, in this embodiment, a front passivation layer 13 can be disposed on the surface of the emitter 12 facing away from the substrate 11; the front gate penetrates the front passivation layer 13 along the thickness direction and contacts the emitter 12. This embodiment does not limit the specific type of the front passivation layer 13, and the front passivation layer 13 may include, but is not limited to, an aluminum oxide layer. It should be noted that an aluminum oxide layer is a common material in the prior art. This embodiment does not limit the internal composition of the front passivation layer 13, but directly uses a film layer made of existing materials as the front passivation layer 13.
[0047] Furthermore, to reduce light reflection, in this embodiment, a front anti-reflection layer 14 can be disposed on the surface of the front passivation layer 13 facing away from the emitter 12; the front gate line 15 sequentially penetrates the front anti-reflection layer 14 and the front passivation layer 13 along the thickness direction and contacts the emitter 12. This embodiment does not limit the specific type of the front anti-reflection layer 14. For example, the front anti-reflection layer 14 may include a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer sequentially disposed along the direction facing away from the front passivation layer 13. It should be noted that the silicon nitride layer, silicon oxynitride layer, and silicon oxide layer are all common materials in the prior art. This embodiment does not limit the internal composition of the front anti-reflection layer 14, but directly uses a stacked film layer made of existing materials as the front anti-reflection layer 14.
[0048] Furthermore, in this embodiment, the height of the substrate 11 in the non-gate region 112 can be lower than the height of the substrate 11 in the gate region 111, creating a height difference. This ensures complete removal of doped ions from the doped polysilicon layer 17 in the non-gate region 112 and the underlying substrate 11, thereby significantly reducing parasitic absorption and improving battery efficiency. It also effectively prevents short circuits caused by contact between the gate region 111 and the non-gate region 112. Simultaneously, tower bases are formed in the gate region 111, the non-gate region 112, and the sides of the substrate 11. The non-gate region 111 of the substrate 11... The width of the tower base can be greater than the width of the side tower base of the substrate 11, and the width of the side tower base of the substrate 11 can be greater than the width of the tower base of the gate line region 111 of the substrate 11. Among them, using a larger tower base on the side can improve the insulation of the front and back sides of the substrate 11, thereby effectively reducing leakage current caused by edge PN junction residue. Using a larger tower base in the non-gate line region 112 can not only improve the passivation effect, but also improve the light absorption capacity, thereby improving the photoelectric conversion efficiency. Using a smaller tower base in the gate line region 11 can improve the ohmic contact, giving it better photoelectric conversion efficiency.
[0049] Based on the above embodiments, after comprehensively considering the influence of various parameters on battery performance, this utility model determines that when the ratio of the width of the back grid line to the width of the grid line area is 1 / 5 to 1 / 18, including the values at both ends; and the thickness of the doped polycrystalline silicon layer is 70nm to 200nm, including the values at both ends, the overall electrical performance parameters of the battery reach the best. While achieving the optimal balance of battery performance, it also avoids the risk of local misalignment, thereby obtaining the best battery efficiency.
[0050] To facilitate understanding of this invention, embodiments of this invention provide a specific process for confirming the structural parameters of the aforementioned solar cell, which includes:
[0051] The doped polysilicon layer 17 is patterned and printed to print gate lines on it. The width d1 of the back gate line 20 (the gate line that collapses after sintering) is designed to be in the range of 5μm-50μm; the width d2 of the doped polysilicon layer 17 is in the range of 5μm-750μm; the width d3 of the non-gate line region 112 is in the range of 500μm-1000μm; the spacing of the back gate line 20 is 1000μm-1500μm; the ratio d1 / d2 of the width of the back gate line 20 to the width of the gate line region 111 (i.e., the width of the doped polysilicon layer 17) is in the range of 1 / 5-1 / 18; and the ratio d2 / d3 of the width of the doped polysilicon layer 17 and the width of the non-gate line region 112 is in the range of 1 / 5-12 / 5. Solar cells under different parameter conditions were tested to obtain their electrical performance parameters, including: conversion efficiency (Eta), open-circuit voltage (Voc), short-circuit current (Isc), fill factor (FF), series resistance (Rs), and parallel resistance (Rsh). The obtained electrical performance parameters under different parameter conditions are shown in Table 1. Table 1 only lists some of the test results when the width d1 of the back grid line 20 is 40 μm.
[0052] Table 1 Electrical performance parameters under different parameter conditions
[0053]
[0054] Based on the above test results, and considering the potential for printing accuracy deviations, screen deformations, and discrepancies between the designed width of the doped polysilicon layer 17 and actual process control, the optimal width of the gate region 111 (i.e., the optimal width of the doped polysilicon layer 17) was determined to be 200μm~700μm, including the values at both ends; the optimal ratio of the width of the back gate line 20 to the width of the gate region 111 (i.e., the width of the doped polysilicon layer 17) was 1 / 7~1 / 13, including the values at both ends.
[0055] Please refer to Figure 6 , Figure 6 This is a schematic diagram showing the relationship between electrical performance parameters and the thickness of the doped polycrystalline silicon layer 17. Figure 6 As the thickness of the doped polysilicon layer 17 increases, on the one hand, the recombination current density (denoted by Jometal, referring to the current density of recombination at the contact between the gate line and the substrate 11) decreases (a smaller Jometal results in a larger on-state voltage, and vice versa), meaning that the recombination loss of the doped polysilicon layer 17 is smaller; on the other hand, the short-circuit current (denoted by Isc, referring to the maximum current that can be generated when the voltage is 0) decreases (a smaller Isc results in a smaller current that can be provided under the same illumination conditions), meaning that parasitic absorption increases; after the thickness of the doped polysilicon layer 17 increases to a certain value, Isc = Jometal, and further increases result in Isc < Jometal. Furthermore, if the thickness of the doped polysilicon layer 17 does not match the actual paste, it will be burned through, leading to increased recombination.
[0056] Based on the relationship between the above electrical performance parameters and the thickness of the doped polysilicon layer 17, the optimal thickness of the doped polysilicon layer 17 is sought so that the efficiency gain (on-state gain) caused by the decrease of Jometal is greater than the efficiency loss caused by the decrease of Isc, so as to achieve the best balance point and maximize efficiency. At the same time, considering that the thickness of the doped polysilicon layer 17 must match the actual paste to ensure that it will not be burned through, thereby avoiding the increase of recombination due to burn-through, the optimal thickness of the doped polysilicon layer 17 is finally determined to be 70nm~200nm, including the values at both ends.
[0057] The present invention has provided a detailed description of a solar cell. For those skilled in the art, based on the ideas of the embodiments of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A solar cell, characterized by, The application relates to a substrate; the back of the substrate comprises a gate line area and a non-gate line area; the gate line area is provided with a back gate line and at least one group of functional layers arranged along the thickness direction of the substrate; one group of the functional layers comprises a tunneling layer and a doped polysilicon layer; the back gate line is inserted into the functional layers and is in contact with the doped polysilicon layer close to the substrate; the non-gate line area is not provided with the tunneling layer and the doped polysilicon layer. The ratio of the width of the back gate line to the width of the gate line area is 1 / 5-1 / 18, and the ratio includes both ends; the total thickness of the doped polysilicon layer is 70nm-200nm, and the total thickness includes both ends. The ratio of the width of the back gate line to the width of the gate line area is 1 / 7-1 / 13, and the ratio includes both ends.
2. The solar cell according to claim 1, characterized in that, The width of the gate line area is 200mu m-700mu m, and the width includes both ends.
3. The solar cell according to claim 1, characterized in that, The width of the back gate line is 30mu m-50mu m, and the width includes both ends.
4. The solar cell of claim 1, wherein The pitch of the back gate line is 1000mu m-1500mu m, and the pitch includes both ends.
5. The solar cell of claim 1, wherein The width of the non-gate line area is 500mu m-1000mu m, and the width includes both ends.
6. The solar cell of claim 1, wherein The height of the substrate in the non-gate line area is lower than the height of the substrate in the gate line area, so that a height difference is formed.
7. The solar cell of claim 1, wherein The gate line area, the non-gate line area and the side surface of the substrate are all formed with a tower base; the width of the non-gate line area tower base of the substrate is greater than the width of the side surface tower base of the substrate, and the width of the side surface tower base of the substrate is greater than the width of the gate line area tower base of the substrate. The doped polysilicon layer in the functional layer away from the substrate is provided with a back passivation layer on the surface away from the tunneling layer and the non-gate line area; the back gate line penetrates the back passivation layer along the thickness direction and is in contact with the doped polysilicon layer.
8. The solar cell according to any one of claims 1 to 7, wherein The surface of the back passivation layer away from the substrate is provided with a back anti-reflection layer; the back gate line penetrates the back anti-reflection layer and the back passivation layer along the thickness direction in sequence and is in contact with the doped polysilicon layer.
9. The solar cell of claim 8, wherein, The front surface of the substrate is sequentially provided with an emitter and a front gate line along the thickness direction; the surface of the emitter away from the substrate is provided with a front passivation layer; the surface of the front passivation layer away from the emitter is provided with a front anti-reflection layer; the front gate line penetrates the front anti-reflection layer and the front passivation layer along the thickness direction in sequence and is in contact with the emitter.
10. The solar cell according to any one of claims 1 to 7, wherein