Circuit board structure of compatible chip

Abstract

The utility model discloses a circuit board structure of a compatible chip in the field of circuit board design, which comprises a row of first pads and a row of second pads which are arranged on a circuit board, the first pads and the second pads are arranged in one-to-one correspondence, the first pads comprise outer pads and inner pads, and the inner pads comprise outer pads and inner pads. A solder mask area is arranged between the outer bonding pad and the corresponding inner bonding pad, and the inner bonding pad is arranged between the corresponding outer bonding pad and the corresponding second bonding pad. According to the utility model, the problems that the production cost is increased and the research and development period is prolonged because a circuit board needs to be redesigned and manufactured when a chip is replaced in the prior art are solved, when a large-size chip is packaged, the large-size chip is welded on the outer bonding pad and the second bonding pad, and when a small-size chip is packaged, the small-size chip is welded on the inner bonding pad and the second bonding pad, so that the production efficiency is greatly improved. Compatible packaging of a large-size chip and a small-size chip is achieved, the universality and adaptability of the circuit board are improved, and the requirement for designing different circuit boards for different chip sizes is reduced.

Description

Technical Field

[0001] This utility model relates to the field of circuit board design technology, specifically to a circuit board structure for compatible chips. Background Technology

[0002] In today's era of rapid development in electronic devices, circuit boards, as core components, play a crucial role in the overall performance and application range of electronic devices due to their performance and compatibility. Traditional circuit board structures are often designed with specific chip layouts and pad settings in mind. This leads to numerous challenges when replacing or ensuring compatibility with chips of different specifications and models. For example, different chips have different pin spacing and electrical connection requirements, making it difficult for circuit boards to directly adapt to multiple chips. If chip replacement is needed, the circuit board must be redesigned and remanufactured, which undoubtedly increases production costs and research and development cycles.

[0003] The above-mentioned defects urgently need to be addressed. Utility Model Content

[0004] To address the issue that replacing chips requires redesigning and manufacturing circuit boards, increasing production costs and R&D cycles, this invention provides a circuit board structure for compatible chips.

[0005] The technical solution of this utility model is as follows:

[0006] A circuit board structure for a compatible chip includes a first pad and a second pad disposed on the circuit board, wherein the first pad and the second pad are disposed in a one-to-one correspondence. The first pad includes an outer pad and an inner pad, and a solder mask area is disposed between the outer pad and the corresponding inner pad. The inner pad is disposed between the corresponding outer pad and the corresponding second pad.

[0007] According to the present invention based on the above scheme, the length of the outer pad is equal to the length of the second pad, and the width of the outer pad, the width of the inner pad, and the width of the second pad are all equal.

[0008] According to the above-described scheme of this utility model, the length of the outer pad and the length of the second pad are both 156.5mm to 158.5mm.

[0009] According to the above-described scheme of this utility model, the width of the outer pad, the width of the inner pad, and the width of the second pad are all 25mm to 27mm.

[0010] According to the present invention based on the above scheme, the width of the solder mask area is equal to the width of the outer pad, the width of the inner pad, and the width of the second pad.

[0011] According to the above-described scheme of this utility model, the length of the solder resist area is 74mm to 75mm.

[0012] According to the above-described scheme of this utility model, the distance between the inner pad and the second pad is 101mm to 103mm.

[0013] According to the present invention based on the above scheme, a silkscreen frame is provided between the outer solder pad and the second solder pad, and the inner solder pad is disposed within the silkscreen frame.

[0014] According to the present utility model of the above-described scheme, the screen printing frame includes a first screen printing and a second screen printing, the first screen printing and the second screen printing overlap, the second screen printing is disposed between the inner pad and the second pad, and the inner pad is disposed within the first screen printing.

[0015] According to the present invention based on the above scheme, the width of the first silkscreen is equal to the width of the second silkscreen, and the length of the first silkscreen is greater than the length of the second silkscreen.

[0016] The advantages of this utility model based on the above solution are as follows:

[0017] In the circuit board structure of the aforementioned compatible chip, the inner pad is set between the corresponding outer pad and the corresponding second pad. When packaging a large-size chip, the large-size chip can be soldered onto the outer pad and the second pad. When packaging a small-size chip, the small-size chip can be soldered onto the inner pad and the second pad. This achieves compatibility between packaging large-size and small-size chips, improves the versatility and adaptability of the circuit board, and reduces the need to design different circuit boards for different chip sizes.

[0018] In addition, a solder mask zone is provided between the outer solder pad and the corresponding inner solder pad to prevent solder from overflowing or short-circuiting during soldering, thus ensuring the reliability of the soldering. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the structural schematic diagrams of this utility model;

[0021] Figure 2 This is the second structural schematic diagram of the present invention;

[0022] Figure 3This is a schematic diagram of the structure of the first pad.

[0023] In the diagram, 1 is the circuit board; 11 is the first pad; 111 is the outer pad; 112 is the inner pad; 12 is the second pad; 13 is the solder mask area; 14 is the silkscreen frame; 141 is the first silkscreen; and 142 is the second silkscreen. Detailed Implementation

[0024] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0025] like Figure 1 , Figure 2 As shown, this utility model provides a circuit board structure for a compatible chip, including a row of first pads 11 and a row of second pads 12 disposed on a circuit board 1, wherein the first pads 11 and the second pads 12 are disposed in a one-to-one correspondence. The first pads 11 include an outer pad 111 and an inner pad 112, and a solder resist area 13 is disposed between the outer pad 111 and the corresponding inner pad 112. The inner pad 112 is disposed between the corresponding outer pad 111 and the corresponding second pad 12.

[0026] When large-size chips need to be packaged, the chips can be soldered onto the outer pad 111 and the second pad 12. The outer pad 111 provides a larger soldering area, suitable for the pin layout of large-size chips. When small-size chips need to be packaged, the chips can be soldered onto the inner pad 112 and the second pad 12. The inner pad 112 is closer to the second pad 12, suitable for the pin layout of small-size chips. This invention achieves compatibility with both large-size and small-size chip packaging, allowing the same circuit board 1 to accommodate chips of different sizes, improving the versatility and adaptability of the circuit board 1, and reducing the need to design different circuit boards 1 for different chip sizes. In addition, a solder mask area 13 is provided between the outer pad 111 and the corresponding inner pad 112 to prevent solder overflow or short circuit during soldering, ensuring the reliability of soldering. At the same time, by rationally arranging the outer pad 111, the inner pad 112, and the second pad 12, the space utilization of the circuit board 1 is optimized, allowing more pads to be accommodated in a limited space to meet the needs of chips of different sizes.

[0027] like Figure 2 , Figure 3As shown, in this embodiment, the length of the outer pad 111 is equal to the length of the second pad 12, which makes the solder distribution more uniform during soldering and improves the soldering reliability. In addition, the widths of the outer pad 111, the inner pad 112, and the second pad 12 are all equal, ensuring the electrical compatibility between large-size chips (soldered on the outer pad 111 and the second pad 12) and small-size chips (soldered on the inner pad 112 and the second pad 12).

[0028] In this embodiment, the length of the outer pad 111 and the length of the second pad 12 are both 156.5mm to 158.5mm. The length of the outer pad 111 and the length of the second pad 12 can be designed to be any value in the range of 156.5mm, 156.6mm, 156.7mm, 156.8mm, 156.9mm, 157mm, 157.1mm, 157.2mm, 157.3mm, 157.4mm, 157.48mm, 157.5mm, 157.6mm, 157.7mm, 157.8mm, 157.9mm, 158mm, 158.1mm, 158.2mm, 158.3mm, 158.4mm, and 158.5mm. In actual design, the length of the outer pad 111 and the length of the second pad 12 can be designed according to actual needs.

[0029] In this embodiment, the width of the outer pad 111, the width of the inner pad 112, and the width of the second pad 12 are all 25mm to 27mm. The widths of the outer pad 111, inner pad 112, and second pad 12 can be designed to be any value within the range of 25mm, 25.1mm, 25.2mm, 25.3mm, 25.4mm, 25.5mm, 25.6mm, 25.7mm, 25.8mm, 25.9mm, 26mm, 26.1mm, 26.2mm, 26.3mm, 26.4mm, 26.5mm, 26.6mm, 26.7mm, 26.8mm, and 27mm. In actual design, the widths of the outer pad 111, inner pad 112, and second pad 12 can be designed according to actual needs.

[0030] like Figure 2 , Figure 3 As shown, in this embodiment, the width of the solder mask area 13 is equal to the width of the outer pad 111, the width of the inner pad 112, and the width of the second pad 12, ensuring that the solder mask area 13 can completely cover the gap between the outer pad 111 and the inner pad 112, providing sufficient electrical isolation to prevent solder overflow or short circuit during the soldering process.

[0031] In this embodiment, the length of the solder mask area 13 is 74mm to 75mm. The length of the solder mask area 13 can be designed to be any value in the range of 74mm, 74.1mm, 74.2mm, 74.3mm, 74.4mm, 74.5mm, 74.6mm, 74.7mm, 74.8mm, 74.9mm, 75mm, etc. In actual design, the length of the solder mask area 13 can be designed according to actual needs.

[0032] In this embodiment, the spacing between the inner pad 112 and the second pad 12 is 101mm to 103mm. The spacing between the inner pad 112 and the second pad 12 can be designed to be any value in the range of 101mm, 101.1mm, 101.2mm, 101.3mm, 101.4mm, 101.5mm, 101.6mm, 101.7mm, 101.8mm, 101.9mm, 102mm, 102.1mm, 102.2mm, 102.3mm, 102.36mm, 102.4mm, 102.5mm, 102.6mm, 102.7mm, 102.8mm, 102.9mm, and 103mm. In actual design, the spacing between the inner pad 112 and the second pad 12 can be designed according to actual needs.

[0033] like Figure 2 , Figure 3 As shown, in this embodiment, a silkscreen frame 14 is provided between the outer pad 111 and the second pad 12, and the inner pad 112 is disposed within the silkscreen frame 14. The silkscreen frame 14 provides a clear positioning reference for the pads, facilitating precise alignment of chip pins during soldering and reducing soldering errors. Specifically, the silkscreen frame 14 includes a first silkscreen 141 and a second silkscreen 142, which overlap to provide a dual positioning reference, further improving the alignment accuracy between the pads and chip pins. Furthermore, the second silkscreen 142 is disposed between the inner pad 112 and the second pad 12, and the inner pad 112 is disposed within the first silkscreen 141. During soldering, larger chips are disposed within the first silkscreen 141, and smaller chips are disposed within the second silkscreen 142, allowing the circuit board 1 to better accommodate chips of different sizes.

[0034] like Figure 2 , Figure 3 As shown, in this embodiment, the width of the first silkscreen 141 is equal to the width of the second silkscreen 142, and the length of the first silkscreen 141 is greater than the length of the second silkscreen 142. The larger length of the first silkscreen 141 is suitable for the pin layout of large-size chips, providing a larger soldering area and ensuring the soldering reliability of large-size chips; the smaller length of the second silkscreen 142 is suitable for the pin layout of small-size chips, providing higher soldering precision and ensuring the soldering reliability of small-size chips.

[0035] It should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product is usually placed in during use, or the orientation or positional relationship that is commonly understood by those skilled in the art, or the orientation or positional relationship that the product is usually placed in during use. It is only for the purpose of facilitating the description of this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application.

[0036] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0037] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.

Claims

1. A compatible chip's circuit board structure, characterized by, The first pad and the second pad are arranged on a circuit board, and the first pad and the second pad are arranged one by one, the first pad comprises an outer pad and an inner pad, and a solder mask area is arranged between the outer pad and the corresponding inner pad, and the inner pad is arranged between the corresponding outer pad and the corresponding second pad.

2. The compatible chip-on-board structure of claim 1, wherein The length of the outer pad is equal to the length of the second pad, and the width of the outer pad, the width of the inner pad and the width of the second pad are equal.

3. The compatible chip-on-board structure of claim 2, wherein The length of the outer pad and the length of the second pad are 156.5mm-158.5mm.

4. The compatible chip-on-board structure of claim 2, wherein The width of the outer pad, the width of the inner pad and the width of the second pad are 25mm-27mm.

5. The compatible chip-on-board structure of claim 1, wherein The width of the solder mask area is equal to the width of the outer pad, the width of the inner pad and the width of the second pad.

6. The compatible chip-on-board structure of claim 1, wherein The length of the solder mask area is 74mm-75mm.

7. The compatible chip-on-board structure of claim 1, wherein The distance between the inner pad and the second pad is 101mm-103mm.

8. The compatible chip-on-board structure of claim 1, wherein A silk screen frame is arranged between the outer pad and the second pad, and the inner pad is arranged in the silk screen frame.

9. The compatible chip-on-board structure of claim 8, wherein, The silk screen frame comprises a first silk screen and a second silk screen, the first silk screen overlaps the second silk screen, the second silk screen is arranged between the inner pad and the second pad, and the inner pad is arranged in the first silk screen.

10. The compatible chip-on-board structure of claim 9, wherein, The width of the first silk screen is equal to the width of the second silk screen, and the length of the first silk screen is greater than the length of the second silk screen.

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