Semiconductor device

Abstract

A semiconductor device includes a memory cell structure including a transistor structure and a memory structure. The gate electrode of the transistor structure extends in a direction substantially perpendicular to the surface of the substrate of the semiconductor device, which enables an increase in gate length with minimal to no increase in the horizontal or lateral dimension of the memory cell structure. The channel layer surrounds the sidewalls and the bottom surface of the gate electrode to form a cylindrical channel, which increases the channel area of the transistor structure, which enables the memory cell structure to achieve low leakage current, and enables high lateral density of the memory cell structure in a semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Non-volatile memory cells are a type of memory cell that can include transistors connected in series with memory elements such as capacitors, phase change material layers, resistive layers, and / or magnetic layers. This can be called a one transistor-one memory element (1T-1X). In a 1T-1X cell, the memory element selectively stores data (e.g., logic "1" or logic "0" values) based on factors such as charge, resistivity, capacitance, and / or magnetic field. The state of the memory element can be selectively modified and / or read by charging or discharging the memory element using a transistor. Utility Model Content

[0003] In embodiments of this disclosure, a device includes a plurality of back-end dielectric layers. A semiconductor device includes a memory cell structure within the plurality of back-end dielectric layers. The memory cell structure includes a memory structure and a transistor structure above the memory structure. The transistor structure includes a first source / drain region, a second source / drain region above the first source / drain region, a gate electrode extending between the first source / drain region and the second source / drain region, and a channel layer extending between the first source / drain region and the second source / drain region, wherein the channel layer surrounds the periphery of the gate electrode.

[0004] In embodiments of this disclosure, a semiconductor device includes a memory structure. The semiconductor device includes a first source / drain region, a second source / drain region above the first source / drain region, and a gate electrode having an elongated shape in a direction generally perpendicular to a plurality of back-end dielectric layers of the semiconductor device. The first source / drain region is located below the bottom surface of the gate electrode. The second source / drain region is adjacent to the sidewall of the gate electrode. The semiconductor device includes a channel layer surrounding the sidewall and bottom surface of the gate electrode.

[0005] In embodiments of this disclosure, a method includes forming a first source / drain region of a transistor structure for forming a memory cell structure in a semiconductor device. The method includes forming a dielectric layer over the first source / drain region. The method includes forming a second source / drain region in the dielectric layer. The method includes forming a notch in the dielectric layer adjacent to the second source / drain region, wherein the first source / drain region is exposed via the notch. The method includes forming a channel layer on the sidewalls and bottom surface of the notch. The method includes forming a gate dielectric layer on the channel layer in the notch. The method includes forming a gate electrode on the gate dielectric layer.

[0006] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a schematic diagram of an exemplary environment in which the systems and / or methods described herein can be implemented.

[0009] Figure 2A-2C This is a schematic diagram of the exemplary semiconductor device described in this article.

[0010] Figures 3A-3D This is a schematic diagram of an exemplary implementation of the storage cell structure described in this article.

[0011] Figure 4A-4X This is a schematic diagram illustrating an exemplary implementation of the storage cell structure described herein.

[0012] Figure 5A and 5B This is a schematic diagram of an exemplary implementation of the storage cell structure described in this article.

[0013] Figures 6A-6F This is a schematic diagram illustrating an exemplary implementation of the storage cell structure described herein.

[0014] Figure 7A and 7B This is a schematic diagram of an exemplary implementation of the storage cell structure described in this article.

[0015] Figures 8A-8D This is a schematic diagram illustrating an exemplary implementation of the storage cell structure described herein.

[0016] Figure 9A and 9B This is a schematic diagram of an exemplary implementation of the storage cell structure described in this article.

[0017] Figure 10A-10D This is a schematic diagram illustrating an exemplary implementation of the storage cell structure described herein.

[0018] Figure 11 This is a schematic diagram of the exemplary components or devices described in this article.

[0019] Figure 12 This is a flowchart of an exemplary process related to forming the memory cell structure described in this article.

[0020] Explanation of reference numerals in the attached figures

[0021] 100: Exemplary Environment

[0022] 102: Sedimentation Tools

[0023] 102-112: Semiconductor Processing Tools

[0024] 104: Exposure Tools

[0025] 106: Developing tools

[0026] 108: Etching tools

[0027] 110: Flattening tool

[0028] 112: Electroplating tools

[0029] 114: Wafer / Die Transfer Tool

[0030] 200: Semiconductor devices

[0031] 202: Storage Cell Structure

[0032] 204: Storage Structure

[0033] 206, 208, 210: Source / Drain regions

[0034] 212: Channel Layer

[0035] 212a, 212b, 216a, 216b: Partial

[0036] 214: Gate electrode

[0037] 216: Gate dielectric layer

[0038] 218, 224, 226: Source / Drain Interconnect

[0039] 220: Word line conductive structure

[0040] 222: Bit line conductive structure

[0041] 228, 232, 236, 240, 242: Dielectric layers

[0042] 230, 234, 238: Etching stop layer, ESL

[0043] 244, 246, 250, 252, 254, 256, 258: Padding layer

[0044] 248: Transistor Structure

[0045] 300, 400, 500, 600, 700, 800, 900, 1000: Exemplary embodiments; 402, 404, 406, 408, 410, 412, 416, 602, 802, 1002: Notch

[0046] 414: Sacrificial Layer

[0047] 702, 704: Diffusion barrier layer

[0048] 1100: Device

[0049] 1110: Bus

[0050] 1120: Processor

[0051] 1130: Memory

[0052] 1140: Input element

[0053] 1150: Output element

[0054] 1160: Communication Components

[0055] 1200: Process

[0056] 1210, 1220, 1230, 1240, 1250, 1260, 1270: Squares

[0057] D1, D2, D3, D4, D5, D6, D7: Dimensions Detailed Implementation

[0058] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may further include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0059] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0060] Memory elements with a memory cell structure (e.g., a 1T-1X memory cell structure) can be configured to store data for extended periods without applied power. Current leakage through the transistor or memory cell structure negatively impacts the memory element's ability to store data for long periods. For example, if the memory element is implemented using a capacitor, current leakage through the transistor can deplete the charge stored in the capacitor, leading to data loss. As a result, the memory element may need to be periodically "refreshed" (e.g., the charge stored in the memory element may need to be replenished) to prevent data loss. This increases the power consumption of the memory cell structure, thereby reducing the power efficiency of the memory cell structure. Increasing the gate length of the transistor can reduce current leakage through the transistor, but at the cost of reducing the memory cell density in semiconductor devices containing memory cell structures.

[0061] In some embodiments described herein, the semiconductor device includes a memory cell structure (e.g., a 1T-1X memory cell structure), which includes transistor structures and memory structures corresponding to memory elements of the memory cell structure. The gate electrode of the transistor structure extends vertically within the semiconductor device (e.g., in the z-direction, substantially perpendicular to the surface of the substrate of the semiconductor device), allowing the gate length of the memory cell structure to be increased with minimal to no increase in horizontal or lateral (e.g., xy-direction) dimensions. A channel layer surrounds the sidewalls and bottom surface of the gate electrode to form a cylindrical channel, which increases the channel area of ​​the transistor structure, enabling low leakage current in the memory cell structure and allowing for high horizontal or lateral density of the memory cell structure within the semiconductor device. The low current leakage of the memory cell structure allows data stored in the memory cell structure and memory structure to be retained for longer periods between refreshes, thereby reducing the power consumption of the memory cell structure and improving its power efficiency.

[0062] Figure 1 This is a schematic diagram of an exemplary environment 100 in which the systems and / or methods described herein can be implemented. For example... Figure 1As shown, the exemplary environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transfer tool 114. The plurality of semiconductor processing tools 102-112 may include deposition tools 102, exposure tools 104, developing tools 106, etching tools 108, planarization tools 110, electroplating tools 112, and / or other types of semiconductor processing tools. Among other examples, the tools included in the exemplary environment 100 may be contained in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, etc.

[0063] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced chemical vapor deposition (PECVD) tool, a high-density plasma chemical vapor deposition (HDP-CVD) tool, a sub-atmospheric chemical vapor deposition (SACVD) tool, a low-pressure chemical vapor deposition (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form layers and / or regions of a device through epitaxial growth. In some embodiments, the exemplary environment 100 includes various types of deposition tools 102.

[0064] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., deep UV, extreme UV, EUV, and / or the like), an X-ray source, an electron beam source, and / or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming structures of one or more semiconductor devices, patterns for etching various portions of the semiconductor devices, etc. In some implementations, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0065] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve either exposed or unexposed portions of the photoresist layer.

[0066] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, etc. In some embodiments, etching tool 108 includes a chamber filled with etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to etch the one or more portions isotropically or directionally.

[0067] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing multiple layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or electroplated materials. Planarization tool 110 can polish or planarize the surface of a semiconductor device via a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). Planarization tool 110 may utilize an abrasive and corrosive chemical slurry combined with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device). The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in position by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and plan any irregularities in the semiconductor device, making the semiconductor device flat or planar.

[0068] Electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, semiconductor device, etc.) or a portion thereof with one or more metals. For example, electroplating tool 112 may include copper electroplating devices, aluminum electroplating devices, nickel electroplating devices, tin electroplating devices, compound material or alloy (e.g., tin-silver, tin-lead, and / or similar) electroplating devices, and / or one or more other types of conductive materials, metals, and / or similar materials.

[0069] The wafer / die transport vehicle 114 includes a mobile robot, robotic arm, tram or railcar, overhead hoist transport (OHT) system, automated materially handling system (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between semiconductor processing tools 102-112, or configured to transport substrates and / or semiconductor devices between multiple processing chambers within the same semiconductor processing tool and / or configured to transport substrates and / or semiconductor devices to and from other locations (e.g., wafer racks, storage chambers, etc.). In some implementations, the wafer / die transport vehicle 114 may be a programmed device programmed to travel a specific path and / or capable of semi-autonomous or autonomous operation. In some implementations, exemplary environment 100 includes multiple wafer / die transport vehicles 114.

[0070] For example, the wafer / die transfer tool 114 can be incorporated into a cluster tool or another type of tool that includes multiple processing chambers, and can be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, such as transferring substrates and / or semiconductor devices between processing chambers and buffers, transferring substrates and / or semiconductor devices between processing chambers and interface tools such as equipment front end modules (EFEMs), and / or transferring substrates and / or semiconductor devices between processing chambers and transport vehicles (e.g., front opening unified pods, FOUPs). In some embodiments, the wafer / die transfer tool 114 may be incorporated into a multi-chamber (or cluster) deposition tool 102, which may include pre-cleaning chambers (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from the substrate and / or semiconductor device) and various types of deposition chambers (e.g., chambers for depositing different types of materials, chambers for performing different types of deposition operations). In these embodiments, the wafer / die transfer tool 114 is configured to transfer substrates and / or semiconductor devices between the chambers of the deposition tool 102 without disrupting or removing the vacuum (or at least a partial vacuum) between the multiple chambers and / or multiple processing operations in the deposition tool 102, as described herein.

[0071] In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transfer tool 114 may be used to perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transfer tool 114 may be used to form a first source / drain region of a transistor structure for a memory cell structure in a semiconductor device; form a dielectric layer over the first source / drain region; form a second source / drain region in the dielectric layer; form a notch in the dielectric layer adjacent to the second source / drain region, wherein the first source / drain region is exposed through the notch; form a channel layer on the sidewalls and bottom surface of the notch; form a gate dielectric layer on the channel layer in the notch and / or form a gate electrode on the gate dielectric layer, etc. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transfer tool 114 may be used to perform bonding Figures 4A to 4X , Figures 6A to 6F , Figures 8A to 8D , Figures 10A to 10D and / or Figure 12 One or more semiconductor processing operations as described above.

[0072] Figure 1The number and arrangement of the devices shown are provided as one or more examples. In fact, with... Figure 1 Compared to what is shown, there may be additional devices, fewer devices, different devices, or devices arranged differently. Furthermore, Figure 1 The two or more devices shown can be implemented within a single device or Figure 1 The single device shown can be implemented as multiple distributed devices. Alternatively, a group of devices (e.g., one or more devices) in the exemplary environment 100 can perform one or more functions described as being performed by another group of devices in the exemplary environment 100.

[0073] Figure 2A-2C This is a schematic diagram of the exemplary semiconductor device 200 described herein. The semiconductor device 200 may include a semiconductor memory device or another type of semiconductor device including one or more memory cell structures 202. In some embodiments, the semiconductor device 200 includes a plurality of memory cell structures 202 arranged in a grid as a memory cell array. Each memory cell structure 202 may correspond to a 1T-1X memory cell in the memory cell array.

[0074] Figure 2A A perspective view of a memory cell structure 202 is shown. The memory cell structure 202 includes a memory structure 204 coupled to a transistor structure. The memory structure 204 includes a capacitor structure (e.g., a deep trench capacitor (DTC) structure, a thin film capacitor structure), a ferroelectric memory structure, a resistive memory structure, a phase change material memory structure, and / or other types of memory structures that can be configured to correspond to two or more states corresponding to two or more logic values.

[0075] The memory structure 204 is electrically coupled to the source / drain region 206 of the memory cell structure 202. "Source / drain region" can refer individually or collectively to the source or drain, depending on the context. The source / drain region 206 is located above the memory structure 204, such that the memory structure and the source / drain region 206 are arranged perpendicularly to the z-direction in the semiconductor device 200. The z-direction may be substantially perpendicular to the substrate and / or one or more back-end dielectric layers of the semiconductor device 200.

[0076] The memory cell structure 202 further includes one or more source / drain regions 208 and / or 210 located above the source / drain region 206 in the z-direction. A channel layer 212 of the memory cell structure 202 is located between the gate electrode 214 and the source / drain regions 208 and / or 210. The source / drain regions 208 and 210 are adjacent to the sidewalls of the gate electrode 214 on opposite sides of the gate electrode 214, and the source / drain region 206 is located below the bottom surface of the gate electrode 214.

[0077] Gate electrode 214 includes an elongated structure in the z-direction. Gate electrode 214 extends in the z-direction between source / drain regions 206 and 208 (and / or between source / drain regions 206 and 210), and can therefore be referred to as a vertical gate. Gate electrode 214 may include an approximately cylindrical shape such that channel layer 212 surrounds gate electrode 214 to form an approximately cylindrical channel. Alternatively, gate electrode 214 may include a rectangular or triangular prism shape, and channel layer 212 surrounds the side and bottom surfaces of gate electrode 214.

[0078] The channel extends in the z-direction between source / drain regions 206 and 208 and / or between source / drain regions 206 and 210. Therefore, the gate length and channel length of the transistor in the memory cell structure 202 are dimensions in the z-direction. A portion 212a of the channel layer 212 extends in the xy plane of the semiconductor device 200 such that it lies on the top surface of the source / drain regions 208 and / or 210. The portion 212a of the channel layer 212 extends laterally outward from the portion 212b of the channel layer 212 and may extend across multiple memory cell structures 202 in the x-direction (which is substantially perpendicular to the z-direction), such as... Figure 2A As shown in Example 200, source / drain regions 208 and 210 can each be spaced apart from a portion 212b of channel layer 212, while source / drain regions 208 and 210 can each be in direct physical contact with a portion 212a of channel layer 212. Therefore, current can flow between source / drain regions 206 and 208 through portions 212a and 212b of channel layer 212.

[0079] A portion 212b of the channel layer 212 is an approximately cylindrical portion of the channel layer 212 surrounding the gate electrode 214. The portion 212b of the channel layer 212 is also located below the bottom surface of the gate electrode 214, such that the portion 212b of the channel layer 212 is located between the bottom surface of the gate electrode 214 and the source / drain region 206.

[0080] The memory cell structure 202 further includes a gate dielectric layer 216. The gate dielectric layer 216 is located between the channel layer 212 and the gate electrode 214, and its arrangement is similar to that of the channel layer 212. For example, the gate dielectric layer 216 may include a portion 216a extending in the xy plane of the semiconductor device 200, such that portion 216a of the gate dielectric layer 216 is located above the top surface of the source / drain regions 208 and / or 210. Portion 216a of the gate dielectric layer 216 extends laterally outward from portion 216b of the gate dielectric layer 216, and may extend in the x-direction across multiple memory cell structures 202, such as... Figure 2A As shown in the example, a portion 216b of the gate dielectric layer 216 is an approximately cylindrical portion of the gate dielectric layer 216 surrounding the gate electrode 214. This portion 216b of the gate dielectric layer 216 is also located below the bottom surface of the gate electrode 214, such that it lies between the bottom surface of the gate electrode 214 and the source / drain region 206.

[0081] The memory cell structure 202 includes an electrically coupled memory structure 204 and a source / drain interconnect 218 of a source / drain region 206. The source / drain interconnect 218 may include vias, columns, pillars, and / or another type of elongated structure in the z-direction.

[0082] The gate electrode 214 may extend over a portion 212a of the channel layer 212 and a portion 216b of the gate dielectric layer 216, and may be electrically coupled and / or physically coupled to the word line conductive structure 220 of the semiconductor device 200. In some embodiments, the word line conductive structure 220 extends along the y-direction in the semiconductor device 200, which is substantially perpendicular to the x and z directions. Alternatively and additionally, the word line conductive structure 220 extends in the x-direction. The word line conductive structure 220 may include a metallization layer, trenches, conductive traces, and / or another type of conductive structure.

[0083] Source / drain regions 208 and / or 210 may be electrically coupled to bit line conductive structures 222 via source / drain interconnects 224 and / or source / drain interconnects 226, respectively. Source / drain interconnects 224 and 226 may each include vias, pillars, struts, and / or another type of elongated structure in the z-direction. Bit line conductive structures 222 extend in the x-direction of the semiconductor device 200. Additionally and / or alternatively, bit line conductive structures 222 extend in the y-direction. Bit line conductive structures 222 may include metallization layers, trenches, conductive traces, and / or another type of conductive structure. Both word line conductive structures 220 and bit line conductive structures 222 may be coupled to circuitry (including control circuitry, read buffers, write buffers, and / or another type of circuitry in the semiconductor device 200).

[0084] Figure 2B The storage cell structure 202 is shown along... Figure 2A The cross-sectional view of line AA in the diagram shows that the line passes through the center of gate electrode 214. (See diagram for reference.) Figure 2B As shown, the memory cell structure 202 can be located within multiple back-end dielectric layers of the semiconductor device 200. These multiple back-end dielectric layers can be located in the back-end ofline (BEOL) region of the semiconductor device 200. In some embodiments, the memory cell structure 202 can be located in another region of the semiconductor device 200, such as the front-end ofline (FEOL) region of the semiconductor device 200.

[0085] Multiple back-end dielectric layers may include dielectric layer 228, an etch stop layer (ESL) 230 above dielectric layer 228, dielectric layer 232 above ESL 230, ESL 234 above dielectric layer 232, dielectric layer 236 above ESL 234, ESL 238 above dielectric layer 236, dielectric layer 240 above ESL 238, and / or dielectric layer 242 above dielectric layer 240, etc. Dielectric layers 228, 232, 240, and 242, as well as ESLs 230, 234, and 238, may each include one or more dielectric materials. Examples of dielectric materials include oxides, nitrides, and silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorinated silicate glass (FSG), low-k dielectric materials (e.g., dielectric materials with a dielectric constant less than 3.9), high-k dielectric materials (e.g., dielectric materials with a dielectric constant greater than 3.9) and / or another suitable dielectric material.

[0086] The memory structure 204 may be located within the dielectric layer 228 and may extend through the ESL 230. The source / drain interconnect 218 may be coupled to the top surface of the memory structure 204 and may extend through the dielectric layer 232, ESL 234, and / or dielectric layer 236, etc. The source / drain interconnect 218 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys thereof, and / or combinations thereof.

[0087] One or more pad layers 244 may be located between the source / drain interconnect 218 and the dielectric layers 232, 236 and ESL 234. The pad layer 244 may include an adhesion pad (e.g., a pad configured to promote adhesion between the source / drain interconnect 218 and the surrounding layers), a barrier layer (e.g., a barrier layer configured to reduce or minimize material diffusion from the source / drain interconnect 218 into the surrounding layers), and / or another type of pad layer. Examples of materials used for the pad layer 244 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0088] Source / drain regions 206 may be located on source / drain interconnects 218, such that source / drain regions 206 are electrically and / or physically coupled to source / drain interconnects 218. Source / drain regions 206 may be located within dielectric layer 240 and may extend through ESL 238. Source / drain regions 206 may include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), etc.

[0089] One or more pad layers 246 may be located between the source / drain region 206 and the dielectric layer 240 and / or ESL 238. The pad layer 246 may include a barrier pad configured to prevent material migration from the source / drain region 206 into the surrounding layers, an adhesive layer configured to promote adhesion between the source / drain region 206 and the surrounding layers, and / or another type of pad layer. Examples of pad layers 246 include tantalum nitride (TaN), titanium nitride (TiN), and / or another suitable pad layer.

[0090] Gate electrode 214 extends through dielectric layer 240 and is located above source / drain region 206. Gate electrode 214 may include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), etc. A portion 212b of channel layer 212 and a portion 216b of gate dielectric layer are located between gate electrode 214 and dielectric layer 240, and between gate electrode 214 and source / drain region 206. A portion 212a of channel layer 212 and a portion 216a of gate dielectric layer 216 may be located between dielectric layer 240 and dielectric layer 242.

[0091] In some embodiments, channel layer 212 comprises a semiconductor material, such as silicon (Si). In some embodiments, channel layer 212 may comprise one or more metal oxide materials or metal oxide semiconductor materials. In some embodiments, channel layer 212 is an n-type channel, comprising tin oxide (SnO). x For example, SnO2), indium oxide (In x O yExamples of suitable materials include In₂O₃, zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO or IGZO), indium tin oxide (ITO), and / or another n-type metal oxide material. In some embodiments, channel layer 212 is a p-type channel, comprising nickel oxide (NiO), copper oxide (Cu), etc. x O, such as Cu2O), copper aluminum oxide (CuAlO) x For example, CuAlO2), copper gallium oxide (CuGaO) x For example, CuGaO2), indium copper oxide (CuInO) x For example, CuInO2), strontium copper oxide (SrCu) x O y For example, SrCu2O2), tin oxide (SnO) and / or another p-type metal oxide material.

[0092] The gate dielectric layer 216 may include one or more dielectric materials, such as hafnium oxide (HfO). x For example, HfO2), silicon dioxide (SiO2) x For example, SiO2), aluminum oxide (Al) x O y For example, Al2O3), zirconium oxide (Zr) x O y ), titanium dioxide (Ti x O y ) and / or silicon oxynitride (SiON), etc.

[0093] The source / drain region 206, gate electrode 214, channel layer 212, and gate dielectric layer 216 may be part of the transistor structure 248 of the memory cell structure 202. The source / drain region 206 of the transistor structure 248 is electrically coupled to the memory structure 204 of the memory cell structure 202 (e.g., through the source / drain interconnect 218). The memory structure 204 is located below the transistor structure 248 in the z-direction.

[0094] The gate electrode 214 of the transistor structure 248 is electrically coupled and / or physically coupled to the word line conductive structure 220 above the transistor structure 248 in the z-direction. The word line conductive structure 220 may be located in the dielectric layer 242 and may be located on the top surface of the gate electrode 214. The word line conductive structure 220 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys thereof, and / or combinations thereof.

[0095] Figure 2C The memory cell structure 202 is shown along Figure 2A The cross-sectional view of line BB in the diagram shows the line located on the side adjacent to gate electrode 214. (See diagram below.) Figure 2C As shown, the transistor structure 248 further includes source / drain regions 208 and / or source / drain regions 210. Source / drain regions 208 and 210 may be located in the dielectric layer 240 and may be electrically coupled to the bit line conductive structure 222 via source / drain interconnects 224 and 226, respectively. In some embodiments, source / drain regions 210 and 226 are omitted in the memory cell structure 202. Source / drain regions 208 and / or 210 may each include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), etc.

[0096] Source / drain interconnects 224 and 226 may be located within and extend through ESL 234, dielectric layer 236, ESL 238, and / or dielectric layer 240. Source / drain interconnects 224 and / or 226 may each comprise one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys thereof, and / or combinations thereof.

[0097] The bit-line conductive structure 222 may be located in and / or above the dielectric layer 232. The bit-line conductive structure 222 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys thereof, and / or combinations thereof.

[0098] One or more padding layers 250 may be located between the bit line conductive structure 222 and the dielectric layer 232. The padding layer 250 may include an adhesive pad (e.g., a pad configured to promote adhesion between the bit line conductive structure 222 and the surrounding layer), a barrier layer (e.g., a barrier layer configured to reduce or minimize material diffusion of the bit line conductive structure 222 into the surrounding layer), and / or another type of padding layer. Examples of materials used for the padding layer 250 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0099] One or more pad layers 252 may be located between the source / drain interconnect 224 and the dielectric layer 236 and / or 238 and / or between the source / drain interconnect 224 and the ESL 234 and / or 238. The pad layer 252 may include an adhesion pad (e.g., a pad included to promote adhesion between the source / drain interconnect 224 and surrounding layers), a barrier layer (e.g., a layer included to reduce or minimize the diffusion of material from the source / drain interconnect 224 into the surrounding layers), and / or another type of pad layer. Examples of materials used for the pad layer 252 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0100] One or more padding layers 254 may be included between the source / drain interconnect 226 and the dielectric layer 236 and / or 238 and / or between the source / drain interconnect 226 and the ESL 234 and / or 238. The padding layer 254 may include an adhesion pad (e.g., a pad configured to promote adhesion between the source / drain interconnect 226 and the surrounding layer), a barrier layer (e.g., a barrier layer configured to reduce or minimize the diffusion of source / drain interconnect 226 material into the surrounding layer), and / or another type of padding layer. Examples of materials used for the padding layer 254 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0101] One or more pad layers 256 may be located between the source / drain region 208 and the dielectric layer 240. The pad layer 256 may include an adhesion pad (e.g., a pad configured to promote adhesion between the source / drain region 208 and the surrounding layer), a barrier layer (e.g., a barrier layer configured to reduce or minimize material diffusion from the source / drain region 208 into the surrounding layer), and / or another type of pad layer. Examples of materials used for the pad layer 256 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0102] One or more pad layers 258 may be located between the source / drain region 210 and the dielectric layer 240. The pad layer 258 may include an adhesion pad (e.g., a pad configured to promote adhesion between the source / drain region 210 and the surrounding layer), a barrier layer (e.g., a barrier layer configured to reduce or minimize material diffusion from the source / drain region 210 into the surrounding layer), and / or another type of pad layer. Examples of materials used for the pad layer 258 include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0103] A portion 212a of the channel layer 212 is located on the top surface of the source / drain region 208 and / or the source / drain region 210. A portion 212a of the channel layer 212 may also be located between the dielectric layer 240 and the dielectric layer 242, such that a portion 212a of the channel layer 212 extends between the source / drain regions 208 and 210.

[0104] A portion 216a of the gate dielectric layer 216 is located above the top surface of the source / drain region 208 and / or the source / drain region 210 on a portion 212a of the channel layer 212. A portion 216a of the gate dielectric layer 216 may also be located between dielectric layers 240 and 242, such that a portion 216a of the gate dielectric layer 216 extends between the source / drain regions 208 and 210.

[0105] As mentioned above, providing Figure 2A-2C As an example. Other examples can be found related to... Figure 2A-2C The descriptions are different.

[0106] Figures 3A to 3D This is a schematic diagram of an exemplary embodiment 300 of the storage cell structure 202 described herein. Figure 3A A perspective view showing an exemplary implementation 300 of the storage cell structure 202 is shown. Figure 3B An exemplary embodiment 300 of the storage cell structure 202 is shown along... Figure 3A The cross-sectional view of line AA in the memory cell structure 202 shows that the line passes through the center of the gate electrode 214.

[0107] like Figure 3A As shown, the gate electrode 214 includes an elongated structure in the z-direction. The gate electrode 214 extends in the z-direction between the source / drain regions 206 and 208 (and / or between the source / drain regions 206 and 210), and can therefore be referred to as a vertical gate. The gate electrode 214 may include an approximately cylindrical shape, such that the channel layer 212 surrounds the gate electrode 214 to form an approximately cylindrical channel. Alternatively, the gate electrode 214 may include a rectangular or triangular prism shape, and the channel layer 212 surrounds the side and bottom surfaces of the gate electrode 214.

[0108] Further as Figure 3A As shown, and as Figure 3B As shown, a portion 212b of the channel layer 212 extends in the z-direction between the source / drain region 206 and the source / drain region 208 and / or extends in the z-direction between the source / drain region 206 and the source / drain region 210. Therefore, the channel length (Lg-) of the transistor in the memory cell structure 202 is... Figure 3A and 3B The dimension (represented as D1) can be increased in the z direction, while the dimension of the storage cell structure 202 is not increased (or minimally increased) in the x and / or y directions.

[0109] In some implementations, the channel length (dimension D1 in the z-direction) is between about 25 nanometers and about 50 nanometers. Choosing a channel length less than about 25 nanometers may result in a threshold voltage roll-off, which could lead to increased leakage in the transistor or memory cell structure 202. Choosing a channel length greater than about 50 nanometers may result in insufficient drive current for programming and / or erasing the memory structure 204. If the channel length is between about 25 nanometers and about 50 nanometers, low current leakage of the transistor can be achieved without sacrificing the drive current for programming and / or erasing the memory structure 204. However, other values ​​for the channel length, and ranges other than about 25 nanometers to about 50 nanometers, are also within the scope of this disclosure.

[0110] like Figure 3B As further shown, another example of the memory cell structure 202 includes the x-direction (or y-direction) width of the gate electrode 214. In some embodiments, the dimension D2 is at least about 30 nanometers and smaller than the diameter of a portion 212b of the channel layer 212. If the dimension D2 is less than about 30 nanometers, voids may appear in the gate electrode 214 due to insufficient gap-filling performance during the formation of the gate electrode 214. However, other values ​​and ranges of the dimension D2 are also within the scope of this disclosure.

[0111] like Figure 3B As further shown, another example of the memory cell structure 202 includes the z-direction thickness of the gate electrode 214 in terms of dimension D3. In some embodiments, dimension D3 is in the range of about 40 nanometers to about 85 nanometers. If dimension D3 is less than about 40 nanometers, the word line conductive structure 220 may not be able to fall on the gate electrode 214 because the gate electrode 214 cannot extend above the top surface of the portion 216a of the gate dielectric layer 216. If dimension D3 is greater than about 85 nanometers, voids may appear in the gate electrode 214 due to insufficient gap-filling performance during the formation of the gate electrode 214. If dimension D3 is in the range of about 40 nanometers to about 85 nanometers, the gate electrode 214 can extend a sufficient distance above the portion 216a of the gate dielectric layer 216 so that the word line conductive structure 220 can be formed on the gate electrode 214, while reducing the likelihood of voids forming in the gate electrode 214. However, other values ​​of dimension D3, as well as ranges other than about 40 nanometers to about 85 nanometers, are also within the scope of this disclosure.

[0112] Other exemplary dimensions of the memory cell structure 202 include the z-direction thickness of the source / drain regions 208 and / or 210 and the extension distance of the gate electrode 214 over a portion 216a of the gate dielectric layer 216. In some embodiments, the thickness of the source / drain regions 208 and / or 210 may be in the range of about 15 nanometers to about 30 nanometers to achieve sufficiently high planarization uniformity of the source / drain regions 208 and / or 210 while achieving sufficient gap-fill performance for the gate electrode 214. However, other values ​​in this range are also within the scope of this disclosure. In some embodiments, the extension distance of the gate electrode 214 over a portion 216a of the gate dielectric layer 216 includes a range of greater than 0 nanometers to about 5 nanometers to allow the word line conductive structure 220 to be formed on the gate electrode 214. However, other values ​​in this range are also within the scope of this disclosure.

[0113] Figure 3C and 3D A detailed view of the channel layer 212 and the storage cell structure 202 in the exemplary embodiment 300 is shown. Figure 3C A perspective view of channel layer 212 is shown. Figure 3D A top view of the channel layer is shown. (See attached image.) Figure 3C and 3D As shown, a portion 212b of channel layer 212 completely surrounds the periphery of gate electrode 214. Similarly, a portion 216b of gate dielectric layer 216 surrounds the periphery of gate electrode 214. The channel width of channel layer 212 (in...) Figure 3C and 3D The dimension D4 (as indicated in the text) can correspond to the perimeter of portion 212b of channel layer 212. Therefore, the channel width of channel layer 212 can be determined as:

[0114] D4 = πD5

[0115] Among them, size D5 (e.g.) Figure 3D (As shown) is the width of portion 212b corresponding to channel layer 212.

[0116] In some implementations, the channel width (size D4) is in the range of about 70 nanometers to about 200 nanometers. Choosing a channel width smaller than about 70 nanometers may result in insufficient drive current for programming and / or erasing the memory structure 204. Due to the high parasitic capacitance in the memory cell structure 202, choosing a channel width greater than about 200 nanometers may result in longer read / write times for the memory cell structure 202 and / or may result in lower memory cell density in the semiconductor device 200. If the channel width is in the range of about 70 nanometers to about 200 nanometers, high memory cell density can be achieved in the semiconductor device 200, and shorter read / write times can be achieved in the memory cell structure 202 without sacrificing drive current for programming and / or erasing the memory structure 204. However, other values ​​for the channel width, and ranges other than about 70 nanometers to about 200 nanometers, are also within the scope of this disclosure.

[0117] As mentioned above, providing Figures 3A to 3D As an example. Other examples can be found related to... Figures 3A to 3D The descriptions are different.

[0118] Figures 4A to 4X This is a schematic diagram of an exemplary embodiment 400 forming the storage cell structure 202 described herein. In some embodiments, combined with Figures 4A to 4X One or more of the described semiconductor processing operations can be performed using one or more of the semiconductor processing tools 102-112 described herein. In some implementations, another semiconductor processing tool can be used to perform the combined operation. Figures 4A to 4X One or more of the semiconductor processing operations described. Figures 4A to 4X Some of them are from along Figure 2A The cross-section of line AA in the diagram is shown, and Figures 4A to 4X Some of them are from along Figure 2A It is shown in the sectional view of line BB.

[0119] Turning Figure 4A A dielectric layer 228 may be formed in the semiconductor device 200. An ESL 230 may be formed on and / or above the dielectric layer 228. A memory structure 204 may pass through the ESL 230 and be formed in the dielectric layer 228. A dielectric layer 232 may be formed on and / or above the ESL 230 and on and / or above the memory structure 204. The dielectric layers 228, 230, and 232 may be arranged in the z-direction of the semiconductor device 200. The top surfaces of the dielectric layers 228, 230, and 232 may extend in the x-direction and y-direction of the semiconductor device 200.

[0120] Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and in combination Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit dielectric layer 228, ESL 230 and / or dielectric layer 232. In some embodiments, planarization tool 110 is used to planarize dielectric layer 228, ESL 230 and / or dielectric layer 232 after its formation.

[0121] In some embodiments, forming the memory structure 204 includes forming a capacitor structure in the dielectric layer 228. The capacitor structure may include a thin-film capacitor structure (e.g., a planar capacitor structure), a DTC structure, and / or another type of capacitor structure. The capacitor structure may have a metal-insulator-metal (MIM) arrangement, wherein the bottom electrode and the top electrode are separated by an insulating layer. Additionally and / or alternatively, forming the memory structure 204 may include forming a phase change material structure, forming a resistive structure, forming a ferroelectric structure, and / or forming another type of memory structure.

[0122] like Figure 4B As shown, a bitline conductive structure 222 is formed in and / or on the bitline dielectric layer 228. Forming the bitline conductive structure 222 may include forming a liner layer 250 and forming the bitline conductive structure 222 on the liner layer 250. In some embodiments, an etching tool 108 is used to etch the dielectric layer 228 and / or 232 to form trenches in which the bitline conductive structure 222 is formed. A deposition tool 102 may be used using PVD technology, ALD technology, CVD technology, or a combination of these techniques. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the backing layer 250. The deposition tool 102 and / or the electroplating tool 112 can be used with CVD, PVD, ALD, electroplating, or a combination thereof. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the bit line conductive structure 222. In some embodiments, a seed layer is first deposited on the pad layer 250, and the bit line conductive structure 222 is deposited on the seed layer. In some embodiments, a planarization tool 110 is used to planarize the bit line conductive structure 222 after its formation.

[0123] like Figure 4C and 4D As shown, ESL 234 can be formed on and / or above dielectric layer 232 (e.g. Figure 4C (as shown) and on and / or above the bit line conductive structure 222 (such as Figure 4D(As shown). Dielectric layer 236 can be formed above and / or on ESL 234. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit ESL 234 and / or dielectric layer 236. In some embodiments, planarization tool 110 is used to planarize ESL 234 and / or dielectric layer 236 after formation of ESL 234 and / or dielectric layer 236.

[0124] like Figure 4E As shown, a notch 402 is formed to extend through dielectric layer 236, through ESL 234, and through dielectric layer 232 to memory structure 204. The notch 402 can be formed in the z-direction of semiconductor device 200 such that it extends from the top surface of dielectric layer 236 to the top surface of memory structure 204. The top surface of memory structure 204 can be exposed via the notch 402.

[0125] In some embodiments, the pattern in the photoresist layer is used to etch dielectric layer 236, ESL 234, and / or dielectric layer 232 to form notch 402. In these embodiments, deposition tool 102 can be used to form the photoresist layer on dielectric layer 236. Exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 can be used to etch dielectric layer 236, ESL 234, and / or dielectric layer 232 based on the pattern to form notch 402. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming notch 402 based on the pattern.

[0126] like Figure 4F As shown, a liner layer 244 is formed on the sidewalls and bottom surface of the recess 402 (where the bottom surface of the recess 402 may correspond to the top surface of the storage structure 204). The liner layer 244 can be deposited conformally, such that the liner layer 244 conforms to the contour of the recess 402. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and a combination of these techniques. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the liner layer 244.

[0127] like Figure 4FAs further shown, the notch 402 can be filled with source / drain interconnects 218 on the backing layer 244. The source / drain interconnects 218 extend in the z-direction through dielectric layer 232, ESL 234, and / or dielectric layer 236. Deposition tool 102 and / or electroplating tool 112 can be used with CVD, PVD, ALD, electroplating, or other techniques. Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the source / drain interconnect 218. In some embodiments, a seed layer is first deposited on the liner layer 244, and the source / drain interconnect 218 is deposited on the seed layer. In some embodiments, a planarization tool 110 is used to planarize the dielectric layer 236 and / or the top surface of the source / drain interconnect 218 after the formation of the source / drain interconnect 218.

[0128] like Figure 4G As shown, ESL238 can be formed on and / or above dielectric layer 236 and / or on and / or above source / drain interconnect 218. Dielectric layer 240 can be formed on and / or above ESL 238. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit ESL 238 and / or dielectric layer 240. In some embodiments, planarization tool 110 is used to planarize ESL 238 and / or dielectric layer 240 after formation.

[0129] like Figure 4H As shown, source / drain regions 206 and associated pad layers 246 are formed on and / or over source / drain interconnects 218. Source / drain regions 206 and associated pad layers 246 may be formed in and / or through dielectric layers 240 and / or ESL 238.

[0130] To form the source / drain region 206 and the associated pad layer 246, a notch may be formed through the dielectric layer 240 and / or through the ESL 238 to the source / drain interconnect 218. The top surface of the source / drain interconnect 218 is exposed via the notch. The notch may be formed in the z-direction from the top surface of the dielectric layer 240 to the top surface of the source / drain interconnect 218.

[0131] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 240 and / or ESL 238 to form a notch. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 240 and / or ESL 238 based on the pattern to form a notch. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based notch formation.

[0132] The backing layer 246 can be formed on the sidewalls and bottom surface of the notch. The backing layer 246 can be deposited conformally, such that the backing layer 246 conforms to the contour of the notch. The backing layer 246 can also be formed on the top surface of the dielectric layer 240. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding technology. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the liner layer 246.

[0133] The notch can then be filled with the source / drain region 206 on the backing layer 246. Thus, the source / drain region 206 is formed on the source / drain interconnect 218. The deposition tool 102 and / or electroplating tool 112 can be used with CVD, PVD, ALD, electroplating, or other technologies. Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the source / drain region 206. In some embodiments, a seed layer is first deposited on the liner layer 246, and the source / drain region 206 is deposited on the seed layer.

[0134] like Figure 4I As shown, after depositing the pad layer 246 and the source / drain region 206, a planarization tool 110 can be used to planarize the semiconductor device 200. The planarization tool 110 can be performed to remove the material of the pad layer 246 and the source / drain region 206 from the top surface of the dielectric layer 240.

[0135] like Figure 4J and 4K As shown, additional material is deposited on the dielectric layer 240 after the formation of the source / drain region 206. The deposition tool 102 can be used with PVD, ALD, CVD, and other techniques. Figure 1Another type of deposition technique and / or another suitable deposition technique is described to deposit additional material on dielectric layer 240. In some embodiments, planarization tool 110 is used to planarize dielectric layer 240 after depositing additional material.

[0136] like Figure 4L As shown, notches 404 and 406 are formed to extend through dielectric layer 240, through ESL 238, through dielectric layer 236, and / or through ESL 234 to bit line conductive structure 222. Notches 404 and 406 may be formed in the z-direction of semiconductor device 200 such that notches 404 and 406 extend from the top surface of dielectric layer 240 to the top surface of bit line conductive structure 222. The top surface of bit line conductive structure 222 may be exposed via notches 404 and 406.

[0137] In some embodiments, the pattern in the photoresist layer is used to etch dielectric layers 240, ESL 238, dielectric layer 236, and / or ESL 234 to form notches 404 and 406. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch dielectric layers 240, ESL 238, dielectric layer 236, and / or ESL 234 based on the pattern to form notches 404 and 406. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, hard mask layers are used as an alternative technique to pattern-forming notches 404 and 406.

[0138] like Figure 4M As shown, a padding layer 252 is formed on the sidewalls and bottom surface of the notch 404 (where the bottom surface of the notch 404 may correspond to the top surface of the bitline conductive structure 222). The padding layer 252 can be conformally deposited such that the padding layer 252 conforms to the contour of the notch 404. A padding layer 254 is formed on the sidewalls and bottom surface of the notch 406 (where the bottom surface of the notch 406 may correspond to the top surface of the bitline conductive structure 222). The padding layer 254 can be conformally deposited such that the padding layer 254 conforms to the contour of the notch 406. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and in combination Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the liner layers 252 and / or 254.

[0139] like Figure 4M As further shown, notch 404 can be filled with source / drain interconnects 224 on the liner layer 252. The source / drain interconnects 224 extend in the z-direction through dielectric layer 240, through ESL 238, through dielectric layer 236, and / or through ESL 234. Notch 406 can be filled in the liner layer 254 with source / drain interconnects 226. The source / drain interconnects 226 extend in the z-direction through dielectric layer 240, through ESL 238, through dielectric layer 236, and / or through ESL 234. Deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and in combination with... Figure 1 Another deposition technique and / or another suitable deposition technique are described to deposit source / drain interconnects 224 and / or 226. In some embodiments, a seed layer is first deposited on a liner layer 252, and the source / drain interconnect 224 is deposited on the seed layer. In some embodiments, a seed layer is first deposited on a liner layer 254, and the source / drain interconnect 226 is deposited on the seed layer.

[0140] In some embodiments, the planarization tool 110 is used to planarize the top surface of the dielectric layer 240, the top surface of the source / drain interconnect 224, and / or the top surface of the source / drain interconnect 226 after the source / drain interconnects 224 and 226 are formed.

[0141] like Figure 4N As shown, additional material is deposited on dielectric layer 240 after forming source / drain interconnects 224 and / or 226. Deposition tool 102 can be used with PVD, ALD, CVD, and other technologies. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit additional material on dielectric layer 240. In some embodiments, planarization tool 110 is used to planarize dielectric layer 240 after depositing additional material.

[0142] like Figure 4O As shown, notches 408 and 410 are formed through dielectric layer 240. Notch 408 can be formed to source / drain interconnect 224, such that the top surface of source / drain interconnect 224 is exposed through notch 408. Notch 410 can be formed to source / drain interconnect 226, such that the top surface of source / drain interconnect 226 is exposed through notch 410.

[0143] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 240 to form notches 408 and 410. In these embodiments, a deposition tool 102 can be used to form the photoresist layer on the dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 240 based on the pattern to form notches 408 and 410. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming notches 408 and 410 based on the pattern.

[0144] like Figure 4P As shown, a liner layer 256 is formed on the sidewalls and bottom surface of the notch 408 (where the bottom surface of the notch 408 may correspond to the top surface of the source / drain interconnect 224). The liner layer 256 can be conformally deposited such that the liner layer 256 conforms to the contour of the notch 408. A liner layer 258 is formed on the sidewalls and bottom surface of the notch 410 (where the bottom surface of the notch 410 may correspond to the top surface of the source / drain region 210). The liner layer 258 can be conformally deposited such that the liner layer 258 conforms to the contour of the notch 410. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and combined technologies. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the liner layers 256 and / or 258.

[0145] like Figure 4P As further shown, the notch 408 can be filled by the source / drain region 208 of the transistor structure 248 of the memory cell structure 202 on the pad layer 256. The notch 410 can be filled by the source / drain region 210 on the pad layer 258. The deposition tool 102 and / or the electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and combination Figure 1 Another deposition technique and / or another suitable deposition technique are described to deposit source / drain regions 208 and / or 210. In some embodiments, a seed layer is first deposited on a liner layer 256, and the source / drain region 208 is deposited on the seed layer. In some embodiments, a seed layer is first deposited on a liner layer 258, and the source / drain region 210 is deposited on the seed layer.

[0146] In some embodiments, the planarization tool 110 is used to planarize the top surface of the dielectric layer 240, the top surface of the source / drain region 208, and / or the top surface of the source / drain region 210 after the source / drain regions 208 and 210 are formed.

[0147] like Figure 4Q As shown, the notch 412 is formed through the dielectric layer 240 to the top surface of the source / drain region 206, such that the top surface of the source / drain region 206 is exposed via the notch 412. The notch 412 is formed between the source / drain region 208 and the source / drain region 210.

[0148] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 240 to form a notch 412. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 240 based on the pattern to form the notch 412. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the notch 412 based on the pattern.

[0149] like Figure 4R As shown, a channel layer 212 is formed, and a gate dielectric layer 216 is formed on the channel layer 212. A portion 212b of the channel layer 212 is formed on the sidewall and bottom surface of the notch 412 (wherein the bottom surface of the notch 412 corresponds to the top surface of the source / drain region 206). A portion 212a of the channel layer 212 is formed on and / or above the top surface of the dielectric layer 240. A portion 216b of the gate dielectric layer 216 is formed on the sidewall and bottom surface of the notch 412. A portion 216a of the gate dielectric layer 216 is formed on and / or above the top surface of the dielectric layer 240. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding technology. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to conformally deposit the channel layer 212 and / or the gate dielectric layer 216. Thus, portions 212b of the channel layer 212 and 216b of the gate dielectric layer 216 conform to the cross-sectional profile of the notch 412. Therefore, portions 212b of the channel layer 212 and 216b of the gate dielectric layer 216 on the sidewalls of the notch 412 extend primarily in the z-direction of the semiconductor device 200.

[0150] like Figure 4S As shown, a portion 212a of the channel layer 212 and a portion 216a of the gate dielectric layer 216 are formed on and / or above the top surfaces of the source / drain regions 208 and 210. The portion 212a of the channel layer 212 and a portion 216a of the gate dielectric layer 216 may also be formed on the top surface of the dielectric layer 240 between the source / drain regions 208 and 210, such that the portion 212a of the channel layer 212 and the portion 216a of the gate dielectric layer 216 extend continuously between the source / drain regions 208 and 210.

[0151] like Figure 4T As shown, the notch 412 is filled with a sacrificial layer 414 located on a portion 212b of the channel layer 212 and a portion 216b of the gate dielectric layer 216. The sacrificial layer 414 comprises one or more materials having high etch selectivity relative to the material of the gate dielectric layer 216. This allows the sacrificial layer 414 to be subsequently removed by etching without requiring (or minimally requiring) removal of the gate dielectric layer 216. Examples of materials used for the sacrificial layer 414 include amorphous silicon (α-Si) and / or silicon nitride (Si). x N y , such as Si3N4, etc.

[0152] Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and in combination Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the sacrificial layer 414. In some embodiments, a planarization tool 110 is used to planarize the sacrificial layer 414 after deposition. Planarization may stop at a portion 216a of the gate dielectric layer 216, such that the portion 216a of the gate dielectric layer 216 remains above the top surface of the dielectric layer 240.

[0153] like Figure 4U As shown, dielectric layer 242 is formed above dielectric layer 240. Dielectric layer 242 can be formed on and / or above portion 216a of gate dielectric layer 216 and / or on and / or above sacrificial layer 414. Sacrificial layer 414 serves as a placeholder layer and enables dielectric layer 242 to be formed without filling notch 412 with dielectric layer 242. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding technology. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the dielectric layer 242. In some embodiments, a planarization tool 110 is used to planarize the dielectric layer 242 after deposition.

[0154] like Figure 4VAs shown, the notch 416 is formed to extend through the dielectric layer 242 to the top surface of the sacrificial layer 414, such that the top surface of the sacrificial layer 414 is exposed via the notch 416.

[0155] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 242 to form a notch 416. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 242. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 242 based on the pattern to form the notch 416. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the notch 416 based on the pattern.

[0156] like Figure 4W As shown, the sacrificial layer 414 is removed via a notch 416, such that the notch 416 extends along a portion 212b of the channel layer 212 and along a portion 216b of the gate dielectric layer 216. An etching tool 108 can be used to etch the sacrificial layer 414 to remove it from the semiconductor device 200. An etchant with a high etching rate for the material of the sacrificial layer 414 and a low etching rate for the material of the gate dielectric layer 216 can be used to etch the sacrificial layer 414. This minimizes the removal of material from the gate dielectric layer 216 during the etching of the sacrificial layer 414.

[0157] After removing the sacrificial layer 414, the notch 416 can have a dual damascene profile. The via portion of the dual damascene profile can correspond to the portion of the notch 416 extending into the dielectric layer 240 along the channel layer 212 portion 212b and along the gate dielectric layer 216b portion 216b. The trench portion of the dual damascene profile can correspond to the portion of the notch 416 extending into the dielectric layer 242.

[0158] like Figure 4X As shown, the notch 416 is filled with the gate electrode 214 and the word line conductive structure 220 located on and / or above the gate electrode 214. The gate electrode 214 may be formed in the via portion of the dual damascene profile of the notch 416, such that the gate electrode 214 is formed on and / or above the portion 212b of the channel layer 212 and the portion 216b of the gate dielectric layer 216. The gate electrode 214 extends in the z-direction of the semiconductor device 200. The word line conductive structure 220 is formed on the gate electrode 214 in the trench portion of the dual damascene profile of the notch 416.

[0159] Deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and combination Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the gate electrode 214 and / or the word line conductive structure 220. In some embodiments, a seed layer is first deposited on the gate dielectric layer 216 and on the sidewalls of the notch 416 corresponding to the dielectric layer 242, and the gate electrode 214 and the word line conductive structure 220 are deposited on the seed layer. In some embodiments, a planarization tool 110 is used to planarize the word line conductive structure 220 after the gate electrode 214 and the word line conductive structure 220 are deposited.

[0160] As mentioned above, providing Figures 4A to 4X As an example. Other examples can be found related to... Figures 4A to 4X The descriptions are different.

[0161] Figure 5A and Figure 5B This is a schematic diagram of an exemplary embodiment 500 of the storage cell structure 202 described herein. Figure 5A A perspective view of an exemplary embodiment 500 of the storage cell structure 202 is shown, and Figure 5B An exemplary embodiment 500 of the storage cell structure 202 is shown along... Figure 5A A cross-sectional view of line AA in the diagram.

[0162] like Figure 5A and Figure 5B As shown, an exemplary embodiment 500 of the storage cell structure 202 includes... Figures 2A to 2C and Figures 3A to 3D The exemplary embodiment 300 of the memory cell structure 202 shown has a similar structure and layer arrangement. However, in the exemplary embodiment 500 of the memory cell structure 202, the source / drain interconnect 218 is omitted from the memory cell structure 202. Instead, the source / drain region 206 extends fully between a portion 212b of the channel layer 212 (i.e., below the bottom surface of the gate electrode 214) and the top surface of the memory structure 204, such that the source / drain region 206 is in physical contact with the memory structure 204.

[0163] Including the source / drain interconnect 218 in the exemplary embodiment 300 of the memory cell structure 202 allows for greater control over the outline of the memory cell structure 202 during its fabrication. However, omitting the source / drain interconnect 218 in the exemplary embodiment 500 of the memory cell structure 202 allows the memory cell structure 202 to be formed using fewer photolithography operations and associated photomasks.

[0164] like Figure 5A and Figure 5B As further shown, the source / drain region 206 can be tapered between its top and bottom surfaces. Therefore, the source / drain region 206 can have a width greater than the cross-sectional width of its bottom surface (in...). Figure 5B The width of the top surface cross section (indicated by dimension D7) is larger than that of the other two dimensions. Figure 5B (The dimension is indicated as D6). Due to its conical shape, the cross-sectional width of the source / drain region 206 can decrease from the top surface to the bottom surface. The conical shape of the source / drain region 206 may be due to the etching rate at the top of the notch in which the source / drain region 206 is formed being greater than the etching rate at the bottom of the notch in which the source / drain region 206 is formed.

[0165] As mentioned above, providing Figure 5A and Figure 5B As an example. Other examples can be found related to... Figure 5A and Figure 5B The descriptions are different.

[0166] Figures 6A to 6F This is a schematic diagram of an exemplary embodiment 600 that forms the storage cell structure 202 described herein. Specifically, the exemplary embodiment 600 includes forming... Figure 5A and Figure 5B The illustrated storage cell structure 202 is an example of an exemplary implementation 500. In some embodiments, combined with Figures 6A to 6F One or more of the described semiconductor processing operations can be performed using one or more of the semiconductor processing tools 102-112 described herein. In some implementations, another semiconductor processing tool can be used to perform the combined operation. Figures 6A to 6F One or more of the semiconductor processing operations described. Figures 6A to 6F Some of them are from along Figure 2A The cross-sectional view of line AA in the diagram is shown, and Figures 6A to 6F Some of them are from along Figure 2A The cross-sectional view of line BB is shown in the figure.

[0167] Turning Figure 6A It can perform a combination Figures 4A to 4D Similar semiconductor processing operations are described to form memory structure 204, bit line conductive structure 222 (not shown), dielectric layer 228, ESL, dielectric layer 232, ESL 234, dielectric layer 236, and pad layer 250 (not shown).

[0168] like Figure 6BAs shown, ESL 238 can be formed on and / or above dielectric layer 236, and dielectric layer 240 can be used for bonding. Figure 4G A similar manner as described is formed on and / or above ESL 238. However, the formation of source / drain interconnect 218 is omitted before the formation of ESL 238 and dielectric layer 236.

[0169] like Figure 6C As shown, the notch 602 is formed through dielectric layer 240, through ESL 238, through dielectric layer 236, through ESL 234, and / or through dielectric layer 232 to the memory structure 204. The top surface of the memory structure 204 is exposed via the notch 602. The notch 602 can be formed in the z-direction from the top surface of dielectric layer 240 to the top surface of memory structure 204.

[0170] In some embodiments, the pattern in the photoresist layer is used to etch dielectric layers 240, ESL 238, 236, ESL 234, and / or 232 to form a notch 602. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch dielectric layers 240, ESL 238, 236, ESL 234, and / or 232 based on the pattern to form the notch 602. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming notch 602.

[0171] like Figure 6D As shown, a backing layer 246 is formed on the sidewalls and bottom surface of the notch 602. The backing layer 246 can be deposited conformally, such that the backing layer 246 conforms to the contour of the notch 602. The backing layer 246 can also be formed on the top surface of the dielectric layer 240. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and bonding technology. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the liner layer 246.

[0172] like Figure 6DAs further shown, the notch 602 can be filled by the source / drain region 206 on the pad layer 246. Thus, the source / drain region 206 is formed on the memory structure 204, rather than on the source / drain interconnect 218. The deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and in combination... Figure 1 Another deposition technique and / or another suitable deposition technique is described to deposit the source / drain region 206. In some embodiments, a seed layer is first deposited on the liner layer 246, and the source / drain region 206 is deposited on the seed layer.

[0173] like Figure 6E As shown, after depositing the pad layer 246 and the source / drain region 206, a planarization tool 110 can be used to planarize the semiconductor device 200. The planarization tool 110 can be performed to remove the material of the pad layer 246 and the source / drain region 206 from the top surface of the dielectric layer 240.

[0174] like Figure 6F As shown, a combination can be performed. Figure 4J-4X Similar semiconductor processing operations are described to form source / drain regions 208 and 210 (not shown), channel layer 212, gate electrode 214, gate dielectric layer 216, word line conductive structure 220, source / drain interconnects 224 and 226 (not shown), additional material for dielectric layer 240, dielectric layer 242, and pad layers 252, 254, 256, and 258 (not shown).

[0175] As mentioned above, providing Figures 6A to 6F As an example. Other examples can be found related to... Figures 6A to 6F The descriptions are different.

[0176] Figure 7A and Figure 7B This is a schematic diagram of an exemplary embodiment 700 of the storage cell structure 202 described herein. Figure 7A A perspective view of an exemplary embodiment 700 of the storage cell structure 202 is shown, and Figure 7B An exemplary embodiment 700 of the storage cell structure 202 is shown along... Figure 7A A cross-sectional view of line AA in the diagram.

[0177] like Figure 7A and Figure 7B As shown, an exemplary embodiment 700 of the storage cell structure 202 includes... Figures 2A to 2C and Figures 3A to 3DThe exemplary embodiment 300 of the memory cell structure 202 shown has a similar structure and layer arrangement. However, in the exemplary embodiment 700 of the memory cell structure 202, one or more diffusion barrier layers are included around the memory cell structure 202. For example, a diffusion barrier layer 702 may be located above the source / drain region 206 and around the bottom of a portion 212b of the channel layer 212 (and thus around the bottom of the gate electrode 214). As another example, a diffusion barrier layer 704 may be located below the source / drain regions 208 and / or 210 and around the middle of a portion 212b of the channel layer 212 (and thus around the middle of the gate electrode 214).

[0178] As described above, the channel layer 212 may include one or more metal oxide semiconductor materials, such as IGZO and / or ITO. These types of materials may be susceptible to contamination from the diffusion of elements and / or molecules such as oxygen (O), nitrogen (N), hydrogen (H), and / or water (H2O). These contaminants can create vacancy defects in the metal oxide semiconductor material and the channel layer 212, leading to increased leakage current in the memory cell structure 202. Diffusion barrier layers 702 and 704 may be located around the channel layer 212 of the memory cell structure 202 to prevent or reduce the possibility of these contaminants and other contaminants diffusing into the channel layer 212 from below the diffusion barrier layer 702 and above the diffusion barrier layer 704.

[0179] In some embodiments, additional diffusion barrier layers and / or diffusion barrier layers 702 and / or 704 may be arranged in different locations within the semiconductor device 200. For example, diffusion barrier layer 702 (and / or another diffusion barrier layer) may be located below memory structure 204. As another example, diffusion barrier layer 704 (and / or another diffusion barrier layer) may be located above word line conductive structure 220.

[0180] The diffusion barrier layers 702 and / or 704 may each comprise one or more hydrogen-blocking materials, one or more nitrogen-blocking materials, and / or one or more oxygen-blocking materials. Examples of these materials include alumina (Al₂O₃). x O y For example, Al2O3), silicon carbide (SiOC), chromium oxide (Cr). x O y For example, Cr2O3), another oxide-containing material and / or another material, etc.

[0181] As mentioned above, providing Figure 7A and Figure 7B As an example. Other examples can be found related to... Figure 7A and Figure 7B The descriptions are different.

[0182] Figures 8A to 8D This is a schematic diagram of an exemplary embodiment 800 that forms the storage cell structure 202 described herein. Specifically, the exemplary embodiment 800 includes forming... Figure 7A and Figure 7B The illustrated storage cell structure 202 is an example of an exemplary implementation 700. In some embodiments, combined with Figures 8A to 8D One or more of the described semiconductor processing operations can be performed using one or more of the semiconductor processing tools 102-112 described herein. In some implementations, another semiconductor processing tool can be used to perform the combined operation. Figures 8A to 8D One or more of the semiconductor processing operations described. Figures 8A to 8D Some of them are from along Figure 2A The cross-sectional view of line AA in the diagram is shown, and Figures 8A to 8D Some of them are from along Figure 2A The cross-sectional view of line BB is shown in the figure.

[0183] Turning Figure 8A It can perform a combination Figures 4A to 4I Similar semiconductor processing operations are described to form memory structure 204, source / drain region 206, source / drain interconnect 218, bit line conductive structure 222 (not shown), dielectric layer 228, ESL, dielectric layer 232, ESL 234, dielectric layer 236, ESL 238, dielectric layer 240, substrate 244, substrate 246, and substrate 250 (not shown).

[0184] like Figure 8B As shown, the additional portion of dielectric layer 240 is bonded Figure 4J and Figure 4K A similar manner as described is formed on and / or above the source / drain region 206. However, diffusion barrier layers 702 and 704 are additionally formed during the formation of additional portions of dielectric layer 240. For example, diffusion barrier layer 702 may be formed on and / or above dielectric layer 240 and / or on and / or above source / drain region 206. A first additional portion of dielectric layer 240 may be formed on and / or above diffusion barrier layer 702. Diffusion barrier layer 704 may be formed on and / or above the first additional portion of dielectric layer 240. A second additional portion of dielectric layer 240 may be formed on and / or above diffusion barrier layer 704.

[0185] Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and in combination Figure 1Another type of deposition technique and / or another suitable deposition technique is described to deposit additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704. In some embodiments, planarization tool 110 is used to planarize the additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704 after the formation of the additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704.

[0186] After forming additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704, source / drain regions 208 and 210 (not shown), source / drain interconnects 224 and 226 (not shown), and pad layers 252, 254, 256, and 258 (not shown) can be bonded together. Figures 4L to 4P It is formed in a similar manner as described.

[0187] like Figure 8C As shown, a notch 802 is formed to extend through an additional portion of the dielectric layer 240, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 to the source / drain region 206. The notch 802 can be formed after the source / drain regions 208 and 210 (not shown). The top surface of the source / drain region 206 is exposed via the notch 802. The notch 802 can be formed in the z-direction from the top surface of a second additional portion of the dielectric layer 240 to the top surface of the source / drain region 206.

[0188] In some embodiments, the pattern in the photoresist layer is used to etch additional portions of the dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704 to form a notch 802. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on a second additional portion of the dielectric layer 240. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch additional portions of the dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704 based on the pattern to form the notch 802. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming notch 802.

[0189] like Figure 8D As shown, a combination can be performed. Figures 4R to 4XSimilar semiconductor processing operations are described to form a channel layer 212, a gate electrode 214, and a gate dielectric layer 216 in the notch 802, and to form a word line conductive structure 220 and a dielectric layer 242.

[0190] As mentioned above, providing Figures 8A to 8D As an example. Other examples can be found related to... Figures 8A to 8D The descriptions are different.

[0191] Figure 9A and Figure 9B This is a schematic diagram of an exemplary embodiment 900 of the storage cell structure 202 described herein. Figure 9A A perspective view of an exemplary embodiment 900 of the storage cell structure 202 is shown, and Figure 9B An exemplary embodiment 900 of the storage cell structure 202 is shown along... Figure 9A A cross-sectional view of line AA in the diagram.

[0192] like Figure 9A and Figure 9B As shown, an exemplary embodiment 900 of the storage cell structure 202 includes... Figure 5A and Figure 5B The exemplary embodiment 500 of the memory cell structure 202 shown has a similar structure and layer arrangement. Except for the tapered source / drain region 206 and the omission of the source / drain interconnect 218, in the exemplary embodiment 900 of the memory cell structure 202, diffusion barrier layers 702 and / or 704 are disposed around a portion 212b of the channel layer 212, which allows one or more metal-oxide-semiconductor materials to be used in the combination of the channel layer 212 and the tapered source / drain region 206.

[0193] As mentioned above, providing Figure 9A and Figure 9B As an example. Other examples can be found related to... Figure 9A and Figure 9B The descriptions are different.

[0194] Figures 10A to 10D This is a schematic diagram of an exemplary embodiment 1000 that forms the storage cell structure 202 described herein. Specifically, the exemplary embodiment 1000 includes forming... Figure 9A and Figure 9B The exemplary implementation 900 of the storage cell structure 202 shown is an example. In some embodiments, in conjunction with Figures 10A to 10D One or more of the described semiconductor processing operations can be performed using one or more of the semiconductor processing tools 102-112 described herein. In some implementations, another semiconductor processing tool can be used to perform the combined operation. Figures 10A to 10DOne or more of the semiconductor processing operations described. Figures 10A to 10D Some of them are from along Figure 2A The cross-section of line AA in the diagram is shown, and Figures 10A to 10D Some of them are from along Figure 2A It is shown in the sectional view of line BB.

[0195] Turning Figure 10A It can perform a combination Figures 4A to 4D and Figures 6A to 6E Similar semiconductor processing operations are described to form memory structure 204, source / drain regions 206 on memory structure 204 (wherein source / drain interconnect 218 is omitted), bit line conductive structure 222 (not shown), dielectric layer 228, ESL, dielectric layer 232, ESL 234, dielectric layer 236, ESL 238, dielectric layer 240, substrate 246, and substrate 250 (not shown).

[0196] like Figure 10B As shown, the additional portion of dielectric layer 240 is bonded Figure 4J and 4K A similar manner as described is formed on and / or above the source / drain region 206. However, diffusion barrier layers 702 and 704 are additionally formed during the formation of additional portions of dielectric layer 240. For example, diffusion barrier layer 702 may be formed on and / or above dielectric layer 240 and / or on and / or above source / drain region 206. A first additional portion of dielectric layer 240 may be formed on and / or above diffusion barrier layer 702. Diffusion barrier layer 704 may be formed on and / or above the first additional portion of dielectric layer 240. A second additional portion of dielectric layer 240 may be formed on and / or above diffusion barrier layer 704.

[0197] Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and in combination Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704. In some embodiments, planarization tool 110 is used to planarize the additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704 after the formation of the additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704.

[0198] After forming additional portions of dielectric layer 240, diffusion barrier layer 702, and / or diffusion barrier layer 704, source / drain regions 208 and 210 (not shown), source / drain interconnects 224 and 226 (not shown), and pad layers 252, 254, 256, and 258 (not shown) can be bonded together. Figures 4L to 4PIt is formed in a similar manner as described.

[0199] like Figure 10C As shown, a notch 1002 is formed to extend through an additional portion of the dielectric layer 240, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 to the source / drain region 206. The notch 1002 may be formed after the source / drain regions 208 and 210 (not shown). The top surface of the source / drain region 206 is exposed via the notch 1002. The notch 1002 may be formed in the z-direction from the top surface of a second additional portion of the dielectric layer 240 to the top surface of the source / drain region 206.

[0200] In some embodiments, the pattern in the photoresist layer is used to etch additional portions of the dielectric layer 240, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 to form a notch 1002. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on a second additional portion of the dielectric layer 240. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch additional portions of the dielectric layer 240, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 based on the pattern to form the notch 1002. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming notch 1002.

[0201] like Figure 10D As shown, a combination can be performed. Figures 4R to 4X Similar semiconductor processing operations are described to form a channel layer 212, a gate electrode 214, and a gate dielectric layer 216 in the notch 1002, as well as to form a word line conductive structure 220 and a dielectric layer 242.

[0202] As mentioned above, providing Figures 10A to 10D As an example. Other examples can be found related to... Figures 10A to 10D The descriptions are different.

[0203] Figure 11 This is a schematic diagram of the exemplary element or device 1100 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die delivery tool 114 may include one or more devices 1100 and / or one or more element devices 1100. Figure 11As shown, device 1100 may include bus 1110, processor 1120, memory 1130, input element 1140, output element 1150 and / or communication element 1160.

[0204] Bus 1110 may include one or more elements capable of wired and / or wireless communication between components or devices 1100. Bus 1110 can... Figure 11 Two or more elements are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1110 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1120 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing element. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 1120 may include one or more processors that can be programmed to perform one or more operations described elsewhere herein.

[0205] Memory 1130 may include volatile and / or non-volatile memory. For example, memory 1130 may include random access memory (RAM), read-only memory (ROM), hard disk, and / or other types of memory (e.g., flash memory, magnetic storage, and / or optical storage). Memory 1130 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a Universal Serial Bus connection). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information related to the operation of device 1100, one or more instructions, and / or software (e.g., one or more software applications). In some implementations, memory 1130 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120), for example, via bus 1110. The communicative coupling between processor 1120 and memory 1130 enables processor 1120 to read and / or process information stored in memory 1130 and / or store information in memory 1130.

[0206] Input element 1140 enables device 1100 to receive input, such as user input and / or sensed input. For example, input element 1140 may include a touchscreen, keyboard, touchpad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output element 1150 enables device 1100 to provide output (e.g., via a display, speaker, and / or LED). Communication element 1160 enables device 1100 to communicate with other devices via wired and / or wireless connections. For example, communication element 1160 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0207] Device 1100 may perform one or more of the operational processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1130) may store a set of instructions (e.g., one or more instructions or code) to be executed by processor 1120. Processor 1120 may execute a set of instructions to perform one or more of the operations described herein. In some implementations, execution of the set of instructions by one or more processors 1120 causes one or more processors 1120 and / or device 1100 to perform one or more operational processes described herein. In some implementations, hardwired circuitry may be used in place of or in combination with instructions to perform one or more of the operations or processes described herein. Alternatively or additionally, processor 1120 may be configured to perform one or more operational processes described herein. Therefore, the implementations described herein are not limited to any particular combination of hardware circuitry and software.

[0208] Figure 11 The number and arrangement of components shown are provided as an example. Device 1100 may include more than Figure 11 The additional elements, fewer elements, different elements, or elements arranged differently shown. Alternatively, a group of elements (e.g., one or more elements) in device 1100 may perform one or more functions described as being performed by another group of elements in device 1100.

[0209] Figure 12 This is a flowchart of an exemplary process 1200 associated with forming the memory cell structure described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112) are used to perform the process. Figure 12 One or more process blocks. Alternatively, Figure 12One or more process blocks can be executed using one or more elements in device 1100, such as processor 1120, memory 1130, input element 1140, output element 1150 and / or communication element 1160.

[0210] like Figure 12 As shown, process 1200 may include a first source / drain region (block 1210) of a transistor structure forming a memory cell structure in a semiconductor device. For example, one or more of semiconductor processing tools 102-112 may be used to form a first source / drain region 206 of a transistor structure 248 for a memory cell structure 202 in a semiconductor device 200, as described herein.

[0211] like Figure 12 As further shown, process 1200 may include forming a dielectric layer (block 1220) over the first source / drain region. For example, one or more of semiconductor processing tools 102-112 may be used to form a dielectric layer 240 on the first source / drain region 206, as described herein.

[0212] like Figure 12 As further shown, process 1200 may include forming a second source / drain region (block 1230) in the dielectric layer. For example, one or more of semiconductor processing tools 102-112 may be used to form the second source / drain region 208 in the dielectric layer 240, as described herein.

[0213] like Figure 12 As further shown, process 1200 may include forming a notch (block 1240) in the dielectric layer adjacent to the second source / drain region. For example, one or more of semiconductor processing tools 102-112 may be used to form a notch 412 in the dielectric layer 240 adjacent to the second source / drain region 208, as described herein. In some embodiments, the first source / drain region 206 is exposed via the notch 412.

[0214] like Figure 12 As further shown, process 1200 may include forming a channel layer (block 1250) on the sidewalls and bottom surface of the notch. For example, one or more of semiconductor processing tools 102-112 may be used to form channel layer 212 on the sidewalls and bottom surface of notch 412, as described herein.

[0215] like Figure 12 As further shown, process 1200 may include forming a gate dielectric layer (block 1260) on the channel layer in the notch. For example, one or more of semiconductor processing tools 102-112 may be used to form a gate dielectric layer 216 on the channel layer 212 in the notch 412, as described herein.

[0216] like Figure 12 As further shown, process 1200 may include forming a gate electrode on the gate dielectric layer (block 1270). For example, one or more of semiconductor processing tools 102-112 may be used to form a gate electrode 214 on the gate dielectric layer 216, as described herein.

[0217] Process 1200 may include other implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0218] In a first embodiment, dielectric layer 240 is a first dielectric layer, and notch 412 is a first notch. Process 1200 includes filling the first notch with a sacrificial layer 414 on the gate dielectric layer 216 before forming the gate electrode 214, forming a second dielectric layer 242 on the sacrificial layer 414, forming a second notch 416 in the second dielectric layer 242, removing the sacrificial layer 414 through the second notch 416, exposing the gate dielectric layer 216 in the second notch 416, and forming the gate electrode 214 on the gate dielectric layer 216 in the second notch 416.

[0219] In the second embodiment, alone or in combination with the first embodiment, process 1200 includes forming a word line conductive structure 220 on the gate electrode 214 in the second notch 416, wherein the word line conductive structure 220 is located in the second dielectric layer 242.

[0220] In the third embodiment, the channel layer 212 is formed alone or in combination with one or more of the first and second embodiments, including a first portion 21 of the channel layer 212 formed on the top surface of the second source / drain region 208 and a second portion 212b of the channel layer 212 formed on the sidewall and bottom surface of the notch 412.

[0221] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 1200 includes forming a third source / drain region 210 in dielectric layer 240, wherein forming notch 412 includes forming notch 412 between the second source / drain region 208 and the third source / drain region 210.

[0222] although Figure 12 An exemplary block diagram of process 1200 is shown, but in some embodiments, process 1200 includes... Figure 12 The blocks depicted in the diagram can be additional blocks, fewer blocks, different blocks, or blocks with different configurations. Alternatively, two or more blocks in process 1200 can be executed in parallel.

[0223] Thus, the semiconductor device includes a memory cell structure, which in turn includes a transistor structure and a memory structure. The gate electrode of the transistor structure extends in a direction generally perpendicular to the surface of the substrate of the semiconductor device, allowing the gate length to be increased with minimal to no increase in the horizontal or lateral dimensions of the memory cell structure. A channel layer surrounds the sidewalls and bottom surface of the gate electrode to form a cylindrical channel. This increases the channel area of ​​the transistor structure, enabling low leakage current in the memory cell structure and high lateral density of the memory cell structure within the semiconductor device. The low current leakage of the memory cell structure allows data stored in the memory cell structure and the memory structure to be retained for a longer period between refreshes, thereby reducing the power consumption of the memory cell structure and improving its power efficiency.

[0224] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure within the plurality of back-end dielectric layers. The memory cell structure includes a memory structure and a transistor structure above the memory structure. The transistor structure includes a first source / drain region, a second source / drain region above the first source / drain region, a gate electrode extending between the first source / drain region and the second source / drain region, and a channel layer extending between the first source / drain region and the second source / drain region, wherein the channel layer surrounds a periphery of the gate electrode. In one embodiment, a first portion of the channel layer surrounds the periphery of the gate electrode; and wherein a second portion of the channel layer is on the second source / drain region. In one embodiment, the first portion of the channel layer is disposed along one side of the second source / drain region. In one embodiment, the first portion of the channel layer is located below a bottom surface of the gate electrode; and wherein the first portion of the channel layer is located between the first source / drain region and the bottom surface of the gate electrode. In one embodiment, the semiconductor device further includes: a gate dielectric layer extending between the first source / drain region and the second source / drain region, wherein the gate dielectric layer surrounds the periphery of the gate electrode. In one embodiment, the semiconductor device further includes: a source / drain interconnect above the memory structure and below the first source / drain region, wherein the first source / drain region is coupled to the memory structure via the source / drain interconnect. In one embodiment, the first source / drain region is in direct physical contact with the memory structure. In one embodiment, the channel layer comprises a metal-oxide-semiconductor material; and wherein the semiconductor device further includes: one or more diffusion barrier layers located between the first source / drain region and the second source / drain region.

[0225] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a memory structure. The semiconductor device includes a first source / drain region, a second source / drain region above the first source / drain region, and a gate electrode having an elongated shape in a direction generally perpendicular to a plurality of back-end dielectric layers of the semiconductor device. The first source / drain region is located below a bottom surface of the gate electrode. The second source / drain region is adjacent to a sidewall of the gate electrode. The semiconductor device includes a channel layer surrounding the sidewalls and bottom surface of the gate electrode. In one embodiment, a first portion of the channel layer surrounds the sidewalls and bottom surface of the gate electrode, and a second portion of the channel layer extends in a direction generally parallel to the plurality of back-end dielectric layers. In one embodiment, the second portion of the channel layer contacts the second source / drain region. In one embodiment, a top surface of the gate electrode is located above the first portion of the channel layer, above the second portion of the channel layer, and above the second source / drain region. In one embodiment, the channel layer comprises a metal-oxide-semiconductor material; and the semiconductor device further comprises: a first diffusion barrier layer above the first source / drain region; and a second diffusion barrier layer below the second source / drain region. In one embodiment, the first diffusion barrier layer and the second diffusion barrier layer each comprise at least one of the following: aluminum oxide (Al₂O₃). x O y ), silicon dioxide (SiOC) or chromium oxide (Cr) x O y In one embodiment, the semiconductor device further includes: a gate dielectric layer located between the channel layer and the gate electrode, wherein the gate dielectric layer surrounds the sidewall and bottom surface of the gate electrode, and wherein the gate dielectric layer is positioned above the second source / drain region and the third source / drain region. In one embodiment, the semiconductor device further includes: a third source / drain region above the first source / drain region and adjacent to the sidewall of the channel layer, wherein the gate electrode is located between the second source / drain region and the third source / drain region.

[0226] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first source / drain region of a transistor structure for a memory cell structure in a semiconductor device. The method includes forming a dielectric layer over the first source / drain region. The method includes forming a second source / drain region in the dielectric layer. The method includes forming a notch in the dielectric layer adjacent to the second source / drain region, wherein the first source / drain region is exposed via the notch. The method includes forming a channel layer on the sidewalls and bottom surface of the notch. The method includes forming a gate dielectric layer on the channel layer in the notch. The method includes forming a gate electrode on the gate dielectric layer. In one embodiment, the dielectric layer is a first dielectric layer and the notch is a first notch; and the method further includes: filling the first notch with a sacrificial layer on the gate dielectric layer before forming the gate electrode; forming a second dielectric layer over the sacrificial layer; forming a second notch in the second dielectric layer; removing the sacrificial layer via the second notch such that the gate dielectric layer is exposed in the second notch; and forming the gate electrode on the gate dielectric layer in the second notch. In one embodiment, the method further includes: forming a word line conductive structure on the gate electrode in the second notch, wherein the word line conductive structure is located in the second dielectric layer. In one embodiment, forming the channel layer further includes: forming a first portion of the channel layer on the top surface of the second source / drain region; and forming a second portion of the channel layer on the sidewalls and the bottom surface of the notch.

[0227] As used in this article, "meeting the threshold" can refer to a value greater than, greater than or equal to, less than, less than or equal to, or equal to the threshold, depending on the context.

[0228] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by, Comprising: a plurality of back end dielectric layers; and a memory cell structure, in the plurality of back end dielectric layers, comprising: a memory structure; and a transistor structure, above the memory structure, comprising: a first source / drain region; a second source / drain region, above the first source / drain region; a gate electrode, extending between the first source / drain region and the second source / drain region; and a channel layer, extending between the first source / drain region and the second source / drain region, wherein the channel layer surrounds a perimeter of the gate electrode.

2. The semiconductor device according to claim 1, wherein a first portion of the channel layer surrounds the perimeter of the gate electrode; wherein a second portion of the channel layer is on the second source / drain region, the first portion of the channel layer being disposed along a side of the second source / drain region; the first portion of the channel layer is below a bottom surface of the gate electrode; and the first portion of the channel layer is between the first source / drain region and the bottom surface of the gate electrode. Further comprising:

3. The semiconductor device of claim 1, wherein a gate dielectric layer, extending between the first source / drain region and the second source / drain region, wherein the gate dielectric layer surrounds the perimeter of the gate electrode. Further comprising:

4. The semiconductor device of claim 1, wherein a source / drain interconnect, above the memory structure and below the first source / drain region, wherein the first source / drain region is coupled with the memory structure via the source / drain interconnect. the first source / drain region is in direct physical contact with the memory structure.

5. The semiconductor device of claim 1, wherein Comprising:

6. A semiconductor device, characterized by, a memory structure; a first source / drain region; a gate electrode, having an elongated shape in a direction perpendicular to a plurality of back end dielectric layers of the semiconductor device, wherein the first source / drain region is below a bottom surface of the gate electrode; a channel layer, surrounding a sidewall and the bottom surface of the gate electrode; a second source / drain region, above the first source / drain region and adjacent to the sidewall of the channel layer, wherein the gate electrode is adjacent to the second source / drain region. a first portion of the channel layer encircles the sidewall and the bottom surface of the gate electrode, and 7. The semiconductor device of claim 6, wherein, wherein a second portion of the channel layer extends in a direction parallel to the plurality of back end dielectric layers, the second portion of the channel layer being in contact with the second source / drain region, a top surface of the gate electrode being above the first portion of the channel layer, above the second portion of the channel layer, and above the second source / drain region. the channel layer comprises a metal-oxide-semiconductor material; and 8. The semiconductor device of claim 6, wherein, wherein the semiconductor device further comprises: a first diffusion barrier layer, above the first source / drain region; and a second diffusion barrier layer, below the second source / drain region. Further comprising: a gate dielectric layer, between the channel layer and the gate electrode, wherein the gate dielectric layer surrounds the sidewall and the bottom surface of the gate electrode, and 9. The semiconductor device of claim 6, wherein, wherein the gate dielectric layer is above the second source / drain region and a third source / drain region. Further comprising: ​ ​ 10. The semiconductor device of claim 6, wherein ​ a third source / drain region over the first source / drain region and adjacent the sidewall of the channel layer, wherein the gate electrode is between the second source / drain region and the third source / drain region.

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