Low-resistance separation trench gate silicon carbide VDMOS

Abstract

The utility model provides a low-resistance separation trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), which comprises a drift layer connected to a silicon carbide substrate, the drift layer is provided with a lug boss, and the lug boss is provided with a groove; the P-type well region is connected to the lug boss; the N-type source region is connected to the P-type well region; the P-type source region is connected to the drift layer, the lug boss, the P-type well region and the N-type source region; the low-resistance region is arranged in the groove; the lower part of the first insulating dielectric layer is arranged in the groove; a first groove is formed in the first insulating dielectric layer; the lower part of the second insulating dielectric layer is arranged in the groove; a second groove is formed in the second insulating dielectric layer; the first gate metal layer is arranged in the first groove; the second gate metal layer is arranged in the second groove; the lower part of the first source metal layer is arranged in the groove; the second source electrode metal layer is respectively connected with the P-type source region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; and the driving loss and the body diode loss of the device are reduced.

Description

Technical Field

[0001] This utility model relates to a low-resistance discrete trench gate silicon carbide VDMOS. Background Technology

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, widely used in electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements vary across different applications, but generally include higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage surge reliability, and short-circuit reliability), and lower body diode conduction loss. Given the increasingly demanding high-frequency applications of silicon carbide VDMOS in modular power supplies, and the growing proportion of switching losses and body diode losses in device power consumption, a solution is urgently needed. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a low-resistance split trench gate silicon carbide VDMOS, which constructs a first gate metal layer, a second gate metal layer and a Schottky base diode inside the device, thereby reducing the driving loss and body diode loss of the device.

[0004] In a first aspect, this utility model provides a low-resistance split trench gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate;

[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, the drift layer having protrusions and grooves;

[0007] The lower side of the P-type well region is connected to the upper side of the protrusion;

[0008] The N-type source region has its lower side connected to the upper side of the P-type well region;

[0009] The P-type source region is connected to the upper side of the drift layer; the inner side of the P-type source region is connected to the outer side of the protrusion, the outer side of the P-type well region, and the outer side of the N-type source region.

[0010] A low-resistance region is provided within the groove;

[0011] A first insulating dielectric layer is disposed at its lower part within the groove, and the lower side of the first insulating dielectric layer is connected to the upper side of the low-resistivity region. One side of the first insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region. A first trench is provided within the first insulating dielectric layer.

[0012] A second insulating dielectric layer is disposed at its lower part within the groove, and the lower side of the second insulating dielectric layer is connected to the upper side of the low-resistivity region. One side of the second insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region. A second trench is provided within the second insulating dielectric layer.

[0013] A first gate metal layer is disposed within the first trench;

[0014] A second gate metal layer is disposed within the second trench;

[0015] The first source metal layer has a lower part disposed in the groove, and the lower side of the first source metal layer is connected to the upper side of the low resistance region. The side of the first source metal layer is respectively connected to the other side of the first insulating dielectric layer and the other side of the second insulating dielectric layer.

[0016] The second source metal layer is connected to the P-type source region and the N-type source region respectively;

[0017] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0018] The advantages of this utility model are:

[0019] I. By setting a first gate metal and a second gate metal layer, this utility model reduces the gate structure size of the device and the gate-drain capacitance between the gate and the drain, thereby reducing the switching capacitance of the device and improving the switching speed of the device.

[0020] Second, a first source metal layer is constructed in the middle of the device, thereby constructing a Schottky diode inside the device, which can reduce the conduction loss of the body diode of the device. At the same time, under the condition of low source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed.

[0021] Third, a heavily doped P-type source region is constructed outside the P-type well region of the device. This P-type source region has two functions. First, the P-type source region and the drift layer form a space charge region. Due to the high doping concentration of the P-type source region, the space charge region mainly diffuses into the drift layer, forming a space charge region on the side of the first gate metal layer and the second gate metal layer near the P-type well region, thereby improving the device's drain-to-source and gate breakdown voltage. Second, it forms an ohmic contact with the second source metal layer, providing auxiliary freewheeling when the Schottky diode's freewheeling current cannot meet the current demand, thus improving the device's current capability.

[0022] Fourth, the low-resistance region is located directly below the first and second gate metal layers, which can achieve electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a low-resistance discrete trench gate silicon carbide VDMOS according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0027] Figure 4 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0035] Figure 12 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0036] Figure 13 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0037] Figure 14 This is a cross-sectional view of the process of a low-resistivity discrete trench gate silicon carbide VDMOS according to the present invention. Figure 10 three. Detailed Implementation

[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0043] like Figure 1 As shown, this application embodiment provides a low-resistance discrete trench gate silicon carbide VDMOS, comprising:

[0044] Silicon carbide substrate 101;

[0045] A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101, is provided with a protrusion 1021 and a groove 10211 on the protrusion 1021;

[0046] P-type well region 103, the lower side of which is connected to the upper side of the protrusion 1021;

[0047] N-type source region 104, the lower side of which is connected to the upper side of P-type well region 103;

[0048] P-type source region 105, the P-type source region 105 is connected to the upper side of the drift layer 102; the inner side of the P-type source region 105 is connected to the outer side of the protrusion 1021, the outer side of the P-type well region 103 and the outer side of the N-type source region 104.

[0049] Low resistance region 106, the low resistance region 106 is disposed in the groove 10211;

[0050] A first insulating dielectric layer 107 is disposed at its lower part within the groove 10211, and the lower side of the first insulating dielectric layer 107 is connected to the upper side of the low-resistivity region 106. One side of the first insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104. A first trench 1071 is provided within the first insulating dielectric layer 107.

[0051] The second insulating dielectric layer 108 is disposed at its lower part within the groove 10211, and its lower side is connected to the upper side of the low-resistivity region 106. One side of the second insulating dielectric layer 108 is connected to the inner side of the P-type well region 103 and the inner side of the N-type source region 104. A second trench 1081 is provided within the second insulating dielectric layer 108.

[0052] A first gate metal layer 109 is disposed within the first trench 1071;

[0053] The second gate metal layer 110 is disposed in the second trench 1081;

[0054] The first source metal layer 111 is disposed in the groove 10211 at its lower part, and the lower side of the first source metal layer 111 is connected to the upper side of the low resistance region 106. The side of the first source metal layer 111 is connected to the other side of the first insulating dielectric layer 107 and the other side of the second insulating dielectric layer 108, respectively.

[0055] The second source metal layer 112 is connected to the P-type source region 105 and the N-type source region 104 respectively.

[0056] And a drain metal layer 113, which is connected to the lower side of the silicon carbide substrate 101.

[0057] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, and the low-resistivity region 106 are all N-type.

[0058] In this embodiment, preferably, the doping concentration of the low-resistivity region 106 is greater than the doping concentration of the drift layer 102.

[0059] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the drift layer 102; the doping concentration of the P-type source region 105 is greater than the doping concentration of the N-type source region 104; and the doping concentration of the P-type source region 105 is greater than the doping concentration of the P-type well region 103.

[0060] In this embodiment, preferably, the thickness of the left side wall of the first insulating dielectric layer 107 is less than the thickness of the right side wall.

[0061] In this embodiment, preferably, the thickness of the left side wall of the second insulating dielectric layer 108 is greater than the thickness of the right side wall.

[0062] like Figures 1 to 14 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0063] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 113; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102;

[0064] Step 2: Form a barrier layer 114 above the drift layer 102, etch the barrier layer 114 to form a via, and perform ion implantation into the drift layer 102 to form a P-type source region 105;

[0065] Step 3: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a via, and perform ion implantation into the drift layer 102 to form a low-resistivity region 106.

[0066] Step 4: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a via, and implant ions into the drift layer 102 to form a P-type well region 103.

[0067] Step 5: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a via, and implant ions into the P-type well region 103 to form the N-type source region 104.

[0068] Step 6: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a through hole, and etch the low-resistivity region 106 to form the first trench 115 and the second trench 116, and deposit the first insulating dielectric layer 107 and the second insulating dielectric layer 108.

[0069] Step 7: Remove the original barrier layer 114, re-form the barrier layer 114, etch the barrier layer 114 to form a via, and etch the first insulating dielectric layer 107 and the second insulating dielectric layer 108 to form the first trench 1071 and the second trench 1081. Deposit metal to form the first gate metal layer 109 and the second gate metal layer 110, respectively.

[0070] Step 8: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, etch the low-resistivity region 106 to form a third trench 117, deposit metal, and form the first source metal layer 111.

[0071] Step 9: Remove the original barrier layer 114, reform the barrier layer 114, etch the barrier layer 114 to form a via, etch the P-type source region 105 and the N-type source region 104, deposit metal to form a second source metal layer 112, remove the barrier layer 114, and complete the fabrication.

[0072] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 6-10e16cm. -3 The doping concentration of the N-type low-resistivity region 106 is 6-10e17cm. -3 The doping concentration of the P-type well region 103 is 6-10e16cm. -3 The doping concentration of the P-type source region 105 is 1-5e19cm. -3 The first insulating dielectric layer 107 and the second insulating dielectric layer 108 can be made of silicon dioxide, and the doping concentration of the N-type source region 104 is 2-8e18cm. -3 ;

[0073] The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 113, reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a trade-off between the reverse breakdown voltage and on-resistance of the device; the doping concentration of the P-type well region 103 is to achieve the breakdown voltage of the pn junction when the device drain is subjected to high voltage; the doping concentration of the P-type source region 105 is to form a space charge region that mainly diffuses into the N-type drift layer 102, thereby protecting the P-type well 103, the first gate metal layer 109, and the second gate metal layer 110 from high voltage at the drain; simultaneously The P-type source region 105 also needs to achieve an ohmic contact with the second source metal layer 112, thereby supplementing the device's current capability and improving its current capability when the parasitic Schottky body diode's freewheeling current is insufficient. The doping concentration of the N-type low-resistivity region 106 is to form a Schottky contact with the first source metal layer 111, reducing the device's body diode forward voltage drop and ensuring reverse withstand voltage. The N-type low-resistivity region 106 also needs to achieve electric field shielding for the device's gate and drain, thereby reducing the device's gate-drain capacitance and improving the device's switching speed. The doping concentration of the N-type source region 104 is to reduce the device's source contact resistance and reduce the device's on-resistance.

[0074] The N-type silicon carbide substrate 101 has a thickness of 1 μm to form a low-resistance ohmic contact with the drain metal layer 113, reducing the device's on-resistance; the N-type drift layer 102 has a thickness of 50-100 μm, adjusted within this range depending on the device's breakdown voltage requirements; the second source metal layer 112 has a thickness of 300 nm, the first source metal layer 111 has a thickness of 700 nm, the P-type source region 105 has a thickness of 600 nm and a width of 500 nm; the N-type source region 105... The thickness of 04 is 100nm, the thickness of P-type well region 103 is 200nm, the thickness of N-type low-resistivity region 106 is 200nm and the width is 3μm, the bottom thickness of the first insulating dielectric layer is 100nm and the width is 1μm, the sidewall width on the side close to P-type well region 103 is 50nm and the sidewall width on the side away from P-type well region 103 is 100nm, the thickness of the first gate metal layer 109 and the thickness of the second gate metal layer 110 are both 600nm and the width is 850nm.

[0075] In this embodiment, the first gate metal layer 109 and the second gate metal layer 110 are disposed separately, thereby reducing the gate structure size of the device and reducing the gate-drain capacitance between the gate and the drain, thereby reducing the switching capacitance of the device and improving the switching speed of the device. The N-type low-resistance region 106 of the device is located directly below the first gate metal layer 109 and the second gate metal layer 110, which can realize the electric field shielding from the gate to the drain of the device, thereby further reducing the gate-drain capacitance of the device and improving the switching speed of the device.

[0076] A first source metal layer 111 is constructed, thereby creating a Schottky diode inside the device and reducing the conduction loss of the body diode. At the same time, under the condition of low source freewheeling current, the bipolar degradation effect caused by P-type carriers can be effectively suppressed. A heavily doped P-type source region 105 is constructed outside the P-type well region 103 of the device. The P-type source region 105 has two functions: First, the P-type source region 105 and the N-type drift layer 102 form a space charge region. Due to the high doping concentration of the P-type source region 105, the space charge region mainly diffuses into the N-type drift layer 102, forming a space charge region on the side of the first gate metal layer 109 and the second gate metal layer 110 near the P-type well region 103, thereby improving the device's drain-to-source and gate breakdown voltage. Second, it forms an ohmic contact with the second source metal layer 112, providing auxiliary freewheeling when the Schottky body diode freewheeling cannot meet the current demand, thereby improving the device's current capability.

[0077] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A low resistance split-separation trench gate silicon carbide VDMOS, characterized in that: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a convex part provided on the upper side of the drift layer, a groove provided on the convex part, a P-type well region connected to the upper side of the convex part, an N-type source region connected to the upper side of the P-type well region, a P-type source region connected to the upper side of the drift layer, the inner side of the P-type source region connected to the outer side of the convex part, the outer side of the P-type well region and the outer side of the N-type source region, a low-resistance region provided in the groove, a first insulating medium layer provided in the lower part of the groove, the lower side of the first insulating medium layer connected to the upper side of the low-resistance region, one side of the first insulating medium layer connected to the inner side of the P-type well region and the inner side of the N-type source region, a first groove provided in the first insulating medium layer, a second insulating medium layer provided in the lower part of the groove, the lower side of the second insulating medium layer connected to the upper side of the low-resistance region, one side of the second insulating medium layer connected to the inner side of the P-type well region and the inner side of the N-type source region, a second groove provided in the second insulating medium layer, a first gate metal layer provided in the first groove, a second gate metal layer provided in the second groove, a first source metal layer provided in the lower part of the groove, the lower side of the first source metal layer connected to the upper side of the low-resistance region, the side of the first source metal layer connected to the other side of the first insulating medium layer and the other side of the second insulating medium layer, a second source metal layer connected to the P-type source region and the N-type source region, and a drain metal layer connected to the lower side of the silicon carbide substrate. The silicon carbide substrate, the drift layer and the low-resistance region are all N-type. The doping concentration of the low-resistance region is greater than the doping concentration of the drift layer. The doping concentration of the P-type source region is greater than the doping concentration of the drift layer, the doping concentration of the P-type source region is greater than the doping concentration of the N-type source region, and the doping concentration of the P-type source region is greater than the doping concentration of the P-type well region. The left sidewall thickness of the first insulating medium layer is less than the right sidewall thickness. The left sidewall thickness of the second insulating medium layer is greater than the right sidewall thickness. ​ ​ ​ ​ ​ ​ ​ ​ 2. A low resistance separation trench gate silicon carbide VDMOS as claimed in claim 1, characterized in that: ​ 3. A low resistance separation trench gate silicon carbide VDMOS as claimed in claim 1, characterized in that: ​ 4. The low-resistivity discrete trench gate silicon carbide VDMOS as described in claim 1, characterized in that: ​ 5. A low resistance separation trench gate silicon carbide VDMOS as claimed in claim 1, characterized in that: ​ 6. A low resistance separation trench gate silicon carbide VDMOS as claimed in claim 1, characterized by: ​

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