Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and a photovoltaic assembly. The solar cell may include: a silicon substrate; the electric functional areas are arranged on the first main surface of the silicon substrate at intervals, and each electric functional area comprises an emitting electrode and a first passivation structure which are stacked from inside to outside; the isolation regions are arranged between the adjacent electric functional regions and comprise second passivation structures; the first metal electrode penetrates through the first passivation structure and is electrically connected with the emitting electrode; for the first main surface of the silicon substrate, the specific surface area corresponding to the isolation region is smaller than the specific surface area corresponding to the electrical functional region. According to the solar cell cutting process, the doped region can be prevented from being damaged, and carrier recombination of a cell piece is reduced.

Description

Technical Field

[0001] This utility model relates to a solar cell and a photovoltaic module. Background Technology

[0002] Photovoltaic modules typically use solar cells obtained by cutting large-sized solar cells to increase the module's output power. For example, a solar cell can be cut once from its center to obtain half a cell; multiple cuts can yield multiple cells. During the laser cutting process, severe laser damage is inevitably caused to the cut surfaces of the cells, resulting in numerous dangling bonds and defect states. These defects act as recombination centers for charge carriers, recombinating with a large number of charge carriers, leading to poor carrier transport capacity and photoelectric conversion efficiency in the solar cell. Utility Model Content

[0003] In view of this, the present invention provides a solar cell and a photovoltaic module. The solar cell obtained by cutting based on the isolation zone set in the solar cell can avoid surface damage on the cutting surface, reduce carrier recombination in the solar cell, and thus improve the carrier transport capacity and photoelectric conversion efficiency of the solar cell.

[0004] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0005] In a first aspect, this utility model provides a solar cell, comprising: a silicon substrate, electrically functional regions spaced apart on a first main surface of the silicon substrate, an isolation region of a planar structure disposed on the first main surface of the silicon substrate between adjacent electrically functional regions, and a first metal electrode, wherein...

[0006] For the first main surface of the silicon substrate, the specific surface area corresponding to the isolation region is smaller than the specific surface area corresponding to the electrical functional region;

[0007] The electrical functional area includes an emitter and a first passivation structure stacked from the inside out;

[0008] The isolation region includes a second passivation structure;

[0009] The first metal electrode passes through the first passivation structure and is electrically connected to the emitter.

[0010] Secondly, embodiments of the present invention provide a photovoltaic module, comprising: solar cells obtained by cutting the solar cells provided in the first aspect embodiment, wherein...

[0011] The solar cell includes: a silicon substrate, an electrical functional region, and an edge isolation region;

[0012] The electrical functional region and the edge isolation region are disposed side by side on the first main surface of the silicon substrate, and the electrical functional region and the edge isolation region extend in the same direction;

[0013] The electrical functional region includes an emitter and a first passivation structure stacked from the inside out;

[0014] The edge isolation region is provided corresponding to at least one edge of the battery cell, and includes a second passivation structure, the thickness of which is greater than the thickness of the first passivation structure;

[0015] For the first main surface of the silicon substrate, the specific surface area corresponding to the edge isolation region is smaller than the specific surface area corresponding to the electrical functional region, and the region corresponding to the edge isolation region is lower than the region corresponding to the electrical functional region.

[0016] The first aspect of the above-mentioned utility model has the following advantages or beneficial effects:

[0017] The solar cell provided in this embodiment of the invention has electrically functional regions spaced apart on the first main surface of the silicon substrate, and planar isolation regions are provided between adjacent electrically functional regions. The specific surface area of ​​the isolation region is smaller than that of the electrically functional region, and the area corresponding to the isolation region is lower than that of the electrically functional region. This ensures that the isolation region is not affected by doped atoms from the emitter and improves the uniformity and density of the second passivation structure, thereby guaranteeing the passivation effect of the isolation region.

[0018] The solar cells obtained by cutting the isolation zone based on the planar structure of the solar cell can avoid surface damage to the cutting surface, reduce carrier recombination of the solar cells, and thus improve the carrier transport capacity and photoelectric conversion efficiency of the solar cell.

[0019] Furthermore, by aligning the cutting position of the solar cell with the centerline of the extension direction of the isolation zone, the consistency of the cut solar cells can be effectively guaranteed.

[0020] In addition, by designing a second passivation structure in the isolation region to work in conjunction with the planar structure of the isolation region, the edges of the solar cells can maintain a good passivation effect after the isolation region is cut, thus preventing edge leakage and helping to improve the open-circuit voltage and conversion factor of the solar cells, thereby improving the electrical performance, stability and reliability of the solar cells. Attached Figure Description

[0021] Figure 1 This is a partial cross-sectional structural schematic diagram of a first structure of a solar cell according to an embodiment of the present utility model;

[0022] Figure 2 This is a cross-sectional view of the first structure of the solar cell according to an embodiment of the present invention.

[0023] Figure 3 This is a partial cross-sectional structural schematic diagram of a second structure of a solar cell according to an embodiment of the present utility model;

[0024] Figure 4 This is a cross-sectional view of the second structure of the solar cell according to an embodiment of the present invention.

[0025] Figure 5 This is a top view of a second structure of a solar cell according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the main process of the solar cell method according to an embodiment of the present invention;

[0027] Figure 7 This is an EL test pattern of the solar cell prepared in Example 1;

[0028] Figure 8 This is an EL test image of the solar cell prepared in Comparative Example 1.

[0029] The attached figures are labeled as follows:

[0030] 10-Silicon substrate; 20-Electrically functional region; 21-Emitter; 22-First silicon oxide passivation layer; 23-First aluminum oxide passivation layer; 24-First front passivation antireflection layer; 30-Isolation region; 31-Second silicon oxide passivation layer; 32-Second aluminum oxide passivation layer; 33-Second front passivation antireflection layer; 30'-Edge isolation region; 40-First metal electrode; 50-Tunneling oxide layer; 60-Doped polycrystalline silicon layer; 70-Back passivation antireflection layer; 80-Second metal electrode; 90-Edge passivation region; 91-Third silicon oxide passivation layer; 92-Third aluminum oxide passivation layer; 93-Third front passivation antireflection layer. Detailed Implementation

[0031] The solar cells provided in this embodiment of the invention are generally cut into multiple cells (exemplarily two, three, four, etc.) using slicing technology. These cells are then connected in series to form a battery string, and the battery strings are assembled into a photovoltaic module. Compared to directly assembling solar cells into photovoltaic modules, photovoltaic modules assembled from sliced ​​solar cells have superior photoelectric conversion efficiency.

[0032] As described in the background section, damage is inevitable on the cut surface during the dicing process of solar cells, leading to carrier recombination. While techniques exist for repairing dicing damage in solar cells, these methods generally require adding complex processes (such as high-temperature annealing and additional passivation) to existing solar cell manufacturing processes. Although high-temperature annealing can repair lattice defects to some extent, the thermal process itself damages the silicon substrate, reducing its lifetime and open-circuit voltage. Furthermore, current methods using atomic layer deposition passivation to repair damage caused by laser dicing in half-cells suffer from high equipment investment costs and complex processes. In addition, controlling laser process parameters is the most direct solution, but limitations such as uneven laser spot energy density and a small process control window during mass production prevent effectively addressing the poor passivation effect in the isolation region caused by laser damage.

[0033] To address the aforementioned problems in the existing technology, this utility model provides a novel solar cell structure and its fabrication method.

[0034] It is worth noting that the terms "first" and "second" in this embodiment of the present invention are mainly used to distinguish different structural positions. For example, the first passivation structure refers to the passivation structure located in the electrical functional region 20, and the second passivation structure refers to the passivation structure located in the isolation region 30; the first main surface of the silicon substrate 10 refers to the main surface of the silicon substrate 10 on the front side of the solar cell after the solar cell is fabricated on the silicon substrate 10, and the second main surface of the silicon substrate 10 refers to the main surface of the silicon substrate 10 on the back side of the solar cell; the first metal electrode 40 refers to the metal electrode located on the front side of the solar cell, and the second metal electrode 80 refers to the metal electrode located on the back side of the solar cell.

[0035] in, Figure 1 This is a partial cross-sectional structural schematic diagram of a first structure of a solar cell according to an embodiment of the present utility model; Figure 2 This is a cross-sectional view of the first structure of the solar cell according to an embodiment of the present invention. Figure 3 This is a partial cross-sectional structural schematic diagram of a second structure of a solar cell according to an embodiment of the present utility model; Figure 4 This is a cross-sectional view of the second structure of the solar cell according to an embodiment of the present invention. Figure 5 This is a top view of a second structure of a solar cell according to an embodiment of the present invention.

[0036] like Figures 1 to 4As shown, the solar cell may include: a silicon substrate 10; electrical functional regions 20 spaced apart on a first main surface of the silicon substrate 10; an isolation region 30 on the first main surface of the silicon substrate 10, which is a planar structure disposed between adjacent electrical functional regions 20; and a first metal electrode 40.

[0037] Among them, for the first main surface of the silicon substrate 10, the specific surface area corresponding to the isolation region 30 is smaller than the specific surface area corresponding to the electrical functional region 20.

[0038] The electrical functional area 20 may include an emitter 21 and a first passivation structure stacked from the inside to the outside;

[0039] The isolation region 30 may include a second passivation structure;

[0040] The first metal electrode 40 passes through the first passivation structure and is electrically connected to the emitter 21.

[0041] The thickness of the second passivation structure included in the isolation region 30 is generally greater than the thickness of the first passivation structure. Furthermore, this second passivation structure can be used to block the emitter 21 of the adjacent electrical functional region 20.

[0042] In this design, the cutting position of the solar cell coincides with the centerline of the extending direction of the isolation region 30. By designing the structure so that the cutting position of the solar cell coincides with the centerline of the extending direction of the isolation region 30, the conductivity and appearance of each cut cell can be kept consistent, which helps to improve the performance of the cut solar cell and ensures the consistency of the appearance of each cut cell.

[0043] The aforementioned electrical functional area 20 can have a velvety surface or a planar surface. Preferably, the electrical functional area 20 has a velvety surface.

[0044] The first and second main surfaces of the silicon substrate 10 are two opposing main surfaces. After the solar cell is fabricated, the first main surface of the silicon substrate 10 is generally located on the front side of the solar cell, and the second main surface of the silicon substrate is generally located on the back side of the solar cell.

[0045] The electrical functional region 20 involved in this embodiment generally refers to the region in a solar cell used to generate and transport charge carriers. The isolation region 30 or the edge passivation region 90 is generally obtained by passivating a portion of the first main surface of the silicon substrate 10. The isolation region 30 does not have the ability to transport charge carriers. The presence of the isolation region 30 or the edge passivation region 90 can prevent short circuits or leakage in the solar cells obtained from cutting. In addition, the presence of the isolation region 30 gives the laser slicing a wider controllable process window, which helps to improve the yield of the solar cells obtained from cutting.

[0046] In this context, the specific surface area of ​​the first main surface of the silicon substrate 10 corresponding to the isolation region 30 generally refers to the ratio of the surface area of ​​the isolation region to its projected area on a plane; the specific surface area of ​​the first main surface of the silicon substrate 10 corresponding to the electrical functional region 20 refers to the ratio of the surface area of ​​the electrical functional region 20 to its projected area on a plane. In other words, the specific surface area of ​​a structure involved in this embodiment of the present invention refers to the surface area of ​​the structure corresponding to a unit projected area on a plane.

[0047] The solar cell structure provided in this embodiment of the present invention, by adjusting the region corresponding to the isolation region 30 and the region corresponding to the electrical functional region 20 on the first main surface of the silicon substrate 10, makes the specific surface area corresponding to the isolation region 30 smaller than that corresponding to the electrical functional region 20. Furthermore, the isolation region 30 cooperates with the second passivation structure to ensure the integrity and compactness of the second passivation structure on the isolation region 30, effectively improving the isolation and passivation effect of the isolation region 30. At the same time, it can ensure the support strength of the part of the silicon substrate 10 corresponding to the isolation region 30, reduce the risk of the silicon substrate 10 fragmenting or cracking in the isolation region 30, and thus improve the service life of the solar cell.

[0048] Regarding the emitter 21, when the silicon substrate 10 is an N-type silicon substrate, the emitter 21 is generally formed by diffusing and doping P-type dopant atoms (such as boron atoms) on the surface of the N-type silicon substrate. When the silicon substrate 10 is a P-type silicon substrate, the emitter 21 is generally formed by diffusing and doping N-type dopant atoms (such as phosphorus atoms) on the surface of the P-type silicon substrate. Preferably, the silicon substrate 10 of the solar cell provided in this embodiment is an N-type silicon substrate, and the emitter 21 is formed by diffusing boron atoms on the N-type silicon substrate. Furthermore, the doping concentration of the emitter 21 is generally 1 × 10⁻⁶. 17 atom / cm 3 ~1×10 19 atom / cm 3 For example, the doping concentration of the emitter 21 can be 1×10⁻⁶. 17 atom / cm 3 2×10 17 atom / cm 3 5×10 17 atom / cm 3 8×10 17 atom / cm 3 1×10 18 atom / cm 3 5×10 18 atom / cm 3 7×10 18 atom / cm 3 9×10 18atom / cm 3 Or 1×10 19 atom / cm 3 For the case where the isolation region 30 is formed on the first main surface of the textured structure of the silicon substrate with the emitter 21 formed on the entire surface and a portion of the emitter 21 removed, by controlling the doping concentration, the photoelectric conversion efficiency of the electrical functional region 20 is guaranteed while the doping atoms of the isolation region 30 are completely removed, so as to ensure the passivation effect of the isolation region 30.

[0049] Regarding the isolation region 30 involved in this embodiment of the invention, its second passivation structure is generally in direct contact with the silicon substrate 10 to passivate the region of the silicon substrate 10 corresponding to the isolation region 30. Furthermore, the extension direction of the isolation region 30 may be as follows: Figure 5 As shown in direction S, in this extending direction, the isolation region 30 penetrates a portion of the silicon substrate 10, and the centerline of the isolation region 30 extending in this direction is as follows: Figure 5 The centerline l shown. For example, for... Figure 1 The solar cell shown is obtained by cutting it along the centerline of the direction extending from the isolation region 30. Figure 2 The half-cell battery shown; for Figure 3 The solar cell shown is obtained by cutting it along the centerline of the direction extending from the isolation region 30. Figure 4 The three-part battery cell shown.

[0050] via Figure 5 The solar cell shown is divided along a centerline l, meaning the cutting position of the solar cell coincides with the centerline extending in the direction of the isolation region 30. This ensures, on the one hand, that the appearance of each divided cell is consistent, guaranteeing the aesthetic appeal of the photovoltaic module fabricated from the cells; on the other hand, it ensures the integrity of the electrical functional regions 20 of each cell, improving the yield rate of the divided cells. Regarding the solar cell provided in the above embodiment, since the electrical functional regions 20 are arranged at intervals on the first main surface of the silicon substrate 10, and a planar isolation region 30 is provided between adjacent electrical functional regions 20, the specific surface area of ​​the isolation region 30 is smaller than that of the electrical functional regions 20. This ensures that the isolation region 30 is not affected by the doping atoms of the emitter 21, thereby guaranteeing the isolation effect of the isolation region 30.

[0051] The solar cells obtained by cutting the isolation region 30 based on the planar structure of the solar cell can avoid surface damage to the cutting surface, reduce carrier recombination of the solar cells, and improve the carrier transport capacity and photoelectric conversion efficiency of the solar cell.

[0052] In the embodiments of this utility model, such as Figures 1 to 4As shown, the region of the first main surface of the silicon substrate 10 corresponding to the isolation region 30 is lower than the region corresponding to the electrical functional region 20. Generally, the region of the isolation region 30 is lower than the region of the electrical functional region 20 relative to the first main surface of the silicon substrate 10 when it is placed upwards. In particular, when the electrical functional region 20 has a textured structure, the surface of the first main surface of the silicon substrate 10 corresponding to the region of the isolation region 30 is lower than the recessed surface of the textured structure corresponding to the electrical functional region 20. By designing this structure, the isolation and passivation effects of the isolation region 30 can be further improved.

[0053] Furthermore, regarding the first main surface of the silicon substrate 10, the relationship between the specific surface area of ​​the region corresponding to the isolation region 30 and the specific surface area of ​​the region corresponding to the electrical functional region 20 is as follows: the ratio of the specific surface area of ​​the region corresponding to the isolation region 30 to the specific surface area of ​​the region corresponding to the electrical functional region 20 (i.e., specific surface area of ​​the region corresponding to the isolation region 30 : specific surface area of ​​the region corresponding to the electrical functional region 20) is generally controlled within the range of 0.25 to 0.65. For example, this ratio can be 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, or 0.65, etc. By controlling the ratio of the specific surface area of ​​the region corresponding to the isolation region 30 to the specific surface area of ​​the region corresponding to the electrical functional region 20 within the range of 0.25 to 0.65 for the first main surface of the silicon substrate 10, during the simultaneous formation of the first passivation structure and the second passivation structure, it can be further ensured that the thickness of the second passivation structure is greater than the thickness of the first passivation structure, and the integrity and density of the second passivation structure can be improved. Furthermore, regarding the case where the isolation region 30 is formed on the first main surface of the textured structure of the silicon substrate 10, with the emitter 21 formed across the entire surface and a portion of the emitter 21 removed, by controlling the ratio within the range of 0.25 to 0.65, it can be ensured that the area of ​​the emitter 21 corresponding to the isolation region 30 can be completely removed. The isolation region 30 forms a planar structure, which, in conjunction with the second passivation structure, can effectively improve the passivation effect of the isolation region 30. When the ratio is less than 0.25, the isolation region 30 is over-polished, resulting in excessively high reflectivity and significant current loss at the solar cell and photovoltaic module ends. Simultaneously, the depth of the isolation region 30 is also too large, leading to increased carrier transport distance and recombination, affecting the fill factor and open-circuit voltage of the cell. When the ratio is greater than 0.65, laser damage to the isolation region 30 cannot be completely removed, affecting the passivation effect of the cell surface, and causing the photoluminescence or electroluminescence detection image to appear black.

[0054] Furthermore, for structures where the region corresponding to the isolation region 30 is lower than the region corresponding to the electrical functional region 20, the height difference between the region corresponding to the isolation region 30 and the region corresponding to the electrical functional region 20 on the first main surface of the silicon substrate 10 (e.g., Figures 1 to 4The height difference ΔH shown is generally 2μm to 15μm. This height difference ΔH generally refers to the height difference between the surface of the isolation region 30 and the surface of the recessed area of ​​the textured surface of the electrical functional region 20. For example, this height difference ΔH can be 2μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 12μm, 14μm, or 15μm, etc. In the case where the isolation region 30 is formed on the entire first main surface of the textured structure of the silicon substrate 10 with the emitter 21 formed on it and a portion of the emitter 21 removed, by controlling this height difference, it can be ensured that the area of ​​the emitter 21 corresponding to the isolation region 30 can be completely removed. Furthermore, by controlling this height difference, it can be ensured that the second passivation structure can completely cover the side of the emitter 21 of the electrical functional region 20 and the side of the first passivation structure, while avoiding the risk of fragmentation or microcracks caused by the silicon substrate 10 portion corresponding to the isolation region 30 being too thin.

[0055] Besides the structural relationship between the isolation region 30 and the electrical functional region 20, and the structure of the emitter 21, the first passivation structure of the electrical functional region 20 and the second passivation structure of the isolation region 30 also affect the photoelectric conversion efficiency, stability, and reliability of the entire solar cell. The first and second passivation structures will be explained in detail below.

[0056] Furthermore, regarding the relationship between the first and second passivation structures mentioned above, generally, the thickness of the second passivation structure in the isolation region 30 is greater than the thickness of the first passivation structure in the electrical functional region 20. By designing the thickness of the second passivation structure in the isolation region 30 to be greater than the thickness of the first passivation structure in the electrical functional region 20, and in conjunction with the planar structure of the isolation region 30, the edges of the solar cell can maintain a good passivation effect after the isolation region 30 is cut, avoiding edge leakage of the cell. This helps to improve the open-circuit voltage and conversion factor of the cell, thereby improving the electrical performance, stability, and reliability of the solar cell.

[0057] Generally, the second passivation structure is formed simultaneously with the first passivation structure.

[0058] like Figures 1 to 4 As shown, the first passivation structure may include a first silicon oxide passivation layer 22 and a first aluminum oxide passivation layer 23 stacked from the inside to the outside.

[0059] The second passivation structure may include a second silicon oxide passivation layer 31 and a second aluminum oxide passivation layer 32 stacked from the inside to the outside.

[0060] By combining the first passivation structure, which includes the first silicon oxide passivation layer 22 and the first aluminum oxide passivation layer 23, with the second passivation structure, which includes the second silicon oxide passivation layer 31 and the second aluminum oxide passivation layer 32, the passivation effect of the solar cell on the surface of the isolation region 30 and the electrical functional region 20 can be guaranteed, and the second passivation structure can be guaranteed to completely cover the side of the emitter 21 and the side of the first passivation structure.

[0061] More specifically, the thickness of the second silicon oxide passivation layer 31 is greater than the thickness of the first silicon oxide passivation layer 22. The thickness of the second aluminum oxide passivation layer 32 is greater than the thickness of the first aluminum oxide passivation layer 23. This thickness superposition ensures that the second passivation structure completely covers the side surface of the emitter 21 and the side surface of the first passivation structure, and ensures the passivation effect of the isolation region 30.

[0062] The thickness of the second silicon oxide passivation layer 31 is ( Figure 2 The thickness T4 shown is typically 0.5 nm to 5 nm. By controlling the thickness of this second silicon oxide passivation layer 31, most of the dangling bonds on the surface of the silicon substrate 10 can be bonded, achieving a passivation effect. For example, the thickness of this second silicon oxide passivation layer 31 (…) Figure 2 The thickness T4 shown can be 0.5nm, 1nm, 1.3nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 2.8nm, 3nm, 3.3nm, 3.5nm, 3.8nm, 4nm, 4.2nm, 4.5nm, 4.8nm or 5nm, etc.

[0063] The thickness of the first silicon oxide passivation layer 22 ( Figure 2 The thickness T1 shown is typically 0.3 nm to 3.5 nm. For example, the thickness of the first silicon oxide passivation layer 22 (…) Figure 2 The thickness T4 shown can be 0.3nm, 0.8nm, 1nm, 1.1nm, 1.3nm, 1.5nm, 1.7nm, 2nm, 2.2nm, 2.5nm, 2.7nm, 2.9nm, 3nm, 3.3nm, or 3.5nm, etc. It is understood that the thickness of the first silicon oxide passivation layer 22 and the thickness of the second silicon oxide passivation layer 31 still satisfy the condition that the thickness of the first silicon oxide passivation layer 22 is less than the thickness of the second silicon oxide passivation layer 31. For example, if the thickness of the first silicon oxide passivation layer 22 is controlled to be 1nm, then the thickness of the second silicon oxide passivation layer 31 is greater than 1nm.

[0064] The thickness of the second alumina passivation layer 32 ( Figure 2The thickness T3 shown is generally 3nm to 15nm. For example, the thickness of the second alumina passivation layer 32 can be 3nm, 5nm, 8nm, 10nm, 12nm or 15nm, etc. By controlling the second alumina passivation layer 32, it can assist the second silicon oxide passivation layer 31 to further combine the dangling bonds that are not combined by the second silicon oxide passivation layer 31, and form a complementary passivation effect with the second silicon oxide passivation layer 31.

[0065] The thickness of the first alumina passivation layer 23 ( Figure 2 The thickness T2 shown is generally 2nm to 10nm. For example, the thickness of the first alumina passivation layer 23 can be 2nm, 4nm, 5nm, 6nm, 8nm or 10nm, etc.

[0066] It is worth noting that the thickness of the second silicon oxide passivation layer 31 is greater than the thickness of the first silicon oxide passivation layer 22, and the thickness of the second aluminum oxide passivation layer 32 is greater than the thickness of the first aluminum oxide passivation layer 23. This is determined by the relationship between the specific surface area of ​​the isolation region 30 and the specific surface area corresponding to the electrical functional region 20. Furthermore, based on the ratio (0.25 to 0.65) between the specific surface area of ​​the isolation region 30 and the specific surface area corresponding to the electrical functional region 20 given above, the smaller this ratio, the better the isolation effect of the isolation region.

[0067] Furthermore, regarding the electrical functional region 20, based on the aforementioned first passivation structure, the solar cell may further include a first front-side passivation antireflection layer 24 stacked on the outside of the first passivation structure. Preferably, for the first passivation structure comprising a first silicon oxide passivation layer 22 and a first aluminum oxide passivation layer 23, the first front-side passivation antireflection layer 24 is stacked on the outside of the first aluminum oxide passivation layer 23. The first front-side passivation antireflection layer 24 may be a single layer or a stacked structure, and the first front-side passivation antireflection layer 24 may include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0068] In addition, regarding the isolation region 30, based on the aforementioned second passivation structure, the solar cell may further include a second front-side passivation antireflection layer 33 stacked on the outside of the second passivation structure. Preferably, for the second passivation structure comprising a second silicon oxide passivation layer 31 and a second aluminum oxide passivation layer 32, the second front-side passivation antireflection layer 33 is stacked on the outside of the second aluminum oxide passivation layer 32. The second front-side passivation antireflection layer 33 may also be a single layer or a stacked structure, and the second front-side passivation antireflection layer 33 may include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride.

[0069] Furthermore, the thickness of the aforementioned first front passivation antireflection layer 24 is generally 20nm to 180nm. For example, the thickness of the first front passivation antireflection layer 24 can be 20nm, 30nm, 50nm, 60nm, 70nm, 100nm, 120nm, 140nm, 150nm, 170nm, or 180nm, etc. By controlling the thickness of the first front passivation antireflection layer 24, the light reflection of the electrical functional region 20 can be effectively reduced, thereby improving the light utilization rate of the electrical functional region 20.

[0070] The thickness of the second front passivation antireflection layer 33 can be set according to actual needs and is not limited here.

[0071] Additionally, regarding isolation zone 30, the width of isolation zone 30 (e.g.) Figure 1 or Figure 3 The width W shown is typically 20 μm to 1000 μm. For example, the width of the isolation region 30 can be 20 μm, 30 μm, 50 μm, 70 μm, 80 μm, 100 μm, 200 μm, 250 μm, 500 μm, 600 μm, 800 μm, 900 μm, or 1000 μm. Preferably, the width of the isolation region 30 is 20 μm to 600 μm. By controlling the width of the isolation region 30, the isolation and passivation effects of the isolation region 30 can be guaranteed, while allowing sufficient space for cutting deviations, preventing damage to the electrical functional region 20 due to cutting errors during the cutting process, and improving the yield of the solar cells. Furthermore, by controlling the width of the isolation region 30, the passivation effect of the cut solar cell edges can also be guaranteed, preventing carriers from accumulating at the edges of the solar cells.

[0072] Furthermore, regarding the emitter 21, its thickness ( Figures 1 to 4 The thickness T shown is typically 0.5 μm to 1.5 μm. For example, the thickness of the emitter 21 can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.3 μm, or 1.5 μm, etc. By controlling the thickness of the emitter 21, the photoelectric conversion efficiency of the electrical functional region 20 can be improved. Furthermore, in the case where the isolation region 30 is formed on the entire first main surface of the textured structure of the silicon substrate 10 with the emitter 21 formed on it and a portion of the emitter 21 removed, by controlling the thickness of the emitter 21, the photoelectric conversion efficiency of the electrical functional region 20 can be improved while ensuring that the region of the emitter 21 corresponding to the isolation region 30 can be completely removed.

[0073] Furthermore, such as Figures 1 to 4As shown, the aforementioned solar cell may further include: a tunneling oxide layer 50, a doped polycrystalline silicon layer 60, and a back passivation antireflection layer 70 stacked from the inside to the outside on the second main surface of the silicon substrate 10; and a second metal electrode 80, which passes through the back passivation antireflection layer 70 and is electrically connected to the doped polycrystalline silicon layer 60. The tunneling oxide layer 50 is generally silicon oxide, and its thickness is generally 0.5 nm to 3 nm. For example, the thickness of the tunneling oxide layer 50 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm, etc. The thickness of the doped polycrystalline silicon layer 60 is generally 30 nm to 200 nm. For example, the thickness of the doped polycrystalline silicon layer 60 can be 30 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, or 200 nm, etc. The doping concentration of the doped polycrystalline silicon layer 60 is generally 1 × 10⁻⁶. 20 atom / cm 3 ~1×10 21 atom / cm 3 For example, the doping concentration of the doped polysilicon layer 60 can be 1×10⁻⁶. 20 atom / cm 3 2×10 20 atom / cm 3 4×10 20 atom / cm 3 5×10 20 atom / cm 3 7×10 20 atom / cm 3 9×10 20 atom / cm 3 Or 1×10 21 atom / cm 3 The conductivity type of the doped atoms in the polysilicon layer 60 is opposite to that of the doped atoms in the emitter 21. That is, if the doped atoms in the emitter 21 are P-type, the doped atoms in the polysilicon layer 60 are N-type; conversely, if the doped atoms in the emitter 21 are N-type, the doped atoms in the polysilicon layer 60 are P-type. Additionally, the back passivation antireflection layer 70 may include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, and aluminum oxynitride. The thickness of the back passivation antireflection layer 70 is generally 25 nm to 200 nm. For example, the thickness of the back passivation antireflection layer 70 may be 25 nm, 30 nm, 40 nm, 45 nm, 50 nm, 70 nm, 80 nm, 100 nm, 120 nm, 130 nm, 150 nm, 170 nm, 180 nm, or 200 nm, etc.

[0074] Furthermore, such as Figures 3 to 5 As shown, the aforementioned solar cell further includes: an edge passivation region 90 of a planar structure disposed on two opposing edges of a first main surface of the silicon substrate 10, wherein, as Figure 5 As shown, the edge passivation region 90 is parallel to the isolation region 30; for the first main surface of the silicon substrate 10, the specific surface area corresponding to the edge passivation region 90 is smaller than the specific surface area corresponding to the electrical functional region 20, and the region corresponding to the edge passivation region 90 is lower than the region corresponding to the electrical functional region 20; the edge passivation region 90 includes a third passivation structure for blocking the emitter 21 from extending to the edge.

[0075] By setting this edge passivation area 90, on the one hand, the cut solar cells can maintain consistency, and the process of flipping the solar cells can be omitted when connecting solar cells in series, simplifying the manufacturing process of photovoltaic modules; on the other hand, it ensures the insulation of the edge of the solar cells, avoids leakage at the edge of the solar cells, helps to improve the photoelectric conversion efficiency of solar cells, and helps to reduce the spacing between solar cells in photovoltaic modules.

[0076] Furthermore, the thickness of the third passivation structure is generally greater than the thickness of the first passivation structure. The third passivation structure is generally formed simultaneously with the first passivation structure. For example... Figure 3 As shown, the third passivation structure may include a third silicon oxide passivation layer 91 and a third aluminum oxide passivation layer 92 stacked from the inside out. Preferably, the thickness of the third silicon oxide passivation layer 91 is greater than the thickness of the first silicon oxide passivation layer 22, and the thickness of the third aluminum oxide passivation layer 92 is greater than the thickness of the first aluminum oxide passivation layer 23.

[0077] The thickness of the third alumina passivation layer 92 is generally 3nm to 15nm. For example, the thickness of the third alumina passivation layer 92 can be 3nm, 5nm, 8nm, 10nm, 12nm or 15nm, etc. By controlling the third alumina passivation layer 92, it can assist the third silicon oxide passivation layer 91 to further combine the dangling bonds that are not combined by the third silicon oxide passivation layer 91, and form a complementary passivation effect with the third silicon oxide passivation layer 91.

[0078] The third silicon oxide passivation layer 91 is typically 0.5nm to 5nm. For example, the thickness of the third silicon oxide passivation layer 91 can be 1nm, 1.5nm, 2nm, 2.8nm, 3nm, 3.5nm, 4nm, 4.5nm, or 4.8nm, etc.

[0079] Furthermore, such as Figure 3 As shown, the third passivation structure may further include a third front passivation antireflection layer 93. For the third passivation structure comprising a third silicon oxide passivation layer 91 and a third aluminum oxide passivation layer 92, the third front passivation antireflection layer 93 is generally stacked on the outside of the third aluminum oxide passivation layer 92.

[0080] Generally, the edge passivation region 90 is formed in the same way as the isolation region 30, except that the width of the edge passivation region 90 is smaller than that of the isolation region 30. Preferably, the width of the edge passivation region 90 is half the width of the isolation region 30, so as to further ensure the consistency of the appearance of each of the cut-out battery cells.

[0081] It is worth noting that the above Figures 3 to 5 The solar cell shown with the edge passivation region 90 is only a preferred structure; for cells divided into three parts or more, the edge passivation region 90 may not be included. Additionally, for... Figure 2 The structure shown is a solar cell divided into half cells, which can also have an edge passivation region 90 at the edge.

[0082] Furthermore, this utility model embodiment provides a photovoltaic module. The photovoltaic module may include: solar cells cut from the solar cells provided in the above embodiments, such as... Figure 2 and Figure 4 The battery cells shown, wherein,

[0083] The solar cell may include: a silicon substrate 10, an electrical functional region 20, and an edge isolation region 30';

[0084] Electrical functional region 20 and edge isolation region 30' are disposed side by side on the first main surface of silicon substrate 10, and the electrical functional region 20 and edge isolation region 30' extend in the same direction;

[0085] The electrical functional region 20 includes an emitter 21 and a first passivation structure stacked from the inside to the outside;

[0086] The edge isolation region 30' is provided corresponding to at least one edge of the battery cell, and includes a second passivation structure for blocking the emitter 21 of the electrical functional region 20 from extending toward the edge;

[0087] For the first main surface of the silicon substrate 10, the specific surface area corresponding to the edge isolation region 30' is smaller than the specific surface area corresponding to the electrical functional region 20.

[0088] Furthermore, the area corresponding to the edge isolation zone 30' is lower than the area corresponding to the electrical functional zone 20.

[0089] In addition, the thickness of the second passivation structure is greater than the thickness of the first passivation structure.

[0090] For the 30' edge isolation zone, targeting Figure 1 or Figure 3The solar cell shown, after being cut, has its original isolation region 30 and edge passivation layer 90 transformed into the edge isolation region 30' of the cell. By designing this edge isolation region 30' for the cell, the diffusion of carriers from the emitter 21 to the edge can be prevented, thereby avoiding leakage at the cell edge and helping to improve the photoelectric conversion efficiency of the photovoltaic module.

[0091] Among them, the width of the edge isolation zone 30' (e.g. Figure 2 or Figure 4 The width W1 shown is typically 10μm to 300μm. For example, the width of the edge isolation region 30' can be 10μm, 20μm, 50μm, 100μm, 120μm, 150μm, 180μm, 200μm, 230μm, 250μm, 280μm, or 300μm, etc. By controlling the width of the edge isolation region 30', the insulation of the cell edge can be ensured.

[0092] Furthermore, this embodiment of the invention also provides a method for preparing a solar cell. For example... Figure 6 As shown, the method for fabricating this solar cell may include the following steps:

[0093] Step S601: An emitter 21 is prepared on the first main surface of the silicon substrate 10, and the surface of the emitter 21 has a first doped silicon glass layer.

[0094] The specific implementation scheme for fabricating the emitter 21 in this step may include: fabricating the emitter 21 on the entire surface of the first main surface of the silicon substrate 10 through an element diffusion process. During the fabrication of the emitter 21, due to the presence of oxygen in the air, a first doped silicon glass layer is formed on the surface of the emitter 21. For example, if the diffusing atom is boron, the first doped silicon glass layer is a borosilicate glass layer; if the diffusing atom is phosphorus, the first doped silicon glass layer is a phosphosilicate glass layer. This diffusion process can directly use the diffusion process used in existing solar cell production.

[0095] Additionally, in this step, during the diffusion process, a boron-doped layer and a borosilicate glass layer may be deposited around the second main surface and sides of the silicon substrate 10. For example, if the emitter dopant is boron, a boron-doped layer and a borosilicate glass layer are deposited around the second main surface and sides of the silicon substrate 10. Based on this structure, the borosilicate glass layer can be removed by etching the second main surface and sides of the silicon substrate 10 with hydrofluoric acid. The boron-doped layer is then removed by polishing the second main surface and sides of the silicon substrate 10 with an alkaline solution.

[0096] Further, after step S601 and before step S602, the process may further include: sequentially stacking a tunneling oxide layer 50 and a doped polysilicon layer 60 on the second main surface of the silicon substrate 10 by chemical deposition. The conductivity type of the doped atoms in the doped polysilicon layer 60 is opposite to that of the doped atoms in the emitter 21 (for example, the doped polysilicon layer 60 is a phosphorus-doped polysilicon layer, and the doped atoms in the emitter 21 are boron; the doped polysilicon layer 60 is a boron-doped polysilicon layer, and the doped atoms in the emitter 21 are phosphorus). The formation of the tunneling oxide layer 50 and the doped polysilicon layer 60 can be achieved by one or more of the following techniques: plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), in-situ low-pressure chemical vapor deposition, mist-vapor chemical vapor deposition (Mist-CVD), or physical vapor deposition (PVD).

[0097] During the formation of the tunneling oxide layer 50 and the doped polysilicon layer 60, a second doped silicon glass layer is formed on the outside of the doped polysilicon layer 60, and a multilayer winding doped layer is formed on the outside of the first doped silicon glass layer. Specifically, the formation process of this multilayer winding doped layer is as follows: during the formation of the tunneling oxide layer 50 on the second main surface of the silicon substrate 10, a first winding layer corresponding to the tunneling oxide layer 50 is simultaneously formed on the outside of the first doped silicon glass layer. Furthermore, dopants from the first doped silicon glass layer enter the first winding layer, causing the doped first winding layer to fuse with the original first doped silicon glass layer to form a new first doped silicon glass layer. Then, during the formation of the doped polysilicon layer 60, a second wrap-around layer corresponding to the doped polysilicon layer 60 is simultaneously formed on the outside of the new first doped silicon glass layer, and a third wrap-around layer corresponding to the second doped silicon glass layer is formed on the outside of the second wrap-around layer. During the formation of the doped polysilicon 60, dopants in the second wrap-around layer diffuse into the new first doped silicon glass layer, causing the outer portion of the new first doped silicon glass layer to form the third doped silicon glass layer, while the inner portion of the third doped silicon glass layer remains the first doped silicon glass layer. That is, after the doped polysilicon layer 60 is processed, a first doped silicon glass layer, a third doped silicon glass layer, a second wrap-around layer corresponding to the doped polysilicon layer 60, and a third wrap-around layer corresponding to the second doped silicon glass layer are stacked from the inside to the outside of the emitter 21. In other words, the multilayer wrap-around doped layer is a collective term for the first doped silicon glass layer, the third doped silicon glass layer, the second wrap-around layer, and the third wrap-around layer stacked from the inside to the outside.

[0098] For example, taking boron atoms as the doped atoms in the emitter 21 and phosphorus atoms as the doped atoms in the doped polysilicon layer 60, and a borosilicate glass layer (which is the aforementioned first doped silicon glass layer) as an example, the specific process of forming the tunneling oxide layer 50, the doped polysilicon layer 60, the second doped silicon glass layer, and the multilayer winding doped layer is as follows: The tunneling oxide layer 50 and the polysilicon layer are sequentially prepared on the second main surface of the silicon substrate 10 by chemical deposition. Phosphorus atoms are doped and diffused into the polysilicon layer to form a phosphorus-doped polysilicon layer. A phosphorus-silicon glass layer (i.e., the aforementioned second doped silicon glass layer) is then formed on the outside of the phosphorus-doped polysilicon layer. Simultaneously, a first winding coating corresponding to the tunneling oxide layer 50 is first formed on the outside of the borosilicate glass layer on the first main surface of the silicon substrate 10. Boron atoms in the borosilicate glass layer enter the first winding coating, and the first winding coating fuses with the borosilicate glass layer to form a new borosilicate glass layer. Then, a wrap-around coating corresponding to the polycrystalline silicon layer is formed on the outside of the new borosilicate glass layer. During the doping and diffusion of phosphorus atoms into the polycrystalline silicon layer, phosphorus atoms simultaneously diffuse into the wrap-around coating corresponding to the polycrystalline silicon layer to form a second wrap-around coating doped with phosphorus atoms (the composition of this second wrap-around coating is essentially phosphorus-doped polycrystalline silicon). In addition, phosphorus atoms in the second wrap-around coating will enter the outer portion of the new borosilicate glass layer, so that the outer portion of the new borosilicate glass layer forms a phosphobosilicate glass layer (i.e., the aforementioned third doped silicon glass layer), while the inner portion of the phosphobosilicate glass layer remains a borosilicate glass layer. Further, a third wrap-around coating corresponding to the phosphobosilicate glass layer (i.e., the aforementioned second doped silicon glass layer) is formed on the outside of the second wrap-around coating (the composition of this third wrap-around coating is essentially a phosphobosilicate glass layer). That is, the multilayer wrap-around doped layer consists of a phosphobosilicate glass layer, a phosphorus-doped polycrystalline silicon layer, and a phosphobosilicate glass layer stacked from the inside out. Understandably, there are no clear boundaries between the borosilicate phosphorus glass layer, the phosphorus-doped polycrystalline silicon layer, and the phosphorus-silicon glass layer in this multilayer winding doped layer. The description of the borosilicate phosphorus glass layer, the phosphorus-doped polycrystalline silicon layer, and the phosphorus-silicon glass layer is only for the purpose of clearly illustrating the formation process of the multilayer winding doped layer. In addition, a winding layer is also formed on the side of the silicon substrate 10. The composition of the winding layer formed on the side of the silicon substrate 10, from the inside to the outside, is a phosphorus-silicon glass layer (this phosphorus-silicon glass layer is formed by phosphorus atoms entering the tunneling oxide layer), a phosphorus-doped polycrystalline silicon layer, and a phosphorus-silicon glass layer.

[0099] Alternatively, the planar silicon substrate can be fabricated into a textured surface before step S601.

[0100] Step S602: Laser grooving is used to process a portion of the emitter 21 with the first doped silicon glass layer on its surface.

[0101] Specific implementation schemes for this step may include: selecting a green picosecond pulsed laser with a wavelength of 200nm to 600nm, and controlling the power of the green picosecond pulsed laser within the range of 20W to 100W, the pulse width within the range of 1ps to 50ps, and the single pulse energy within the range of 50MJ to 200MJ. For example, the wavelength of the green picosecond pulsed laser selected may be 200nm, 300nm, 400nm, 500nm, or 600nm, etc. The power of the green picosecond pulsed laser may be 20W, 25W, 30W, 40W, 50W, 70W, 80W, 90W, or 100W, etc. The pulse width may be 1ps, 5ps, 10ps, 15ps, 18ps, 20ps, 25ps, 30ps, 40ps, or 50ps, etc. The single pulse energy is 50MJ, 80MJ, 100MJ, 120MJ, 140MJ, 150MJ, 180MJ or 200MJ, etc.

[0102] By selecting a green picosecond pulsed laser with a wavelength of 200nm to 600nm and controlling its parameters, the first doped silicon glass layer, the emitter 21, and the single-crystal silicon on the silicon substrate surface in the laser-grooved region can be molten. This, combined with step S603, allows the laser-grooved region to form a planar structure. This ensures that the first doped silicon glass layer and the emitter 21 in the laser-grooved region are completely removed while minimizing surface damage. Furthermore, the other areas outside the laser-grooved region (i.e., the aforementioned electrical functional region 20) can have the first doped silicon glass layer removed by etching with hydrofluoric acid at a volume concentration of 2% to 10%, leaving a relatively intact emitter 21 in the electrical functional region 20.

[0103] Furthermore, as described above, in the process of sequentially stacking the tunneling oxide layer 50 and the doped polysilicon layer 60 on the second main surface of the silicon substrate 10, there is a related winding plating on the first main surface of the silicon substrate 10 (i.e., a multilayer winding plating doped layer is formed on the outside of the emitter 21 as described above). This step S602 can also make the multilayer winding plating doped layer in the laser grooving region become molten, and does not affect the first doped silicon glass layer and the emitter in the laser grooving region becoming molten, which is beneficial for the subsequent priority removal of each film layer in the laser grooving region.

[0104] It is worth noting that the melting of the various film layers or functional structural layers involved in this step does not mean that they become flowing liquids, but rather that the chemical bonds in the various film layers or functional structural layers are broken by the laser, making the various film layers or functional structural layers "loose" and easier for the cleaning agent in step S603 to penetrate and clean.

[0105] Step S603: Clean the laser-grooved area and the first doped silicon glass layer on the surface of the emitter 21 to form spaced electrical functional regions 20 with emitters 21 and isolation regions 30 with planar structures located between adjacent electrical functional regions 20 on the first main surface of the silicon substrate 10.

[0106] Specifically, for the case where the silicon substrate 10 has a tunneling oxide layer 50 and a doped polycrystalline silicon layer 60 formed during the winding plating process (i.e., a multilayer winding plating doped layer consisting of a third doped silicon glass layer, a second winding plating layer, and a third winding plating layer stacked from the inside to the outside of the first doped silicon glass layer), the outermost third winding plating layer in the multilayer winding plating doped layer is first removed by cleaning with hydrofluoric acid with a volume concentration of 2% to 10%. Then, the first main surface of the silicon substrate 10 is cleaned with an alkaline solution for 280s to 450s to etch the area treated by laser grooving. The alkaline solution can be a sodium hydroxide solution or a potassium hydroxide solution in RCA technology, and the volume concentration of the alkaline solution is 4% to 8%. More specifically, the sodium hydroxide solution or potassium hydroxide solution in RCA technology removes the second winding plating layer, the third doped silicon glass layer, the first doped silicon glass layer, and the emitter 21, which become molten in the area treated by laser grooving. In addition, during the cleaning of the first main surface of the silicon substrate 10 with sodium hydroxide or potassium hydroxide solution in this RCA technology, the second layer corresponding to the doped polysilicon layer 60 in the multilayer doped layer in other regions (i.e., the region corresponding to the electrical functional region 20) can also be removed simultaneously. Finally, the remaining portion of the multilayer doped layer in other regions (i.e., the region corresponding to the electrical functional region 20) is removed using the acid solution in the RCA technology, that is, the third doped silicon glass layer and the first doped silicon glass layer in the electrical functional region 20 are removed.

[0107] The volume concentration of hydrofluoric acid used to remove the outermost third layer of the multilayer doped coating can be 2%, 5%, 7%, or 8%, etc.

[0108] The sodium hydroxide cleaning time in RCA technology can be 280s, 300s, 320s, 350s, 380s, 400s, 430s, or 450s, etc.

[0109] In addition, the acid solution cleaning time in RCA technology can be determined according to the actual situation and is not limited here.

[0110] In addition, the coating around the side of the silicon substrate 10 can be removed simultaneously during this step.

[0111] Step S603, in conjunction with step S602 above, achieves the following: the specific surface area of ​​the first main surface of the silicon substrate 10 corresponding to the isolation region 30 is smaller than the specific surface area corresponding to the electrical functional region 20, and the region corresponding to the isolation region 30 is lower than the region corresponding to the electrical functional region 20. This ensures that all doped atoms in the isolation region 30 can be removed, and further ensures that the thickness of the second passivation structure formed in the isolation region 30 in the subsequent step S604 is greater than the thickness of the first passivation structure formed in the electrical functional region 20 (i.e., the thickness of the second silicon oxide passivation layer 31 is greater than the thickness of the first silicon oxide passivation layer 22; the thickness of the second aluminum oxide passivation layer 32 is greater than the thickness of the first aluminum oxide passivation layer 23).

[0112] This step S603 works in conjunction with the above step S602. It does not require a masking process or additional wet etching process. It can remove the first doped silicon glass layer on the emitter 21 without causing significant damage to the emitter 21. It can also completely remove the emitter 21 in the laser grooving area, ensuring the insulation and passivation effect of the isolation region 30 formed in the laser grooving area. Moreover, the process is simple, reduces surface damage to the isolation region 30, effectively controls production costs, and ensures the performance of the produced solar cells.

[0113] In step S604, a first passivation structure is formed in the electrical functional region 20, and a second passivation structure is simultaneously formed in the isolation region 30.

[0114] Step S604 specifically includes the following scheme: sequentially depositing a silicon oxide layer and an aluminum oxide layer using atomic layer deposition (ALD). Due to the structural differences between the electrical functional region 20 and the isolation region 30 after steps S602 and S603, the thicknesses of the deposited silicon oxide and aluminum oxide layers in the electrical functional region 20 and the isolation region 30 will differ. Specifically, for the silicon oxide layer, the thickness corresponding to the isolation region 30 is greater than the thickness corresponding to the electrical functional region 20; for the aluminum oxide layer, the thickness corresponding to the isolation region 30 is greater than the thickness corresponding to the electrical functional region 20.

[0115] Furthermore, in this step, a front passivation antireflection layer can be deposited on the surface of the alumina layer using the PECVD method.

[0116] In addition, during this step, a back passivation antireflection layer 70 can be stacked on the doped polysilicon layer 60 while the front passivation antireflection layer is being formed.

[0117] Furthermore, after step S604 above, a first metal electrode 40 and a second metal electrode 80 may be prepared on the second main surface of the electrical functional region 20 and the silicon substrate 10, respectively. The first metal electrode 40 penetrates the first front passivation antireflection layer 24, the first alumina passivation layer 23 and the first silicon oxide passivation layer 22 and is electrically connected to the emitter 21. The second metal electrode 80 penetrates the back passivation antireflection layer 70 and is electrically connected to the doped polycrystalline silicon layer 60.

[0118] The following describes in detail the solar cell fabrication process provided by the embodiments of this utility model through several examples.

[0119] Example 1

[0120] Step A1: Select a qualified N-type silicon substrate and prepare a textured surface on the N-type silicon substrate.

[0121] Step B1: Prepare boron-doped material with a boron atom concentration of 1×10⁻⁶ on the first main surface of an N-type silicon substrate using a boron diffusion process. 18 atom / cm 3 The emitter has a borosilicate glass layer formed on its surface.

[0122] Step C1: Clean the second main surface of the N-type silicon substrate and the borosilicate glass layer coated on the side with hydrofluoric acid, and polish the second main surface of the N-type silicon substrate with an alkaline solution.

[0123] Step D1: A tunneling oxide layer with a thickness of 1.5 nm and an N-type doped polycrystalline silicon layer with a thickness of 130 nm are sequentially deposited on the second main surface of the N-type silicon substrate using PECVD.

[0124] Step E1: Using a green picosecond pulsed laser with a wavelength of 532nm, under the conditions of 50W power, 25ps pulse and 100MJ single pulse energy, laser grooving is performed on a portion of the first main surface of the N-type silicon substrate.

[0125] Step F1: Remove the phosphosilicate glass layer and the side phosphosilicate glass layer coated around the first main surface of the N-type silicon substrate using HF with a volume concentration of 10%. Then, clean with NaOH with a volume concentration of 5% in the RCA technique for 400 seconds to remove the coating layer, phosphosilicate glass layer, borosilicate glass layer and emitter 21 corresponding to the N-type doped polysilicon layer in the laser-grooved area. Simultaneously remove the coating layer corresponding to the N-type doped polysilicon layer in the electrical functional region 20. Clean the laser-grooved area into a planar isolation region 30. Clean the phosphosilicate glass layer and borosilicate glass layer of the electrical functional region 20 with acid solution in the RCA technique. After this step, the ratio of the specific surface area of ​​the isolation region 30 to the specific surface area of ​​the electrical functional region 20 with the emitter 21 is 0.3:1.

[0126] Step G1: Using ALD technology at 320℃, a silicon oxide passivation layer and an aluminum oxide passivation layer are sequentially deposited on the first main surface of the N-type silicon substrate. The thickness of the silicon oxide passivation layer on the emitter 21 surface is 1nm and the thickness of the aluminum oxide passivation layer is 5nm. The thickness of the silicon oxide passivation layer deposited in the isolation region is 3nm and the thickness of the aluminum oxide passivation layer is 8nm. Then, using PECVD technology at a temperature of 550℃, a pressure of 255Pa, and an RF power of 10000W, passivation antireflection layers are deposited on the surface of the aluminum oxide passivation layer and on the surface of the N-type doped polysilicon layer on the second main surface of the N-type silicon substrate, respectively.

[0127] Step H1: Metal paste is printed on the first main surface and the second main surface respectively by screen printing, and sintered to form a first metal electrode 40 electrically connected to the emitter 21 and a second metal electrode 80 electrically connected to the N-type doped polysilicon layer.

[0128] Example 2

[0129] The preparation process is basically the same as in Example 1. The difference is that the cleaning time of the alkaline solution laser-grooved area in Example 2 is 300s, and the ratio of the specific surface area of ​​the isolation region 30 to the specific surface area of ​​the electrical functional region 20 with the emitter 21 is 0.5:1. The thickness of the silicon oxide passivation layer on the surface of the emitter 21 is 1nm, the thickness of the aluminum oxide passivation layer is 5nm, the thickness of the silicon oxide passivation layer deposited in the isolation region is 2nm, and the thickness of the aluminum oxide passivation layer is 6nm.

[0130] Comparative Example 1

[0131] The preparation process is basically the same as in Example 1. The difference is that the cleaning time of the alkaline solution laser-grooved area in Example 2 is 100s, and the ratio of the specific surface area of ​​the isolation region to the specific surface area of ​​the electrical functional region with the emitter is 0.75:1. The thickness of the silicon oxide passivation layer on the surface of the emitter 21 is 0.2nm, the thickness of the aluminum oxide passivation layer is 1nm, the thickness of the silicon oxide passivation layer deposited in the isolation region is 0.2nm, and the thickness of the aluminum oxide passivation layer is 1.5nm.

[0132] Multiple electrical performance tests were conducted on the solar cells prepared in Examples 1, 2, and Comparative Example 1. The relevant electrical performance parameters of the solar cells were tested using an IV detection device. These parameters included the photoelectric conversion efficiency (pEFF), open-circuit voltage (Voc), fill factor (pFF), saturated dark current density generated by recombination in the quasi-neutral region reference and emitter region (J01), and saturated dark current density generated by recombination in the space charge region (J02). The average values ​​of the multiple test results for the solar cells prepared in Examples 1, 2, and Comparative Example 1 were calculated, and the results are shown in Table 1 below. Photoluminescence (PL) detection was performed on the solar cells of Example 1 and Comparative Example 1, and the PL images are shown below. Figure 7 and Figure 8 As shown.

[0133] from Figure 7 It can be seen that the solar cell obtained by the technical solution provided in Embodiment 1 of this utility model has no gray areas in the segmented area of ​​the solar cell (i.e., the edge of the solar cell segmented from the solar cell), and its measured photoluminescence performance is good, with no defects or damage at the edge. Figure 8 The presence of extended grayscale areas in the PL image of the solar cell (i.e., the edges of the solar cells cut out from the solar cell) indicates that the edges of the solar cells cut out from the solar cell prepared in Comparative Example 1 have defects and damage. This also shows that the technical solution provided by this utility model embodiment, by controlling the ratio of the specific surface area of ​​the isolation region 30 to the specific surface area of ​​the electrical functional region 20 with the emitter 21 within the range of 0.25 to 0.65, helps to passivate the isolation region 30 and avoid defects and damage at the edges of the solar cells cut out from the solar cell.

[0134] Table 1

[0135] pEFF_(%) Voc_(V) pFF (%) <![CDATA[J01(A / cm 2 )]]> <![CDATA[J02(A / cm 2 )]]> Example 1 25.87 0.7356 85.65 <![CDATA[1.32×10 -14 ]]> <![CDATA[1.64×10 -10 ]]> Example 2 25.59 0.7348 85.01 <![CDATA[1.43×10 -14 ]]> <![CDATA[1.89×10 -10 <!-- 13 -->]]> Comparative Example 1 24.84 0.7334 84.69 <![CDATA[1.66×10 -14 ]]> <![CDATA[3.44×10 -10 ]]>

[0136] Furthermore, the results in Table 1 clearly show that the photoelectric conversion efficiency, open-circuit voltage, and fill factor of the solar cells in Examples 1 and 2 are all higher than those in Comparative Example 1. Therefore, the technical solution provided by this embodiment helps to improve the photoelectric conversion efficiency, open-circuit voltage, and fill factor of solar cells. In addition, controlling the ratio of the specific surface area of ​​the isolation region 30 to the specific surface area of ​​the electrical functional region 20 with the emitter 21 also helps to improve the photoelectric conversion efficiency, open-circuit voltage, and fill factor of the solar cell, indirectly indicating that the passivation effect of the isolation region is better, and can prevent edge leakage of the solar cell cells.

[0137] Furthermore, the saturated dark current densities generated by recombination in the quasi-neutral region and emitter region, as well as the saturated dark current density generated by recombination in the space charge region, in the solar cell test results of Examples 1 and 2 are significantly lower than those of the solar cell in Comparative Example 1. This indicates that the technical solution provided by this embodiment helps reduce carrier recombination and improve carrier transport capability, and also indirectly demonstrates that the passivation effect of the isolation region is relatively good, preventing carrier recombination from occurring at the edges of the solar cell cells.

[0138] In summary, the embodiments of this utility model provide the following technical solutions:

[0139] Technical Solution 1: A solar cell, comprising: a silicon substrate 10, electrically functional regions 20 spaced apart on a first main surface of the silicon substrate 10, an isolation region 30 of a planar structure disposed on the first main surface of the silicon substrate 10 between adjacent electrically functional regions 20, and a first metal electrode 40, wherein...

[0140] For the first main surface of the silicon substrate 10, the specific surface area corresponding to the isolation region 30 is smaller than the specific surface area corresponding to the electrical functional region 20;

[0141] The electrical functional region 20 includes an emitter 21 and a first passivation structure stacked from the inside to the outside;

[0142] The isolation region 30 includes a second passivation structure;

[0143] The first metal electrode 40 passes through the first passivation structure and is electrically connected to the emitter 21;

[0144] Technical Solution 2: The solar cell according to Technical Solution 1,

[0145] For the first main surface of the silicon substrate 10, the ratio of the specific surface area corresponding to the isolation region 30 to the specific surface area corresponding to the electrical functional region 20 is 0.25 to 0.65.

[0146] Technical Solution 3: The solar cell according to Technical Solution 1,

[0147] For the first main surface of the silicon substrate 10, the region corresponding to the isolation region 30 is lower than the region corresponding to the electrical functional region 20.

[0148] Technical Solution 4: The solar cell according to Technical Solution 3,

[0149] For the first main surface of the silicon substrate 10, the height difference between the region corresponding to the isolation region 30 and the region corresponding to the electrical functional region 20 is 2μm to 15μm.

[0150] Technical Solution 5: The solar cell according to Technical Solution 1,

[0151] The thickness of the second passivation structure is greater than the thickness of the first passivation structure.

[0152] Technical Solution 6: The solar cell according to Technical Solution 1 or 5,

[0153] The first passivation structure includes: a first silicon oxide passivation layer 22 and a first aluminum oxide passivation layer 23 stacked from the inside to the outside;

[0154] The second passivation structure includes a second silicon oxide passivation layer 31 and a second aluminum oxide passivation layer 32 stacked from the inside to the outside.

[0155] Technical Solution 7: The solar cell according to Technical Solution 6,

[0156] The thickness of the second silicon oxide passivation layer 31 is greater than the thickness of the first silicon oxide passivation layer 22;

[0157] And / or,

[0158] The thickness of the second alumina passivation layer 32 is greater than the thickness of the first alumina passivation layer 23.

[0159] Technical solution 8: The solar cell according to technical solution 6 further includes:

[0160] A first front passivation and antireflection layer 24 is disposed on the outside of the first alumina passivation layer 23;

[0161] A second front passivation antireflection layer 33 is disposed on the outside of the second alumina passivation layer 32.

[0162] Technical Solution 9: A solar cell according to any one of Technical Solutions 1 to 5, 7 and 8.

[0163] The width of the isolation zone 30 is 20μm to 1000μm.

[0164] Technical Solution 10: The solar cell according to Technical Solution 9,

[0165] Preferably, the width of the isolation zone 30 is 20μm to 600μm;

[0166] Technical Solution 11: A solar cell according to any one of technical solutions 1 to 5, 7 and 8.

[0167] The thickness of the emitter 21 is 0.5 μm to 1.5 μm.

[0168] Technical Solution 12: A solar cell according to any one of Technical Solutions 1 to 5, 7 and 8,

[0169] The second passivation structure is formed simultaneously with the first passivation structure.

[0170] Technical Solution 13: A solar cell according to any one of Technical Solutions 1 to 5, 7 and 8,

[0171] The electrical functional area 20 has a velvety surface structure.

[0172] Technical Solution 14: The solar cell according to any one of technical solutions 1 to 5, 7 and 8 further includes:

[0173] A tunneling oxide layer 50, a doped polycrystalline silicon layer 60, and a back passivation antireflection layer 70 are stacked from the inside to the outside on the second main surface of the silicon substrate 10.

[0174] and a second metal electrode 80, which passes through the back passivation antireflection layer 70 and is electrically connected to the doped polysilicon layer 60.

[0175] Technical Solution 15: The solar cell according to any one of technical solutions 1 to 5, 7, and 8 further includes: an edge passivation region 90 of a planar structure disposed on two opposite edges of the first main surface of the silicon substrate 10, wherein...

[0176] The edge passivation region 90 is parallel to the isolation region 30;

[0177] For the first main surface of the silicon substrate 10, the specific surface area corresponding to the edge passivation region 90 is smaller than the specific surface area corresponding to the electrical functional region 20, and the region corresponding to the edge passivation region 90 is lower than the region corresponding to the electrical functional region 20.

[0178] The edge passivation region 90 includes a third passivation structure for blocking the emitter 21 from extending to the edge.

[0179] Technical Solution 16: The solar cell according to Technical Solution 15,

[0180] The thickness of the third passivation structure is greater than the thickness of the first passivation structure;

[0181] And / or,

[0182] The width of the edge passivation region 90 is half the width of the isolation region 30.

[0183] Technical Solution 17: The solar cell according to Technical Solution 1,

[0184] The cutting position of the solar cell coincides with the centerline of the extending direction of the isolation region 30.

[0185] Technical Solution 18: A photovoltaic module, comprising: solar cells obtained by cutting solar cells according to any one of Technical Solutions 1 to 17, wherein,

[0186] The solar cell includes: a silicon substrate 10, an electrical functional region 20, and an edge isolation region 30';

[0187] The electrical functional region 20 and the edge isolation region 30' are disposed side by side on the first main surface of the silicon substrate 10, and the electrical functional region 20 and the edge isolation region 30' extend in the same direction;

[0188] The electrical functional region 20 includes an emitter 21 and a first passivation structure stacked from the inside to the outside;

[0189] The edge isolation region 30' is provided corresponding to at least one edge of the battery cell and includes a second passivation structure;

[0190] For the first main surface of the silicon substrate 10, the specific surface area corresponding to the edge isolation region 30' is smaller than the specific surface area corresponding to the electrical functional region 20, and the region corresponding to the edge isolation region 30' is lower than the region corresponding to the electrical functional region 20.

[0191] The above steps are provided only to help understand the structure, method, and core idea of ​​this utility model. For those skilled in the art, various improvements and modifications can be made to this utility model without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this utility model.

Claims

1. A solar cell, characterized by, Comprising: a silicon substrate (10), electrically functional regions (20) arranged at intervals on a first main surface of the silicon substrate (10), isolation regions (30) of planar structure provided on the first main surface of the silicon substrate (10) between adjacent ones of the electrically functional regions (20), and a first metal electrode (40), wherein a specific surface area corresponding to the isolation regions (30) is smaller than a specific surface area corresponding to the electrically functional regions (20) for the first main surface of the silicon substrate (10); the electrically functional regions (20) include an emitter (21) and a first passivation structure arranged in layers from inside to outside; the isolation regions (30) include a second passivation structure; the first metal electrode (40) passes through the first passivation structure and is electrically connected to the emitter (21).

2. The solar cell according to claim 1, wherein a ratio of the specific surface area corresponding to the isolation regions (30) to the specific surface area corresponding to the electrically functional regions (20) is 0.25 to 0.65 for the first main surface of the silicon substrate (10).

3. The solar cell according to claim 1, wherein an area corresponding to the isolation regions (30) is lower than an area corresponding to the electrically functional regions (20) for the first main surface of the silicon substrate (10).

4. The solar cell according to claim 3, wherein a height difference between the area corresponding to the isolation regions (30) and the area corresponding to the electrically functional regions (20) is 2 μm to 15 μm for the first main surface of the silicon substrate (10).

5. The solar cell according to claim 1, wherein a thickness of the second passivation structure is greater than a thickness of the first passivation structure.

6. The solar cell according to claim 1 or 5, wherein the first passivation structure includes a first silicon oxide passivation layer (22) and a first aluminum oxide passivation layer (23) arranged in layers from inside to outside; the second passivation structure includes a second silicon oxide passivation layer (31) and a second aluminum oxide passivation layer (32) arranged in layers from inside to outside.

7. The solar cell according to claim 6, wherein a thickness of the second silicon oxide passivation layer (31) is greater than a thickness of the first silicon oxide passivation layer (22); and / or a thickness of the second aluminum oxide passivation layer (32) is greater than a thickness of the first aluminum oxide passivation layer (23). Further comprising:

8. The solar cell of claim 6, wherein, a first front-side passivation anti-reflection layer (24) arranged outside the first aluminum oxide passivation layer (23) in layers; a second front-side passivation anti-reflection layer (33) arranged outside the second aluminum oxide passivation layer (32) in layers. Further comprising:

9. The solar cell according to any one of claims 1 to 5, 7 and 8, characterized in that, an edge passivation region (90) of planar structure provided on opposite edges of the first main surface of the silicon substrate (10), wherein the edge passivation region (90) is parallel to the isolation regions (30); and the first metal electrode (40) passes through the edge passivation region (90) and is electrically connected to the emitter (21). A specific surface area corresponding to the edge passivation region (90) is smaller than a specific surface area corresponding to the electrically functional region (20) for the first main surface of the silicon substrate (10), and an area corresponding to the edge passivation region (90) is lower than an area corresponding to the electrically functional region (20); The edge passivation region (90) includes a third passivation structure.

10. The solar cell according to any one of claims 1 to 5, 7 and 8, wherein A width of the isolation region (30) is 20 μm to 1000 μm.

11. The solar cell according to claim 10, wherein A width of the isolation region (30) is 20 μm to 600 μm.

12. The solar cell according to any one of claims 1 to 5, 7 and 8, wherein A thickness of the emitter (21) is 0.5 μm to 1.5 μm.

13. The solar cell according to any one of claims 1 to 5, 7 and 8, wherein The second passivation structure is formed synchronously with the first passivation structure.

14. The solar cell according to any one of claims 1 to 5, 7 and 8, wherein The electrically functional region (20) is a textured structure.

15. The solar cell according to any one of claims 1 to 5, 7 and 8, characterized in that, Further comprising: A tunneling oxide layer (50), a doped polysilicon layer (60) and a back surface passivation anti-reflection layer (70) are disposed in a stack from inside to outside on a second main surface of the silicon substrate (10); and a second metal electrode (80) which penetrates through the back surface passivation anti-reflection layer (70) and is electrically connected to the doped polysilicon layer (60).

16. The solar cell according to claim 9, wherein A thickness of the third passivation structure is greater than a thickness of the first passivation structure; and / or A width of the edge passivation region (90) is half of a width of the isolation region (30).

17. The solar cell according to claim 1, wherein A cutting position of the solar cell coincides with a center line in an extension direction of the isolation region (30).

18. A photovoltaic module, characterized by Including: A solar cell piece cut from the solar cell according to any one of claims 1 to 17, wherein The solar cell piece includes a silicon substrate (10), an electrically functional region (20) and an edge isolation region (30'); The electrically functional region (20) and the edge isolation region (30') are disposed side by side on a first main surface of the silicon substrate (10), and an extension direction of the electrically functional region (20) and the edge isolation region (30') is consistent; The electrically functional region (20) includes an emitter (21) and a first passivation structure disposed in a stack from inside to outside; The edge isolation region (30') is disposed corresponding to at least one edge of the solar cell piece, and includes a second passivation structure; A specific surface area corresponding to the edge isolation region (30') is smaller than a specific surface area corresponding to the electrically functional region (20) for the first main surface of the silicon substrate (10), and an area corresponding to the edge isolation region (30') is lower than an area corresponding to the electrically functional region (20).

Images