Pixel and display device including same

Abstract

The utility model relates to a pixel and a display device. The pixel includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling an emission duration of the light emitting element based on the data voltage and the sweep signal; and a constant current generator that supplies a driving current having a constant level to the light emitting element based on the constant current generation voltage. The swept signal has a first high voltage level in a non-transmission period, and is boosted to a second high voltage level higher than the first high voltage level before lowering to a low voltage level lower than the first high voltage level in a transmission period.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display apparatus. More particularly, embodiments relate to a pixel driven by pulse width modulation and a display apparatus including the same. BACKGROUND

[0002] A display apparatus can include a plurality of pixels each including a self-emissive element. The self-emissive element can include an organic light emitting diode, a quantum dot light emitting diode, a micro light emitting diode, etc.

[0003] Generally, an organic light emitting diode can be driven by pulse amplitude modulation that controls the brightness of light emitted from the pixel by adjusting the amplitude of a driving current flowing through the organic light emitting diode.

[0004] In the case where a micro light emitting diode is driven by pulse amplitude modulation, the wavelength of light emitted from the micro light emitting diode can be shifted due to a change in the amplitude of a driving current flowing through the micro light emitting diode. To address this issue, the micro light emitting diode can be driven by pulse width modulation that controls the brightness of light emitted from the pixel by adjusting the emission time of the micro light emitting diode while keeping the amplitude of the driving current flowing through the micro light emitting diode constant. SUMMARY

[0005] Embodiments provide a pixel having low power consumption and a display apparatus including the same.

[0006] A pixel according to an embodiment can include a light emitting element including a first electrode and a second electrode, the second electrode connected to a low power line that transmits a low power voltage; a pulse width modulator that controls an emission duration of the light emitting element based on a data voltage and a sweep signal; and a constant current generator that generates a driving current having a constant level based on a constant current generation voltage to the light emitting element. The sweep signal can have a first high voltage level in a non-emission period, and can be boosted to a second high voltage level higher than the first high voltage level before being lowered to a low voltage level lower than the first high voltage level in an emission period.

[0007] In an embodiment, the sweep signal can maintain the second high voltage level for a selected period of time before being lowered to the low voltage level in the emission period.

[0008] In an embodiment, the sweep signal can be linearly lowered from the second high voltage level to the low voltage level in the emission period.

[0009] In an implementation, the pulse width modulator may include: a first driving transistor, including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first write transistor, including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to the second node; a first compensation transistor, including a gate electrode receiving a scan signal, a first electrode connected to the third node, and a second electrode connected to the first node; a first transmit control transistor, including a gate electrode receiving a transmit control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second transmit control transistor, including a gate electrode receiving a transmit control signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a first initialization transistor, including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor, including a first electrode receiving a sweep signal and a second electrode connected to the first node.

[0010] In an implementation, the first driving transistor may be a P-type transistor, and each of the first writing transistor and the first compensation transistor may be an N-type transistor.

[0011] In an implementation, the constant current generator may include: a second driving transistor, including a gate electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; a second write transistor, including a gate electrode receiving a constant current generating scan signal, a first electrode connected to a data line transmitting a constant current generating voltage, and a second electrode connected to the fifth node; a second compensation transistor, including a gate electrode receiving a constant current generating scan signal, a first electrode connected to the sixth node, and a second electrode connected to the fourth node; a third emitter control transistor, including a gate electrode receiving an emitter control signal, a first electrode receiving a second high power voltage, and a second electrode connected to the fifth node; a fourth emitter control transistor, including a gate electrode receiving an emitter control signal, a first electrode connected to the sixth node, and a second electrode connected to a first electrode of a light-emitting element; a second initialization transistor, including a gate electrode receiving a second initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the fourth node; a bypass transistor, including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting the second initialization voltage, and a second electrode connected to a first electrode of a light-emitting element; and a second capacitor, including a first electrode receiving a second high power voltage and a second electrode connected to the fourth node.

[0012] In an implementation, the second driving transistor may be a P-type transistor, and each of the second writing transistor and the second compensation transistor may be an N-type transistor.

[0013] In an implementation, the second initialization voltage line can be disconnected or electrically disconnected from the low power line.

[0014] In one implementation, a frame may include a display scan cycle in which data voltage is written and a self-scan cycle in which no data voltage is written. A second initialization gate signal may have an on-state voltage level during a first initialization cycle of the display scan cycle and a second initialization cycle of the self-scan cycle.

[0015] In one implementation, the first initialization gate signal may have a turn-on voltage level in a first initialization cycle and a turn-off voltage level in a second initialization cycle.

[0016] A pixel of a display device driven in normal mode and high brightness mode according to an embodiment may include: a light-emitting element including a first electrode and a second electrode, the second electrode being connected to a low power line transmitting a low power voltage; a pulse width modulator controlling the emission duration of the light-emitting element based on a data voltage and a sweep frequency signal; and a constant current generator providing a drive current with a constant level to the light-emitting element based on a constant current-generated voltage. The sweep frequency signal may decrease from a first high voltage level to a first low voltage level below the first high voltage level during the emission cycle of normal mode. The sweep frequency signal may increase to a second high voltage level above the first high voltage level during the emission cycle of high brightness mode before decreasing to a second low voltage level.

[0017] In this implementation, the sweep signal can maintain the second high voltage level for a selected time period during the transmission cycle of the high brightness mode before dropping to the second low voltage level.

[0018] In an implementation, the second low voltage level may be higher than the first low voltage level.

[0019] In this implementation, the maximum voltage level of the data voltage in the high-brightness mode can be equal to the maximum voltage level of the data voltage in the normal mode.

[0020] In an implementation, the pulse width modulator may include: a first driving transistor, including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first write transistor, including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to the second node; a first compensation transistor, including a gate electrode receiving a scan signal, a first electrode connected to the third node, and a second electrode connected to the first node; a first transmit control transistor, including a gate electrode receiving a transmit control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second transmit control transistor, including a gate electrode receiving a transmit control signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a first initialization transistor, including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor, including a first electrode receiving a sweep signal and a second electrode connected to the first node.

[0021] In an implementation, the constant current generator may include: a second driving transistor, including a gate electrode connected to a fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; a second write transistor, including a gate electrode receiving a constant current generating scan signal, a first electrode connected to a data line transmitting a constant current generating voltage, and a second electrode connected to the fifth node; a second compensation transistor, including a gate electrode receiving a constant current generating scan signal, a first electrode connected to the sixth node, and a second electrode connected to the fourth node; a third emitter control transistor, including a gate electrode receiving an emitter control signal, a first electrode receiving a second high power voltage, and a second electrode connected to the fifth node; a fourth emitter control transistor, including a gate electrode receiving an emitter control signal, a first electrode connected to the sixth node, and a second electrode connected to a first electrode of a light-emitting element; a second initialization transistor, including a gate electrode receiving a second initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the fourth node; a bypass transistor, including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting the second initialization voltage, and a second electrode connected to a first electrode of a light-emitting element; and a second capacitor, including a first electrode receiving a second high power voltage and a second electrode connected to the fourth node.

[0022] In an implementation, the second initialization voltage line can be disconnected or electrically disconnected from the low power line.

[0023] In one implementation, a frame may include a display scan cycle in which data voltage is written and a self-scan cycle in which no data voltage is written. A second initialization gate signal may have an on-state voltage level during a first initialization cycle of the display scan cycle and a second initialization cycle of the self-scan cycle.

[0024] In one implementation, the first initialization gate signal may have a turn-on voltage level in a first initialization cycle and a turn-off voltage level in a second initialization cycle.

[0025] The display device according to the embodiment may include: a display panel including a plurality of pixels; a scan driver that sequentially provides scan signals to the plurality of pixels; and a data driver that provides a data voltage and a constant current generation voltage to each of the plurality of pixels. Each of the plurality of pixels may include: a light-emitting element including a first electrode and a second electrode, the second electrode being connected to a low power line transmitting a low power voltage; a pulse width modulator that controls the emission duration of the light-emitting element based on the data voltage and the scan signal; and a constant current generator that provides a drive current with a constant level to the light-emitting element based on the constant current generation voltage. The scan signal may have a first high voltage level during non-emission cycles and may be raised to a second high voltage level above the first high voltage level during the emission cycle before decreasing to a low voltage level below the first high voltage level.

[0026] In the pixel and display device according to the embodiment, the sweep signal can be boosted to a second high voltage level during the transmission cycle before the sweep signal decreases, thereby preventing the increase of data voltage and high gate voltage, and thus reducing the power consumption of the pixel. Attached Figure Description

[0027] The above and other aspects, features and advantages of embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a schematic block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 It is a description Figure 1 A schematic diagram of a variable refresh rate driven display device.

[0030] Figure 3 This is a schematic circuit diagram showing pixels according to an embodiment.

[0031] Figure 4 This indicates that the display scan cycle provides... Figure 1 A schematic diagram illustrating an example of the signal and voltage of a pixel.

[0032] Figures 5 to 10This describes the display scan cycle. Figure 3 A schematic diagram of pixel operations.

[0033] Figure 11 This indicates that during the self-scan cycle, the data provided is... Figure 1 A schematic diagram illustrating an example of the signal and voltage of a pixel.

[0034] Figures 12 to 16 It describes the self-scanning cycle. Figure 3 A schematic diagram of pixel operations.

[0035] Figure 17 This is a schematic diagram showing the data voltage, scan signal, and sweep frequency signal according to the comparative example.

[0036] Figure 18 This is a schematic diagram illustrating the data voltage, scan signal, and sweep frequency signal according to an embodiment.

[0037] Figure 19 This is a schematic diagram showing the data voltage and sweep frequency signal in normal mode.

[0038] Figure 20 This is a schematic diagram showing the data voltage and sweep frequency signal in high brightness mode.

[0039] Figure 21 This is a schematic block diagram illustrating an electronic device according to an embodiment.

[0040] Figure 22 It is shown Figure 21 A schematic diagram illustrating an example of an electronic device implemented as a smartwatch. Detailed Implementation

[0041] This disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor do they limit this disclosure. For example, particular shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0042] In the accompanying drawings, the dimensions, thickness, scale, and size of components may be exaggerated for ease of description and clarity. The same reference numerals and / or figure marks always denote the same components.

[0043] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood as equivalent to "and / or".

[0044] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0045] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0046] As used in this article, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] When used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including,” “has,” “have,” and / or “having,” and variations thereof, specify the presence of the stated feature, integral, step, operation, element, component, and / or group thereof, but do not preclude the presence and / or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] It will be understood that when an element (or layer, region, part, etc.) is referred to in the specification as being "formed" on, "on" another element, "set" on, "connected to," or "attached to" another element, it can be directly formed on, directly set on, directly connected to, or directly attached to the other element, or an intervening element may be provided therebetween. It will be understood that the terms "connected to" or "attached to" can include physical connections or linkages, or electrical connections or linkages.

[0049] The phrase "in a plan view" means viewing the object from above, and the phrase "in a schematic sectional view" means viewing the cross-section of a vertically cut object from the side. Therefore, the expression "in a plan view" as used herein can mean viewing the object from above in the third z-direction. The phrase "in a schematic sectional view" means viewing the cross-section of a vertically cut object from the side in the first x-direction or the second y-direction. The third z-direction can also be referred to as the "thickness direction."

[0050] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “up” may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device located “below” or “under” another device may be placed “above” the other device. Therefore, the illustrative term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0051] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated value and mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0052] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0053] For functional blocks, units, and / or modules, embodiments can be described and illustrated in the accompanying drawings.

[0054] Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic circuits (optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0055] Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software.

[0056] It is also envisioned that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmable microprocessors and associated circuitry) performing other functions.

[0057] Without departing from the scope of this disclosure, each block, unit, and / or module of an implementation may be physically separated into two or more interactive and separate blocks, units, and / or modules.

[0058] Furthermore, without departing from the scope of this disclosure, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0059] In the following, the pixels and display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0060] Figure 1 This is a schematic block diagram illustrating a display device 100 according to an embodiment.

[0061] refer to Figure 1 The display device 100 may include a display panel 110, a scan driver 120, a data driver 130, a power management circuit 140, and a controller 150.

[0062] The display panel 110 may include pixels PX. In an embodiment, pixels PX may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. For example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0063] The scan driver 120 can sequentially provide the first scan signal SPWM[1] to the nth scan signal SPWM[n] (where n is a natural number greater than 1) to the pixel PX. The scan driver 120 can sequentially generate the first scan signal SPWM[1] to the nth scan signal SPWM[n] corresponding to the first pixel row to the nth pixel row, respectively, based on the first control signal CNT1. The first control signal CNT1 may include a scan clock signal, a scan start signal, etc.

[0064] Data driver 130 can provide data signal DS to pixel PX. Data signal DS may include data voltage VDAT and constant current generation voltage VCCG. Data driver 130 can generate data signals DS corresponding to pixel columns based on second image data IMD2 and a second control signal CNT2. In this embodiment, the second image data IMD2 may include grayscale values ​​corresponding to pixel PX. The second control signal CNT2 may include a data clock signal, a level start signal, a load signal, etc.

[0065] The power management circuit 140 can provide the pixel PX common ground with a first high power voltage VDD1, a second high power voltage VDD2, a low power voltage VSS, a first initialization voltage VINT, a second initialization voltage VAINT, a first initialization gate signal VST1, a second initialization gate signal VST2, a constant current generating scan signal SCCG, an transmit control signal EM, a sweep frequency signal SWP, and a bypass gate signal BCB. The power management circuit 140 can generate the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the first initialization voltage VINT, the second initialization voltage VAINT, the first initialization gate signal VST1, the second initialization gate signal VST2, the constant current generating scan signal SCCG, the transmit control signal EM, the sweep frequency signal SWP, and the bypass gate signal BCB based on a third control signal CNT3.

[0066] The controller 150 can control the operation (or drive) of the scan driver 120, the data driver 130, and the power management circuit 140. The controller 150 can generate a first control signal CNT1, a second image data IMD2, a second control signal CNT3, and a third control signal CNT3 based on the first image data IMD1 and the control signal CNT. In this embodiment, the first image data IMD1 may include grayscale values ​​corresponding to pixels PX. The controller 150 can convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a master clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc.

[0067] Figure 2 It is a description Figure 1 A schematic diagram of the variable refresh rate driver for the display device 100.

[0068] refer to Figure 1 and Figure 2 The display device 100 can display an image using a variable refresh rate driving method in which the driving frequency can be changed. The driving frequency can represent the frequency at which an image is displayed from the display device 100 per second (in other words, the number of frames per second).

[0069] Each of the frames FRMs in the display device 100 may include a display scan cycle DSP and at least one self-scan cycle SSP. In the display scan cycle DSP, a data voltage VDAT may be written to a pixel PX, and the pixel PX may emit light within a time period corresponding to the written data voltage VDAT. In the self-scan cycle SSP, the data voltage VDAT may not be written to the pixel PX, and the pixel PX may emit light within a time period corresponding to the data voltage VDAT written to the pixel PX in the display scan cycle DSP.

[0070] In this implementation, the length of the display scan cycle DSP can be equal to the length of the self-scan cycle SSP. However, the number of self-scan cycle SSPs included in each frame FRM can vary depending on the drive frequency. For example, when the drive frequency decreases, the number of self-scan cycle SSPs included in the frame FRM can be increased.

[0071] When the display device 100 operates at a first frequency FRQ1 (e.g., 120Hz), each frame FRM may include one display scan cycle DSP and one self-scan cycle SSP. When the display device 100 operates at a second frequency FRQ2 (e.g., 60Hz), which is lower than the first frequency FRQ1, the frame FRM may include one display scan cycle DSP and three consecutive self-scan cycles SSP. Similarly, when the display device 100 operates at a third frequency FRQ3 (e.g., 30Hz), which is lower than the second frequency FRQ2, the frame FRM may include one display scan cycle DSP and seven consecutive self-scan cycles SSP.

[0072] Figure 3 This is a schematic circuit diagram showing a pixel PX[k] according to an embodiment. Figure 3 It can represent Figure 1 The pixel PX[k] in the k-th pixel row (where k is a natural number greater than or equal to 1 and less than or equal to n) is included in the pixel PX.

[0073] refer to Figures 1 to 3 Pixel PX[k] may include a light-emitting element (LED), a pulse width modulator (PWM), and a constant current generator (CCG). The LED may emit light based on a drive current ILED. The LED may include a first electrode and a second electrode connected to a low-power line VSSL that provides a low power voltage VSS.

[0074] In this embodiment, the light-emitting element LED can be a micro light-emitting diode. A micro light-emitting diode can be defined as an ultra-small light-emitting diode with a size less than or equal to about 100 μm.

[0075] A pulse width modulator (PWM) can control the emission duration of an LED based on a data voltage (VDAT) and a sweep frequency signal (SWP).

[0076] In an implementation, the pulse width modulator (PWM) may include a first driving transistor (hereinafter referred to as the first transistor) T1, a first writing transistor (hereinafter referred to as the second transistor) T2, a first compensation transistor (hereinafter referred to as the third transistor) T3, a first emitter control transistor (hereinafter referred to as the fourth transistor) T4, a second emitter control transistor (hereinafter referred to as the fifth transistor) T5, a first initialization transistor (hereinafter referred to as the sixth transistor) T6, and a first capacitor C1.

[0077] A constant current generator (CCG) can provide a constant level of drive current (ILED) to a light-emitting element (LED) based on a constant current-generating voltage (VCCG).

[0078] In an implementation, the constant current generator CCG may include a second driving transistor (hereinafter referred to as the seventh transistor) T7, a second write transistor (hereinafter referred to as the eighth transistor) T8, a second compensation transistor (hereinafter referred to as the ninth transistor) T9, a third emitter control transistor (hereinafter referred to as the tenth transistor) T10, a fourth emitter control transistor (hereinafter referred to as the eleventh transistor) T11, a second initialization transistor (hereinafter referred to as the twelfth transistor) T12, a bypass transistor (hereinafter referred to as the thirteenth transistor) T13, and a second capacitor C2.

[0079] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be turned on based on the voltage difference between the second node N2 and the first node N1.

[0080] The second transistor T2 may include a gate electrode for receiving a scan signal SPWM[k] corresponding to pixel PX[k], a first electrode connected to a data line DL for transmitting a data signal DS, and a second electrode connected to the second node N2. The second transistor T2 may transmit a data voltage VDAT to the second node N2 in response to the scan signal SPWM[k] having a turn-on voltage level.

[0081] The third transistor T3 may include a gate electrode for receiving the scan signal SPWM[k], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may connect the third node N3 and the first node N1 in response to the scan signal SPWM[k] having a conduction voltage level. In other words, the third transistor T3 may cause the first transistor T1 diode to connect in response to the scan signal SPWM[k] having a conduction voltage level.

[0082] The fourth transistor T4 may include a gate electrode for receiving a transmit control signal EM, a first electrode for receiving a first high power voltage VDD1, and a second electrode connected to the second node N2. The fourth transistor T4 may transmit the first high power voltage VDD1 to the second node N2 in response to the transmit control signal EM having a turn-on voltage level.

[0083] The fifth transistor T5 may include a gate electrode for receiving a transmit control signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The fifth transistor T5 may connect the third node N3 and the fourth node N4 in response to the transmit control signal EM having a turn-on voltage level.

[0084] The sixth transistor T6 may include a gate electrode for receiving a first initialization gate signal VST1, a first electrode for receiving a first initialization voltage VINT, and a second electrode connected to the first node N1. The sixth transistor T6 may transmit the first initialization voltage VINT to the first node N1 in response to the first initialization gate signal VST1 having an on-state voltage level.

[0085] The seventh transistor T7 may include a gate electrode connected to the fourth node N4, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6. The seventh transistor T7 can generate a drive current ILED corresponding to the voltage difference between the fifth node N5 and the fourth node N4.

[0086] The eighth transistor T8 may include a gate electrode for receiving a constant current-generated scan signal SCCG, a first electrode connected to a data line DL, and a second electrode connected to the fifth node N5. The eighth transistor T8 may transmit a constant current-generated voltage VCCG to the fifth node N5 in response to the constant current-generated scan signal SCCG having an on-state voltage level.

[0087] The ninth transistor T9 may include a gate electrode that receives a constant current to generate a scan signal SCCG, a first electrode connected to the sixth node N6, and a second electrode connected to the fourth node N4. The ninth transistor T9 may connect the sixth node N6 and the fourth node N4 in response to a constant current having a conduction voltage level generating the scan signal SCCG. In other words, the ninth transistor T9 may connect the seventh transistor T7 diode in response to a constant current having a conduction voltage level generating the scan signal SCCG.

[0088] The tenth transistor T10 may include a gate electrode for receiving a transmit control signal EM, a first electrode for receiving a second high power voltage VDD2, and a second electrode connected to the fifth node N5. The tenth transistor T10 may transmit the second high power voltage VDD2 to the fifth node N5 in response to the transmit control signal EM having a turn-on voltage level.

[0089] The eleventh transistor T11 may include a gate electrode for receiving a transmit control signal EM, a first electrode connected to the sixth node N6, and a second electrode connected to the first electrode of the light-emitting element LED. The eleventh transistor T11 may connect the sixth node N6 and the first electrode of the light-emitting element LED in response to the transmit control signal EM having a conduction voltage level.

[0090] The twelfth transistor T12 may include a gate electrode for receiving a second initialization gate signal VST2, a first electrode for receiving a first initialization voltage VINT, and a second electrode connected to the fourth node N4. The twelfth transistor T12 may transmit the first initialization voltage VINT to the fourth node N4 in response to the second initialization gate signal VST2 having an on-state voltage level.

[0091] The thirteenth transistor T13 may include a gate electrode for receiving a bypass gate signal BCB, a first electrode connected to a second initialization voltage line VAINTL for transmitting the second initialization voltage VAINT, and a second electrode connected to the first electrode of the light-emitting element LED. The thirteenth transistor T13 may transmit the second initialization voltage VAINT to the first electrode of the light-emitting element LED in response to the bypass gate signal BCB having a conduction voltage level.

[0092] The second initialization voltage line VAINTL can be disconnected or electrically disconnected from the low power line VSSL.

[0093] When the second initialization voltage line VAINTL is connected to the low power line VSSL (in other words, when the first electrode of the thirteenth transistor T13 is connected to the second electrode of the light-emitting element LED), the leakage current flowing through the light-emitting element LED can increase when the light-emitting element LED and the thirteenth transistor T13 are connected in parallel. This leakage current can cause the light-emitting element LED to emit light unintentionally, thereby degrading the black display characteristics of the display device 100 when displaying black.

[0094] In this implementation, the second initialization voltage line VAINTL can be disconnected or electrically disconnected from the low power line VSSL, thereby allowing a current path to be formed from the first electrode of the light-emitting element LED through the thirteenth transistor T13 to the second initialization voltage line VAINTL. Therefore, the leakage current flowing through the light-emitting element LED can be reduced, thereby improving the black display characteristics of the display device 100.

[0095] In this embodiment, each of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, and the thirteenth transistor T13 can be a P-type transistor (e.g., a PMOS transistor), and each of the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth transistor T12 can be an N-type transistor (e.g., an NMOS transistor). In this embodiment, the P-type transistor can be a polysilicon transistor, and the N-type transistor can be an oxide semiconductor transistor.

[0096] The first capacitor C1 may include a first electrode for receiving the sweep frequency signal SWP and a second electrode connected to the first node N1. The first capacitor C1 can store the voltage of the first node N1. Furthermore, the first capacitor C1 can transmit changes in the sweep frequency signal SWP to the first node N1.

[0097] The second capacitor C2 may include a first electrode that receives the second high power voltage VDD2 and a second electrode connected to the fourth node N4. The second capacitor C2 may store the voltage of the fourth node N4.

[0098] Figure 4 This shows the output provided by the DSP during the display scan cycle. Figure 1 A schematic diagram illustrating an example of the signal and voltage of a pixel PX.

[0099] refer to Figures 1 to 4The display scan cycle DSP may include a first initialization cycle (hereinafter referred to as the first cycle) P1 in which the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7 are initialized; a first write cycle (hereinafter referred to as the second cycle) P2 in which a data voltage VDAT, which compensates for the threshold voltage of the first transistor T1, is written to the gate electrode of the first transistor T1; a second write cycle (hereinafter referred to as the third cycle) P3 in which a constant current generation voltage VCCG, which compensates for the threshold voltage of the seventh transistor T7, is written to the gate electrode of the seventh transistor T7; a first emission cycle (hereinafter referred to as the fourth cycle) P4 in which the light-emitting element LED emits light; and a first bypass cycle (hereinafter referred to as the fifth cycle) P5 in which the charge of the light-emitting element LED is discharged. The fourth cycle P4 may include a fourth-first cycle P4-1 and a fourth-second cycle P4-2, in which a constant level of drive current ILED flows through the light-emitting element LED, and in the fourth-second cycle P4-2, no drive current ILED flows through the light-emitting element LED. In the DSP, the cycles P1 to P3 and P5, excluding the fourth cycle P4, can be non-emission cycles.

[0100] The first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, the first initialization voltage VINT, the first initialization gate signal VST1, the second initialization gate signal VST2, the constant current generating scan signal SCCG, the transmit control signal EM, the sweep frequency signal SWP, and the bypass gate signal BCB can all be provided to the pixel PX. The scan signals SPWM[1]..., SPWM[k]..., SPWM[n] can be provided to the pixel PX sequentially row by row.

[0101] Each of the first high power voltage VDD1, the second high power voltage VDD2, the low power voltage VSS, the second initialization voltage VAINT, and the first initialization voltage VINT can be a constant voltage with a constant voltage level. In an embodiment, the voltage level VL1 of the first high power voltage VDD1 can be higher than the voltage level VL2 of the second high power voltage VDD2. For example, the voltage level VL1 of the first high power voltage VDD1 can be about 5.2V, and the voltage level VL2 of the second high power voltage VDD2 can be about 4.6V. In an embodiment, the voltage level VL4 of the second initialization voltage VAINT can be higher than or equal to the voltage level VL3 of the low power voltage VSS. For example, the voltage level VL3 of the low power voltage VSS can be about -5V, and the voltage level VL4 of the second initialization voltage VAINT can be from about -4V to about -5V.

[0102] The data signal DS can have a data voltage VDAT in the second cycle P2 and a constant current generation voltage VCCG in the third cycle P3.

[0103] Each of the first initialization gate signal VST1 and the second initialization gate signal VST2 may have an on-state voltage level (e.g., high gate voltage) in the first cycle P1 and an off-state voltage level (e.g., low gate voltage) in the second cycle P2 to the fifth cycle P5.

[0104] The constant current generating scan signal SCCG can have a turn-on voltage level (e.g., high gate voltage) in the third cycle P3, and can have a turn-off voltage level (e.g., low gate voltage) in the first cycle P1, the second cycle P2, the fourth cycle P4, and the fifth cycle P5.

[0105] Each of the scan signals SPWM[1]..., SPWM[k]..., SPWM[n] can have an on-state voltage level (e.g., high gate voltage) in the second period P2, and can have an off-state voltage level (e.g., low gate voltage) in the first period P1, the third period P3, the fourth period P4, and the fifth period P5. The scan signals SPWM[1]..., SPWM[k]..., SPWM[n] can be sequentially shifted by selected time periods (e.g., one horizontal time).

[0106] The transmit control signal EM can have an on-state voltage level (e.g., low gate voltage) in the fourth cycle P4, and can have an off-state voltage level (e.g., high gate voltage) in the first cycle P1, the second cycle P2, the third cycle P3 and the fifth cycle P5.

[0107] The sweep signal SWP can have a first high voltage level VLH1 in the first cycle P1, the second cycle P2, the third cycle P3, and the fifth cycle P5. In the fourth cycle P4, the sweep signal SWP can rise to a second high voltage level VLH2, which is higher than the first high voltage level VLH1, before falling to a second low voltage level VLL2, which is lower than the first high voltage level VLH1, and can then fall from the second high voltage level VLH2 to the second low voltage level VLL2.

[0108] In this implementation, the sweep signal SWP can maintain the second high voltage level VLH2 for a selected time period in the fourth cycle P4 before dropping to the second low voltage level VLL2.

[0109] In this implementation, the sweep signal SWP can be linearly reduced from the second high voltage level VLH2 to the second low voltage level VLL2 in the fourth cycle P4.

[0110] The bypass gate signal BCB can have an on-state voltage level (e.g., low gate voltage) in the first cycle P1, the second cycle P2, the third cycle P3 and the fifth cycle P5, and can have an off-state voltage level (e.g., high gate voltage) in the fourth cycle P4.

[0111] Figures 5 to 10 This describes the display scan cycle in the DSP. Figure 3 A schematic diagram of the operation of pixel PX[k].

[0112] refer to Figure 4 and Figure 5 In the first cycle P1, the sixth transistor T6 can be turned on in response to the first initialization gate signal VST1 having a turn-on voltage level, and the twelfth transistor T12 can be turned on in response to the second initialization gate signal VST2 having a turn-on voltage level. Therefore, the first initialization voltage VINT can be applied to the first node N1 through the sixth transistor T6, and the first initialization voltage VINT can be applied to the fourth node N4 through the twelfth transistor T12, thereby initializing the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7.

[0113] refer to Figure 4 and Figure 6 In the second cycle P2, the second transistor T2 and the third transistor T3 can be turned on in response to the scan signal SPWM[k] with a turn-on voltage level. Therefore, the data voltage VDAT that compensates for the threshold voltage VTH1 of the first transistor T1 can be applied to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3.

[0114] refer to Figure 4 and Figure 7 In the third cycle P3, the eighth transistor T8 and the ninth transistor T9 can be turned on in response to a constant current generating scan signal SCCG with a turn-on voltage level. Therefore, the constant current generating voltage VCCG that compensates for the threshold voltage VTH2 of the seventh transistor T7 can be applied to the fourth node N4 through the eighth transistor T8, the seventh transistor T7, and the ninth transistor T9.

[0115] refer to Figure 4 , Figure 8 and Figure 9In the fourth cycle P4, the transmit control signal EM can have a turn-on voltage level, a first high power voltage VDD1 can be applied to the second node N2, and a second high power voltage VDD2 can be applied to the fifth node N5. In the fourth cycle P4, the sweep signal SWP can rise from the first high voltage level VLH1 to the second high voltage level VLH2, and then linearly decrease from the second high voltage level VLH2 to the second low voltage level VLL2. The change in the sweep signal SWP can be transmitted to the first node N1 through the coupling effect of the first capacitor C1. Therefore, in the fourth cycle P4, the voltage at the first node N1 can linearly decrease from the sum of the data voltage VDAT of the threshold voltage VTH1 of the first transistor T1 and the second high voltage level VLH2.

[0116] like Figure 8 As shown, in the fourth-first cycle P4-1, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (i.e., the voltage difference between the second node N2 and the first node N1) can be less than the threshold voltage VTH1 of the first transistor T1, thereby causing the first transistor T1 to be turned off. In the fourth-first cycle P4-1, the seventh transistor T7 can generate a drive current ILED with a constant level corresponding to the voltage difference between the first electrode and the gate electrode of the seventh transistor T7 (i.e., the voltage difference between the fifth node N5 and the fourth node N4), and the light-emitting element LED can emit light with a brightness corresponding to the drive current ILED.

[0117] like Figure 9 As shown, in the fourth-second cycle P4-2, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (i.e., the voltage difference between the second node N2 and the first node N1) can be greater than the threshold voltage VTH1 of the first transistor T1, thereby causing the first transistor T1 to turn on. A first high-power voltage VDD1 can be applied to the fourth node N4 through the fourth transistor T4, the first transistor T1, and the fifth transistor T5, thereby turning off the seventh transistor T7. In the fourth-second cycle P4-2, the seventh transistor T7 can stop generating the drive current ILED, and the light-emitting element LED can stop emitting light.

[0118] In the fourth cycle P4, the drive current ILED, corresponding to the constant current generation voltage VCCG, can flow through the light-emitting element LED for a duration corresponding to the data voltage VDAT, and the light-emitting element LED can emit light with a brightness corresponding to the constant current generation voltage VCCG for a duration corresponding to the data voltage VDAT. Therefore, the brightness of the light emitted from the light-emitting element LED can correspond to the emission time of the light-emitting element LED.

[0119] refer to Figure 4 andFigure 10 In the fifth cycle P5, the thirteenth transistor T13 can be turned on in response to the bypass gate signal BCB with a turn-on voltage level. Therefore, the charge stored in the first electrode of the LED through the parasitic capacitance of the LED can be discharged to the second initialization voltage line VAINTL through the thirteenth transistor T13, thereby preventing leakage current from flowing through the LED.

[0120] Figure 11 This shows the information provided in the self-scanning cycle SSP. Figure 1 A schematic diagram illustrating an example of the signal and voltage of a pixel PX.

[0121] refer to Figures 1 to 3 as well as Figure 11 The self-scanning cycle SSP may include a second initialization cycle (hereinafter referred to as the sixth cycle) P6 in which the gate electrode of the seventh transistor T7 is initialized; a third write cycle (hereinafter referred to as the seventh cycle) P7 in which a constant current generating voltage VCCG, which compensates for the threshold voltage of the seventh transistor T7, is written to the gate electrode of the seventh transistor T7; a second emission cycle (hereinafter referred to as the eighth cycle) P8 in which the light-emitting element LED emits light; and a second bypass cycle (hereinafter referred to as the ninth cycle) P9 in which the charge of the light-emitting element LED is discharged. The eighth cycle P8 may include an eighth-first cycle P8-1 and an eighth-second cycle P8-2, in which a constant level of drive current ILED flows through the light-emitting element LED, and in the eighth-second cycle P8-2, no drive current ILED flows through the light-emitting element LED. The cycles P6, P7, and P9 in the self-scanning cycle SSP, other than the eighth cycle P8, may be non-emission cycles.

[0122] omission and reference Figure 4 The components of the described signal and voltage are substantially the same or similar to those in the reference. Figure 11 The description of the signal and voltage components.

[0123] The data signal DS can have a constant current generating voltage VCCG in the seventh cycle P7.

[0124] The first initialization gate signal VST1 can have a cutoff voltage level during the sixth cycle P6 to the ninth cycle P9. The second initialization gate signal VST2 can have a turn-on voltage level during the sixth cycle P6 and a cutoff voltage level during the seventh cycle P7 to the ninth cycle P9.

[0125] Each of the scanning signals SPWM[1]..., SPWM[k]..., SPWM[n] can have a cutoff voltage level in the sixth cycle P6 to the ninth cycle P9.

[0126] Figures 12 to 16 It describes the self-scanning cycle in SSP. Figure 3 A schematic diagram of the operation of pixel PX[k].

[0127] refer to Figure 11 and Figure 12 In the sixth cycle P6, the twelfth transistor T12 can be turned on in response to the second initialization gate signal VST2, which has a turn-on voltage level. Therefore, the first initialization voltage VINT can be applied to the fourth node N4 through the twelfth transistor T12, thereby initializing the gate electrode of the seventh transistor T7.

[0128] refer to Figure 11 and Figure 13 In the seventh cycle P7, the eighth transistor T8 and the ninth transistor T9 can be turned on in response to a constant current generating scan signal SCCG with a turn-on voltage level. Therefore, the constant current generating voltage VCCG that compensates for the threshold voltage VTH2 of the seventh transistor T7 can be applied to the fourth node N4 through the eighth transistor T8, the seventh transistor T7, and the ninth transistor T9.

[0129] refer to Figure 11 , Figure 14 and Figure 15 In the eighth cycle P8, the transmit control signal EM can have a turn-on voltage level, a first high power voltage VDD1 can be applied to the second node N2, and a second high power voltage VDD2 can be applied to the fifth node N5. In the eighth cycle P8, the sweep signal SWP can rise from the first high voltage level VLH1 to the second high voltage level VLH2, and then linearly decrease from the second high voltage level VLH2 to the second low voltage level VLL2. This change in the sweep signal SWP can be transmitted to the first node N1 through the coupling effect of the first capacitor C1. Therefore, in the eighth cycle P8, the voltage of the first node N1 can linearly decrease from the sum of the data voltage VDAT of the threshold voltage VTH1 of the first transistor T1 and the second high voltage level VLH2.

[0130] like Figure 14 As shown, in the eighth-first cycle P8-1, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (i.e., the voltage difference between the second node N2 and the first node N1) can be less than the threshold voltage VTH1 of the first transistor T1, thereby causing the first transistor T1 to be turned off. In the eighth-first cycle P8-1, the seventh transistor T7 can generate a drive current ILED with a constant level corresponding to the voltage difference between the first electrode and the gate electrode of the seventh transistor T7 (i.e., the voltage difference between the fifth node N5 and the fourth node N4), thereby causing the light-emitting element LED to emit light with a brightness corresponding to the drive current ILED.

[0131] like Figure 15 As shown, in the eighth-second cycle P8-2, the voltage difference between the first electrode and the gate electrode of the first transistor T1 (i.e., the voltage difference between the second node N2 and the first node N1) can be greater than the threshold voltage VTH1 of the first transistor T1, thereby causing the first transistor T1 to conduct. A first high-power voltage VDD1 can be applied to the fourth node N4 through the fourth transistor T4, the first transistor T1, and the fifth transistor T5, thereby turning off the seventh transistor T7. In the eighth-second cycle P8-2, the seventh transistor T7 can stop generating the drive current ILED, and the light-emitting element LED can stop emitting light.

[0132] In the eighth cycle P8, the drive current ILED corresponding to the constant current generation voltage VCCG flows through the light-emitting element LED for a duration corresponding to the data voltage VDAT written in the second cycle P2, and the light-emitting element LED emits light with a brightness corresponding to the constant current generation voltage VCCG for the duration corresponding to the data voltage VDAT written in the second cycle P2. Therefore, the brightness of the light emitted from the light-emitting element LED can be proportional to the emission time of the light-emitting element LED.

[0133] refer to Figure 11 and Figure 16 In the ninth cycle P9, the thirteenth transistor T13 can be turned on in response to the bypass gate signal BCB with a turn-on voltage level. Therefore, the charge stored in the first electrode of the LED through the parasitic capacitance of the LED can be discharged to the second initialization voltage line VAINTL through the thirteenth transistor T13, thereby preventing leakage current from flowing through the LED.

[0134] Figure 17 This is a schematic diagram showing the data voltage VDAT, the scan signal SPWN[k], and the sweep frequency signal SWP according to the comparative example.

[0135] refer to Figure 3 and Figure 17 In the comparative example, the sweep signal SWP can decrease from the first high voltage level VLH1 to the first low voltage level VLL1 in the fourth cycle P4. When pixel PX[k] emits light at maximum brightness, the data voltage VDAT can reach the maximum voltage level VLM' in the second cycle P2. At the beginning of the fourth cycle P4, the voltage corresponding to the sum of the maximum voltage level VLM' of the data voltage VDAT and the first high voltage level VLH1 can be stored in the first node N1, thereby causing pixel PX[k] to emit light at maximum brightness corresponding to the sum of the maximum voltage level VLM' of the data voltage VDAT and the first high voltage level VLH1.

[0136] like Figure 6 As shown, in order to turn on the second transistor T2, which applies the data voltage VDAT to the first electrode in the second cycle P2, a scan signal SPWM[k] with a voltage level higher than the maximum voltage level VLM' of the data voltage VDAT can be applied to the gate electrode of the second transistor T2. Therefore, the high gate voltage VGH' of the scan signal SPWM[k] can be greater than the maximum voltage level VLM' of the data voltage VDAT, thereby increasing the power consumption of pixel PX[k] as the high gate voltage VGH' increases.

[0137] Figure 18 This is a schematic diagram illustrating the data voltage VDAT, the scan signal SPWM[k], and the sweep frequency signal SWP according to an embodiment.

[0138] refer to Figure 3 and Figure 18 In this embodiment, the sweep signal SWP can decrease from a second high voltage level VLH2 (which is higher than the first high voltage level VLH1) to a second low voltage level VLL2 during the fourth cycle P4. When pixel PX[k] emits light at maximum brightness, the data voltage VDAT can reach its maximum voltage level VLM during the second cycle P2. At the beginning of the fourth cycle P4, the voltage corresponding to the sum of the maximum voltage level VLM of the data voltage VDAT and the second high voltage level VLH2 can be stored at the first node N1, so that pixel PX[k] emits light at its maximum brightness corresponding to the sum of the maximum voltage level VLM of the data voltage VDAT and the second high voltage level VLH2. In this case, since the second high voltage level VLH2 is greater than the first high voltage level VLH1, the maximum voltage level VLM of the data voltage VDAT in this embodiment can be lower than the maximum voltage level VLM' of the data voltage VDAT in the comparative example.

[0139] like Figure 6As shown, in order to turn on the second transistor T2, which applies the data voltage VDAT to the first electrode during the second cycle P2, a scan signal SPWM[k] having a voltage level higher than the maximum voltage level VLM of the data voltage VDAT can be applied to the gate electrode of the second transistor T2. Therefore, the high gate voltage VGH of the scan signal SPWM[k] can be higher than the maximum voltage level VLM of the data voltage VDAT. In this case, since the maximum voltage level VLM of the data voltage VDAT in this embodiment is lower than the maximum voltage level VLM' of the data voltage VDAT in the comparative example, the high gate voltage VGH of the scan signal SPWM[k] in this embodiment can be lower than the high gate voltage VGH' of the scan signal SPWM[k] in the comparative example. Therefore, as the high gate voltage VGH decreases, the power consumption of pixel PX[k] can be reduced.

[0140] Figure 19 This is a schematic diagram showing the data voltage VDAT and the sweep frequency signal SWP in normal mode NM. Figure 20 This is a schematic diagram showing the data voltage VDAT and the sweep frequency signal SWP in high brightness mode HBM.

[0141] refer to Figure 1 , Figure 3 , Figure 19 and Figure 20 The display device 100 can operate in either Normal Mode (NM) or High Brightness Mode (HBM) based on the maximum brightness of the image displayed by the display device 100. The maximum brightness of the image in High Brightness Mode (HBM) can be higher than the maximum brightness of the image in Normal Mode (NM). For example, the maximum brightness of the image in Normal Mode (NM) can be approximately 600 nits, while the maximum brightness of the image in High Brightness Mode (HBM) can be approximately 3000 nits.

[0142] In this implementation, the sweep signal SWP can take different forms in normal mode NM and high-brightness mode HBM. During the transmission cycle P4 / P8 of normal mode NM, the sweep signal SWP can decrease from a first high voltage level VLH1 to a first low voltage level VLL1, which is lower than the first high voltage level VLH1. During the transmission cycle P4 / P8 of high-brightness mode HBM, before decreasing to a second low voltage level VLL2, the sweep signal SWP can increase to a second high voltage level VLH2, which is higher than the first high voltage level VLH1, and can decrease from the second high voltage level VLH2 to a second low voltage level VLL2, which is lower than the second high voltage level VLH2.

[0143] In the implementation, during the transmission cycle P4 / P8 of the high-brightness mode HBM, the sweep signal SWP can maintain the second high-voltage level VLH2 for a selected time period before it drops to the second low voltage level VLL2.

[0144] In an implementation, the second low voltage level VLL2 may be higher than the first low voltage level VLL1.

[0145] At the start of emission period P4 / P8, the voltage corresponding to the sum of the data voltage VDAT and the sweep signal SWP can be stored in the first node N1, causing pixel PX[k] to emit light with a brightness corresponding to the sum of the data voltage VDAT and the sweep signal SWP. In this case, since the second high voltage level VLH2 of the sweep signal SWP at the start of emission period P4 / P8 in high-brightness mode HBM is higher than the first high voltage level VLH1 of the sweep signal SWP at the start of emission period P4 / P8 in normal mode NM, the emission time of the light-emitting element LED in high-brightness mode HBM can be greater than the emission time of the light-emitting element LED in normal mode NM. Therefore, the brightness of the light emitted from pixel PX[k] in high-brightness mode HBM can be higher than the brightness of the light emitted from pixel PX[k] in normal mode NM.

[0146] In this implementation, the maximum voltage level VLM of the data voltage VDAT in the high-brightness mode HBM can be equal to the maximum voltage level VLM of the data voltage VDAT in the normal mode NM. Since the second high voltage level VLH2 of the sweep signal SWP at the start of the emission period P4 / P8 in the high-brightness mode HBM is higher than the first high voltage level VLH1 of the sweep signal SWP at the start of the emission period P4 / P8 in the normal mode NM, even though the maximum voltage level VLM of the data voltage VDAT in the high-brightness mode HBM is equal to the maximum voltage level VLM of the data voltage VDAT in the normal mode NM, the emission time of the light-emitting element LED in the high-brightness mode HBM can also be greater than the emission time of the light-emitting element LED in the normal mode NM. Therefore, the brightness of the light emitted from pixel PX[k] in the high-brightness mode HBM can be higher than the brightness of the light emitted from pixel PX[k] in the normal mode NM.

[0147] Figure 21 This is a schematic block diagram showing an electronic device 1000 according to an embodiment. Figure 22 It is shown Figure 21 A schematic diagram illustrating an example of an electronic device 1000 implemented as a smartwatch.

[0148] refer to Figure 21 and Figure 22The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include multiple ports for communicating with devices such as video cards, sound cards, memory cards, USB devices, or other systems.

[0149] In the implementation method, such as Figure 22 As shown, the electronic device 1000 can be implemented as a smartwatch. However, this disclosure is not limited to this, and the electronic device 1000 can also be implemented as a television, mobile phone, video phone, smart board, tablet PC, vehicle navigation system, laptop computer, head-mounted display, etc.

[0150] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 can be a microprocessor, central processing unit (CPU), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In embodiments, processor 1010 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide first image data to display device 1060. Figure 1 IMD1) and control signals ( Figure 1 (CNT).

[0151] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM) and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), or mobile DRAM.

[0152] Storage device 1030 may include storage options such as solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc. I / O device 1040 may include input devices such as keyboards, keypads, touchpads, touchscreens, or mice, and output devices such as speakers or printers. Power supply 1050 provides the power required for the operation of electronic device 1000. Display device 1060 can be connected to other components via a bus or other communication link. Display device 1060 may correspond to... Figure 1The display device 100. Therefore, the display device 1060 may include pixels driven (or operated) by pulse width modulation, such as Figure 3 The pixel PX[k] shown.

[0153] The display device according to the embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, MP3 players, etc.

[0154] Embodiments have been disclosed herein, and although terminology is used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A pixel, characterized by, The pixel includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling an emission duration of the light emitting element based on a data voltage and a sweep signal; and a constant current generator providing a driving current having a constant level to the light emitting element based on a constant current generation voltage, wherein the sweep signal has a first high voltage level in a non-emission period and is boosted to a second high voltage level higher than the first high voltage level before being lowered to a low voltage level lower than the first high voltage level in an emission period.

2. The pixel of claim 1, wherein, The sweep signal maintains the second high voltage level for a selected period of time before being lowered to the low voltage level in the emission period.

3. The pixel of claim 1, wherein, The sweep signal linearly lowers from the second high voltage level to the low voltage level in the emission period.

4. The pixel of claim 1, wherein, The pulse width modulator includes: a first driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a first write transistor including a gate electrode receiving a scan signal, a first electrode connected to a data line transmitting the data voltage, and a second electrode connected to the second node; a first compensation transistor including a gate electrode receiving the scan signal, a first electrode connected to the third node, and a second electrode connected to the first node; a first emission control transistor including a gate electrode receiving an emission control signal, a first electrode receiving a first high power voltage, and a second electrode connected to the second node; a second emission control transistor including a gate electrode receiving the emission control signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a first initialization transistor including a gate electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node; and a first capacitor including a first electrode receiving the sweep signal and a second electrode connected to the first node.

5. The pixel of claim 4, wherein, The constant current generator includes: a second driving transistor including a gate electrode connected to the fourth node, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; a second write transistor including a gate electrode receiving a constant current generation scan signal, a first electrode connected to the data line transmitting the constant current generation voltage, and a second electrode connected to the fifth node; a second compensation transistor including a gate electrode receiving the constant current generation scan signal, a first electrode connected to the sixth node, and a second electrode connected to the fourth node; a third emission control transistor including a gate electrode receiving the emission control signal, a first electrode receiving a second high power voltage, and a second electrode connected to the fifth node; a fourth emission control transistor including a gate electrode receiving the emission control signal, a first electrode connected to the sixth node, and a second electrode connected to the first electrode of the light emitting element; a second initialization transistor including a gate electrode receiving a second initialization gate signal, a first electrode receiving the first initialization voltage, and a second electrode connected to the fourth node; a bypass transistor including a gate electrode receiving a bypass gate signal, a first electrode connected to a second initialization voltage line transmitting the second initialization voltage, and a second electrode connected to the first electrode of the light emitting element; and a second capacitor including a first electrode receiving the second high power voltage and a second electrode connected to the fourth node.

6. A pixel of a display device which is driven in a normal mode and a high luminance mode, characterized by, The pixel includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling an emission duration of the light emitting element based on a data voltage and a sweep signal; and a constant current generator providing a driving current having a constant level to the light emitting element based on a constant current generation voltage, wherein the sweep signal decreases from a first high voltage level to a first low voltage level lower than the first high voltage level in an emission period of the normal mode, and the sweep signal increases to a second high voltage level higher than the first high voltage level before decreasing to a second low voltage level in an emission period of the high brightness mode.

7. The pixel of claim 6, wherein, the sweep signal maintains the second high voltage level for a selected time period before decreasing to the second low voltage level in the emission period of the high brightness mode.

8. The pixel of claim 6, wherein, the second low voltage level is higher than the first low voltage level.

9. The pixel of claim 6, wherein, a maximum voltage level of the data voltage in the high brightness mode is equal to a maximum voltage level of the data voltage in the normal mode.

10. A display device, characterized by comprising: The display apparatus includes: a display panel including a plurality of pixels; a scan driver sequentially providing a scan signal to the plurality of pixels; and a data driver providing a data voltage and a constant current generation voltage to each of the plurality of pixels, wherein each of the plurality of pixels includes: a light emitting element including a first electrode and a second electrode connected to a low power line transmitting a low power voltage; a pulse width modulator controlling an emission duration of the light emitting element based on the data voltage and a sweep signal; and a constant current generator providing a driving current having a constant level to the light emitting element based on the constant current generation voltage, and the sweep signal has a first high voltage level in a non-emission period, and increases to a second high voltage level higher than the first high voltage level before decreasing to a low voltage level lower than the first high voltage level in an emission period.

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