Avalanche signal jitter elimination circuit and single-photon detector

Abstract

The utility model discloses an avalanche signal jitter elimination circuit, which comprises a second phase shifter, a second discriminator and a D flip-flop which are connected in sequence, the output end of the second discriminator is connected to the clock input end CLK of the D flip-flop, and the data input end D of the D flip-flop is connected with the output end of an avalanche signal extraction circuit. The utility model also discloses a single photon detector using the avalanche signal jitter elimination circuit. According to the technical scheme of the utility model, the front edges of avalanche signals at different moments in each sine gating period can be re-timed to positions having a relatively fixed position relationship with the gating signals, and the input avalanche signals are re-timed in real time, so that factors influencing the jitter of the avalanche signals can be effectively reduced.

Description

Technical Field

[0001] This utility model relates to the fields of quantum communication and weak light detection technology, and more specifically, to an avalanche signal de-jitter circuit and a single-photon detector. Background Technology

[0002] In practical quantum key distribution (QKD) systems, single-photon detectors primarily utilize single-photon avalanche diodes (SPADs) for single-photon detection. However, single-photon detectors exhibit relatively high noise, typically requiring active or passive quenching to suppress this noise. Due to the varying width of the injected optical pulse and the different time intervals between single-photon absorption and avalanche effect generation, the final output avalanche signal exhibits jitter. The magnitude of this jitter determines the upper limit of the detector's gating frequency. For low-speed gated detectors, the longer gating period results in a much smaller avalanche signal jitter than the gating period itself, preventing detection position identification errors. However, for high-speed gated detectors, the avalanche signal jitter may approach the gating period, further increasing during subsequent data processing and potentially leading to detection errors. In severe cases, this can prevent the QKD system from generating quantum keys. Therefore, it is necessary to consider employing techniques to reduce avalanche signal jitter, thereby decreasing error counts and supporting the secure key generation capability of the QKD system.

[0003] The patent document with publication number CN103759840A, entitled "A Semiconductor Infrared Single-Photon Detector Avalanche Signal Differentiation Device and Method", discloses a single-photon detector avalanche signal synchronous differentiation device, which includes functions such as dual-channel delay, comparator latching, and D flip-flop sampling. The maximum avalanche amplitude is found through the latching function of the comparator. The timing reference is based on the moment of the maximum avalanche amplitude. The avalanche signal and the latched signal need to have a certain timing relationship. This invention can eliminate the detection signal time jitter caused by avalanche signal amplitude changes and noise. However, since the avalanche signal amplitude and avalanche path length are inconsistent in the detector, sampling with the maximum avalanche amplitude will lose some small avalanche data, thereby reducing the effective counting rate of the detector.

[0004] Current technologies generally aim to preserve the frequency components of avalanche signals as much as possible, or discard some avalanche signals to reduce the probability of aftershocks, or use higher gating amplitudes to shorten the avalanche duration, or use integrated chip technology to reduce the parasitic parameters of the avalanche readout circuit. However, various factors that cause jitter in the system-level probe pulse output still exist, making it impossible to achieve better jitter performance in the system. Utility Model Content

[0005] The technical problem to be solved by this invention is how to effectively reduce system-level jitter while ensuring detection efficiency.

[0006] This utility model solves the above-mentioned technical problems through the following technical means: an avalanche signal debouncing circuit, including a second phase shifter, a second discriminator, and a D flip-flop connected in sequence, the output terminal of the second discriminator is connected to the clock input terminal CLK of the D flip-flop, and the data input terminal D of the D flip-flop is connected to the output terminal of the avalanche signal extraction circuit.

[0007] As a further optimized technical solution, the second phase shifter is connected to one of the output terminals of the PLL.

[0008] This utility model also provides a single-photon detector using the avalanche signal de-jitter circuit described in any of the above-mentioned schemes, including a PLL, a bias voltage generation circuit, a gating signal generation circuit, a SPAD, an avalanche signal extraction circuit, an avalanche signal de-jitter circuit, and a control unit. The two output terminals of the PLL are respectively connected to the input terminals of the second phase shifters of the gating signal generation circuit and the avalanche signal de-jitter circuit. The bias voltage generation circuit is connected to the cathode of the SPAD, the gating signal generation circuit is connected to the cathode of the SPAD, the avalanche signal extraction circuit is connected to the anode of the SPAD, and the control unit is connected to the bias voltage generation circuit, the gating signal generation circuit, and the avalanche signal extraction circuit.

[0009] As a further optimized technical solution, the gate signal generation circuit includes a first phase shifter and a first power amplifier connected in sequence. The input terminal of the first phase shifter is connected to the first output terminal of the PLL, and the output terminal of the first power amplifier is connected to the cathode of the SPAD through a capacitor C1.

[0010] As a further optimized technical solution, the avalanche signal extraction circuit includes a cascaded filtering and amplification module and a first discriminator connected in sequence. The input terminal of the cascaded filtering and amplification module is connected to the anode of the SPAD through capacitor C2. The anode of the SPAD is grounded through resistor R1. The output terminal of the first discriminator is connected to the avalanche signal debouncing circuit.

[0011] As a further optimized technical solution, the single-photon detector also includes a pulse arrival time detection circuit, which includes a time-of-arrival (TDC) and a control unit connected to the TDC. The output of the avalanche signal extraction circuit is connected to a clock distributor, and the different outputs of the clock distributor are respectively connected to the TDC and the data input D of the D flip-flop.

[0012] As a further optimized technical solution, the clock distributor is a 1:2 clock distributor.

[0013] As a further optimized technical solution, the single-photon detector also includes a cooling temperature control circuit, which is connected to the TEC and control unit in the SPAD cooling box.

[0014] As a further optimized technical solution, the control unit is a general-purpose processor, a programmable logic controller, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or any suitable combination thereof.

[0015] As a further optimized technical solution, the bias voltage generation circuit is connected to the cathode of the SPAD through resistor R2, the gate signal generation circuit is connected to the cathode of the SPAD through capacitor C1, the avalanche signal extraction circuit is connected to the anode of the SPAD through capacitor C2, and the anode of the SPAD is grounded through resistor R1.

[0016] The advantages of this utility model are:

[0017] 1. The present invention provides a general-purpose low-jitter single-photon detector that can retime the avalanche signal leading edge at different times within each sinusoidal gating cycle to a position with a relatively fixed positional relationship with the gating signal, thereby performing real-time retime of the input avalanche signal and effectively reducing factors affecting avalanche signal jitter.

[0018] 2. This utility model uses a 1:2 clock splitter to realize two directional branches of the detection pulse. One signal is dedicated to debouncing to reduce the probability of false identification, and the other is used for security detection to monitor the system status in real time and ensure the safety of operation. The operation behaviors of the two paths do not interfere with each other, which reduces the system error rate and ensures the system security.

[0019] 3. This utility model uses a coincident signal with the same frequency and origin as the gate signal to sample the detection pulse signal. It uses a high-speed D flip-flop to realize the retiming and debouncing of the avalanche signal leading edge, eliminating errors caused by jitter. A second phase shifter is set up to adjust the delay of the coincident signal, which has the ability to dynamically adjust the timing of the detection pulse and retiming, ensuring that each detection pulse output is in a suitable window, thus improving the effectiveness of the detection event.

[0020] 4. This utility model uses a discriminator to shape a sine wave signal with a relatively slow rising edge into a square wave signal with a rapidly changing rising edge, thereby reducing the discriminative jitter of the coincident signal.

[0021] 5. The circuit designed in this utility model has universality and is applicable to the readout circuits of various high-speed gated single-photon detectors, such as low-pass filtering, band-pass filtering, interferometer filtering, etc., and will not affect the performance of the original single-photon detector.

[0022] 6. The low-jitter single-photon detector designed in this utility model has a simple structure, is easy to implement in engineering, and has low cost. It can operate in both gated detection mode and free operation mode, and has high operational adaptability and reliability. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a low-jitter sinusoidal gated single-photon detector according to an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram illustrating whether the control unit identifies the detection signal in the detection area in an embodiment of this utility model.

[0025] Figure 3 This is a schematic diagram of the avalanche signal front retiming principle in an embodiment of this utility model. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below in conjunction with the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0027] Example 1

[0028] Existing solutions for reducing avalanche signal jitter do not consider the operating mode and gating period characteristics of gated detectors in QKD systems. This results in various factors contributing to system-level probe pulse output jitter persisting, preventing the achievement of superior jitter performance. This invention provides a low-jitter single-photon detector that does not affect the original bias voltage, gating voltage, or cooling control process. While maintaining detection efficiency, it re-times the arrival time of the avalanche signal's leading edge, effectively reducing system-level jitter. It is suitable for high-speed sinusoidal gated single-photon detectors.

[0029] For QKD systems, only one photon is received per gating cycle. Therefore, all probe pulses within the same gating cycle can be considered to be caused by the corresponding optical pulse, and there is no need to distinguish the differences in their arrival times. Following this approach, a coincidence signal with the same source and frequency as the gating signal can be used to sample and re-time the avalanche signal's probe pulses, thereby achieving "de-jittering" of the pulse leading edge. The working principle of sinusoidal gating single-photon probe pulse timing re-regulation is described below.

[0030] Figure 1The circuit diagram of the low-jitter sinusoidal gated single-photon detector proposed in this utility model includes a PLL (Phase Locked Loop), a bias voltage generation circuit, a gate signal generation circuit 2, a SPAD 3 (Single Photon Avalanche Diode), an avalanche signal extraction circuit 4, an avalanche signal de-jitter circuit 5, and a control unit.

[0031] The input of the PLL is connected to a low-frequency synchronous clock signal, and the two outputs are connected to the gate signal generation circuit 2 and the avalanche signal debouncing circuit 5, respectively, to multiply the low-frequency synchronous clock signal and turn it into two identical high-frequency sine wave outputs.

[0032] The bias voltage generation circuit is connected to the cathode of SPAD 3 through resistor R2 to apply a reverse bias voltage HV to SPAD 3.

[0033] The gating signal generation circuit 2 is connected to the cathode of SPAD 3 via capacitor C1 to generate the gating voltage. The gating voltage amplitude is adjustable and the output can be turned off. Different gating voltage amplitudes combined with bias voltages can make the final voltage applied across SPAD 3 higher or lower than the avalanche breakdown voltage, allowing SPAD 3 to alternate between avalanche and quenching processes. The gating signal generation circuit 2 includes a first phase shifter and a first power amplifier connected in sequence. The input terminal of the first phase shifter is connected to the first output terminal of the PLL, and the output terminal of the first power amplifier is connected to the cathode of SPAD 3 via capacitor C1.

[0034] The avalanche signal extraction circuit 4 is connected to the anode of SPAD 3 via capacitor C2, and is used for filtering, amplifying, and discriminating the avalanche signal. The avalanche signal extraction circuit 4 includes a cascaded filtering and amplification module and a first discriminator connected in sequence. The input terminal of the cascaded filtering and amplification module is connected to the anode of SPAD 3 via capacitor C2, and the output terminal of the first discriminator is connected to the avalanche signal debouncing circuit 5. The cascaded filtering and amplification module can employ existing filtering and amplification schemes found in existing avalanche signal extraction circuits.

[0035] The avalanche signal debouncing circuit 5 uses a coincident signal with the same frequency and origin as the gate signal to sample the probe pulse signal output by the avalanche signal extraction circuit 4. A high-speed D flip-flop is used to re-timing and debouncing the leading edge of the probe pulse signal, eliminating errors caused by jitter. The avalanche signal debouncing circuit 5 includes a second phase shifter, a second discriminator, and a D flip-flop connected in sequence. The second phase shifter is connected to the second output terminal of the PLL, the output terminal of the second discriminator is connected to the clock input terminal CLK of the D flip-flop, the output terminal of the first discriminator is connected to the data input terminal D of the D flip-flop, and the output terminal of the D flip-flop outputs a valid pulse.

[0036] The control unit, as the control unit of the single-photon detector, is connected to the bias voltage generation circuit, the gate signal generation circuit 2, and the avalanche signal extraction circuit 4. It is mainly used to control the generation and stabilization of the bias voltage and gate voltage, receive the avalanche signal, and identify whether the original pulse signal output by the avalanche signal extraction circuit 4 is within the effective detection area.

[0037] The single-photon detector of this invention can operate in either free-running mode or gated mode: when the control unit controls the gate signal generation circuit 2 to close, the bias voltage generated by the bias voltage generation circuit is adjusted to be higher than the avalanche breakdown voltage, and passive quenching is completed by the resistor R2 connected in series with SPAD 3, the detector operates in free-running mode; when the control unit controls the gate signal generation circuit 2 to open, the bias voltage generated by the bias voltage generation circuit is adjusted to be lower than the avalanche breakdown voltage, and a gate voltage is applied so that the voltage across SPAD 3 exceeds the avalanche breakdown voltage and active quenching is completed by the gate voltage, the detector operates in gated mode.

[0038] This low-jitter sinusoidal gated single-photon detector may also include a cooling temperature control circuit. This circuit detects the temperature of the cold surface of the thermoelectric cooler (TEC) in the SPAD 3's cooling chamber and applies a control voltage to the TEC to cool it, thereby reducing the SPAD 3's operating temperature and lowering its thermal noise level. At this time, the control unit is connected to the cooling temperature control circuit to adjust the TEC temperature.

[0039] The overall connection relationship of the low-jitter sinusoidal gated single-photon detector is as follows:

[0040] The two output terminals of the PLL are connected to the first phase shifter and the second phase shifter respectively, which are used to multiply a low-frequency synchronous clock signal into two identical high-frequency sine wave signals for output.

[0041] One signal from the PLL is input to the first phase shifter, and the other signal is input to the second phase shifter. The first phase shifter is used to adjust the path delay of the high-frequency sinusoidal signal so that the optical signal arrives at SPAD 3 at the opening moment. The first power amplifier is used to amplify the low-amplitude high-frequency sinusoidal signal into a high-amplitude high-frequency sinusoidal signal, and then loads it onto the cathode of SPAD 3 through capacitor C1 as the gate signal of SPAD 3. In addition, the cathode of SPAD 3 is also connected to a bias voltage (HV high voltage) to provide a reverse bias voltage to SPAD 3. SPAD 3's anodes are connected to sampling resistor R1 and coupling capacitor C2, respectively. Resistor R1 is used to sample the generated avalanche current to obtain the avalanche signal. Capacitor C2 is used to AC couple the sampled avalanche signal and output it to the cascaded filtering and amplification module to suppress the detector's high-frequency gated differential noise and amplify the avalanche signal. The output of the cascaded filtering and amplification module is connected to the first discriminator. By setting an appropriate threshold for the first discriminator, the amplitude of the avalanche signal is discriminated and shaped to obtain the original avalanche detection pulse. The original avalanche detection pulse enters the data input terminal D of the high-speed D flip-flop (DFF) for timing retiming.

[0042] The other output of the PLL is connected to a second phase shifter as a coincidence signal. The second phase shifter adjusts the coincidence position so that the coincidence signal can sample the probe pulse signal output from the first discriminator at an appropriate position. The output signal of the second phase shifter enters the second discriminator, where an appropriate threshold is set to shape the coincidence signal, converting it into a square wave signal. This further improves the edge rate of the coincidence signal and reduces its leading-edge jitter. The coincidence signal, after being discriminated by the second discriminator, enters the clock input CLK of the high-speed D flip-flop. Under the action of the coincidence signal, the leading edge of the probe pulse signal is re-tied to the leading edge of the coincidence signal by the high-speed D flip-flop.

[0043] The dejitter process of this low-jitter sinusoidal gated single-photon detector includes the following steps:

[0044] 1. A low-frequency synchronous clock signal (Sync clk, e.g., 100kHz) is connected to the PLL. The PLL multiplies the low-frequency synchronous clock signal to a high-frequency synchronous clock signal (e.g., 1.25GHz) and outputs two sine signals. One sine signal is loaded onto the SPAD 3 cathode after passing through the first phase shifter and the first power amplifier, serving as the gate signal for the single-photon detector. The other sine signal is generated into a periodic square wave signal after passing through the second phase shifter and the second discriminator, serving as the coincidence signal connected to the clock input terminal CLK of the high-speed D flip-flop.

[0045] 2. When an optical signal arrives at SPAD 3, the first phase shifter is adjusted to align the gating signal with the optical signal, allowing SPAD 3 to receive photon injection and generate an avalanche current during the opening time. The avalanche current is sampled by resistor R1, AC coupled by capacitor C2, and then filtered and amplified before entering the first discriminator for amplitude discrimination, outputting a detection pulse signal.

[0046] 3. The probe pulse signal enters the data input terminal D of the high-speed D flip-flop for debouncing. By adjusting the second phase shifter, the coincidence signal entering the clock input terminal CLK is aligned with the probe pulse signal entering the data input terminal D. This re-timings the leading edge of the probe pulse signals (i.e., the avalanche signal) generated at different times within the same gating cycle to the leading edge of the coincidence signal, thereby achieving timing reordering of the avalanche signal.

[0047] In step 3, the specific process of retiming the avalanche signal by re-timing the leading edge of the probe pulse signals (i.e., the avalanche signal) generated at different times within the same gating cycle to the leading edge of the coincidence signal is as follows:

[0048] The next state of the output Q of the D flip-flop depends on the level of the data input D when the rising edge of the clock input CLK arrives. When the rising edge of the clock input CLK arrives, if the data input D is high, the output Q is high; otherwise, the output Q is low. That is, the next state of the output Q of the D flip-flop is Q* = D. Figure 3 As shown, the leading edge position of the original avalanche detection pulse signal generated within each gate signal (GATE) cycle is inconsistent, exhibiting a certain degree of difference. This is the source of jitter in the detection pulse signal; the jitter of the leading edge of the detection pulse signal relative to the leading edge of the gate signal constitutes the avalanche signal jitter. Under the action of the coincidence signal, the detection pulse signal at the data input terminal D of the D flip-flop is sampled. That is, the level of the detection pulse signal is sampled at the rising edge of the coincidence signal by the D flip-flop. This allows the detection pulse signals at different leading edge positions to be retied to the rising edge of the corresponding coincidence signal, thereby obtaining an effective detection pulse signal. This achieves retiming processing of the detection pulse signal, i.e., the leading edge of the avalanche signal, reducing the jitter of the detection pulse signal.

[0049] In this invention, the control unit can be implemented as a general-purpose processor, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or any suitable combination thereof for performing the functions described in this disclosure.

[0050] Example 2

[0051] Based on Embodiment 1 above, this utility model further includes a pulse arrival time detection circuit. This circuit includes a TDC (Time-to-Digital Converter) and a control unit connected to the TDC. The output of the first discriminator is connected to a 1:2 clock distributor. The first output of the 1:2 clock distributor is connected to the TDC, and the second output is connected to the data input D of a D flip-flop. The discriminated raw avalanche detection pulse is split into two paths after passing through the 1:2 clock distributor. One path is sent to the TDC as a monitoring signal to monitor the arrival time of the raw avalanche detection pulse. The other path is entered into the data input D of the high-speed D flip-flop as a detection pulse signal for timing re-timing.

[0052] The control unit (e.g., FPGA) identifies whether the avalanche detection pulse entering the TDC is within the effective detection area, such as... Figure 2 As shown, if an avalanche detection pulse (such as an avalanche transition zone or doorway detection signal) is detected outside the effective detection area, an alarm is generated and the effective detection pulse signal that has been re-tied by the D flip-flop is discarded.

[0053] This embodiment uses a 1:2 clock splitter to implement two directional branches for the probe pulse. One signal is dedicated to debouncing to reduce the probability of false identification, while the other is used for security detection. This allows for real-time monitoring of the system status and retains only the valid probe pulses that are re-tied by the D flip-flops within the valid probe area, ensuring operational safety. The operation behaviors of the two paths do not interfere with each other, which reduces the system error rate and ensures system security.

[0054] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. An avalanche signal debouncing circuit, characterized by, The second phase shifter, the second discriminator and the D flip-flop are sequentially connected, the output end of the second discriminator is connected to the clock input end CLK of the D flip-flop, and the data input end D of the D flip-flop is connected to the output end of the avalanche signal extraction circuit.

2. An avalanche signal debouncing circuit as claimed in claim 1, characterized in that, The second phase shifter is connected to one of the outputs of the PLL.

3. Single photon detector employing the avalanche signal debouncing circuit according to any one of claims 1 or 2, characterized in that: The control unit is connected to the bias voltage generation circuit, the gate signal generation circuit and the avalanche signal extraction circuit.

4. The single photon detector of claim 3, wherein: The gate signal generation circuit comprises a first phase shifter and a first power amplifier connected in sequence, the input end of the first phase shifter is connected to the first output end of the PLL, and the output end of the first power amplifier is connected to the cathode of the SPAD through the capacitor C1.

5. The single photon detector of claim 3, wherein: The avalanche signal extraction circuit comprises a cascade filtering and amplifying module and a first discriminator connected in sequence, the input end of the cascade filtering and amplifying module is connected to the anode of the SPAD through the capacitor C2, the anode of the SPAD is grounded through the resistor R1, and the output end of the first discriminator is connected to the avalanche signal de-bouncing circuit.

6. The single photon detector of claim 3, wherein: The pulse arrival time detection circuit comprises a TDC and a control unit connected to the TDC, the output end of the avalanche signal extraction circuit is connected to a clock distributor, and different output ends of the clock distributor are respectively connected to the TDC and the data input end D of the D flip-flop.

7. The single photon detector of claim 6, wherein: The clock distributor is a 1:2 clock distributor.

8. The single photon detector of claim 3, wherein: The refrigeration temperature control circuit is connected to the TEC in the SPAD refrigeration box and the control unit.

9. The single photon detector of claim 3, wherein: The control unit is a general processor, a programmable logic controller, a digital signal processor, an application specific integrated circuit or a field programmable gate array.

10. The single photon detector of claim 3, wherein: The bias voltage generation circuit is connected to the cathode of the SPAD through the resistor R2, the gate signal generation circuit is connected to the cathode of the SPAD through the capacitor C1, the avalanche signal extraction circuit is connected to the anode of the SPAD through the capacitor C2, and the anode of the SPAD is grounded through the resistor R1.

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