Readout circuit, readout system and solid-state imaging device
By introducing a current mirror circuit, a negative impedance transformation circuit, and a charge/discharge acceleration circuit into the CMOS image sensor, the problem of circuit performance degradation caused by the bias current of the load current source circuit is solved, and the signal establishment speed is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2026-03-13
AI Technical Summary
In existing CMOS image sensors, increasing the bias current of the load current source circuit to speed up the VSL settling time can easily lead to a limited VSL dynamic range and degraded circuit performance.
The system employs a current mirror circuit unit, a negative impedance transformation circuit unit, and a charge-discharge acceleration circuit unit. The negative impedance transformation circuit unit cancels out parasitic impedance, and the charge-discharge acceleration circuit unit provides transient current to accelerate signal establishment.
It effectively accelerates the establishment speed of small and large signals, avoids circuit performance degradation, and improves the readout efficiency of image sensors.
Smart Images
Figure CN223993709U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image sensor imaging and reading technology, and in particular to a readout circuit, a readout system, and a solid-state imaging device. Background Technology
[0002] In existing CMOS image sensors, the ADC (A / D Converter) consists of a load current source array, a comparator array, and a counter array. The load current source array provides constant current to the source follower of the pixel array. During the signal readout process of the pixel array, the charge in the PD (Photon Diode) needs to be transferred to the FD (Flowing Diffusion), causing the FD voltage to drop. This further reduces the pixel array output signal VSL (Vertical Signature Line) through the pixel SF (Source Follower).
[0003] During the readout process described above, the VSL descent process is affected by the parasitic resistance and capacitance of the metal traces and the equivalent output impedance of SF, which slows down the VSL descent process. This means that the entire image sensor needs to wait for the VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.
[0004] In traditional image sensor architectures, increasing the bias current of the load current source is typically used to accelerate VSL settling time. However, increasing the bias current often involves using a current amplifier circuit. Increasing the bias current of the load current source circuit can easily limit the dynamic range of VSL, causing the VSL to drop to a certain level and degrading circuit performance. Consequently, image readout may fail to respond. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of existing technologies where increasing the bias current of the load current source circuit can easily lead to a limited dynamic range of VSL, causing the circuit performance to deteriorate when VSL drops to a certain level. Therefore, this invention proposes a readout circuit, readout system, and solid-state imaging device.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] In a first aspect, this utility model provides a readout circuit, which is electrically connected to a pixel array unit in a pixel driving module, comprising:
[0008] A current mirror circuit unit is electrically connected to the pixel driving module, and the current mirror circuit is used to provide bias current.
[0009] The current mirror circuit unit includes: a common-source cascode current mirror;
[0010] A negative impedance transformation circuit unit is electrically connected to the current mirror circuit unit. The negative impedance transformation circuit unit is used to generate negative impedance to cancel out the parasitic impedance of the VSL itself.
[0011] The negative impedance transformation circuit unit includes: a source follower;
[0012] A charge / discharge acceleration circuit unit is provided to provide charge / discharge current during VSL establishment.
[0013] In one feasible embodiment, the common-source cascode current mirror comprises:
[0014] Two N-channel field-effect transistors are connected via a common source and common gate connection. The gate of the N-channel field-effect transistor connected via the common source and common gate connection is connected to a bias voltage. The source of the N-channel field-effect transistor connected via the common source and common gate connection is electrically connected to the pixel driving module, the negative impedance conversion circuit unit, and the charge and discharge acceleration circuit unit, respectively.
[0015] In one feasible embodiment, the negative impedance transformation circuit unit further includes:
[0016] A first capacitor is electrically connected to the pixel array unit;
[0017] A third N-channel field-effect transistor, wherein the gate of the third N-channel field-effect transistor is electrically connected to a bias voltage;
[0018] The fourth N-channel field-effect transistor has its gate electrically connected to the pixel array unit, its drain connected to a power supply, and its source electrically connected to the drain of the third N-channel field-effect transistor.
[0019] One end of the first capacitor is electrically connected to the source of the fourth N-channel field-effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit unit.
[0020] In one feasible embodiment, the third N-channel field-effect transistor serves as the bias current source for the fourth N-channel field-effect transistor, which is a source follower.
[0021] In one feasible embodiment, the charge / discharge acceleration circuit unit includes:
[0022] A voltage-to-current conversion circuit, one end of which is connected to a drain power supply voltage, is used to perform voltage-to-current conversion.
[0023] A current amplification circuit is electrically connected to the voltage-to-current conversion circuit, and the current amplification circuit is used to amplify the voltage-to-current conversion current.
[0024] In one feasible embodiment, the voltage-to-current conversion circuit includes:
[0025] The first P-channel field-effect transistor has a drain power supply voltage connected to one end, and is used to provide a current source.
[0026] The second P-channel field-effect transistor is also connected to a drain power supply voltage at one end, and is used to provide bias current.
[0027] A capacitor is disposed on one side of the second P-channel field-effect transistor and is electrically connected to the second P-channel field-effect transistor. The capacitor is a bypass capacitor of the second P-channel field-effect transistor.
[0028] The third P-channel field-effect transistor has its gate connected to a vertical signal line signal output node, and its source is connected to the second P-channel field-effect transistor.
[0029] In one feasible embodiment, the current amplification circuit includes:
[0030] The first N-channel field-effect transistor is connected to the second P-channel field-effect transistor, and the drain of the first N-channel field-effect transistor is connected to the third P-channel field-effect transistor.
[0031] The second N-channel field-effect transistor and the first N-channel field-effect transistor form a current mirror.
[0032] In a second aspect, this utility model provides an image sensing readout system that employs an image sensing readout circuit as described in any one of the first aspects.
[0033] In one feasible solution, the readout system further includes:
[0034] Pixel driving module, the pixel driving module includes: multiple pixel array units;
[0035] A pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array units in the pixel driving module.
[0036] A reference ramp generation module, which is electrically connected to the pixel driving module;
[0037] The comparator is electrically connected to both the readout circuit and the reference ramp generation module.
[0038] A counter, which is electrically connected to the comparator;
[0039] A data transmission module is electrically connected to the counter.
[0040] The third aspect of this utility model provides a solid-state imaging device, which employs an image sensing readout circuit as described in any one of the first aspects or an image sensing readout system as described in any one of the second aspects.
[0041] The beneficial effects of this utility model are as follows:
[0042] This invention, by configuring a negative impedance transformation circuit unit and a charge / discharge acceleration circuit unit, addresses the shortcomings of existing technologies. Firstly, the negative impedance transformation circuit unit, through the connection of its source follower and related circuit components, generates a negative impedance that cancels out the parasitic impedance of the VSL (Voltage-Side Array) itself, eliminating the need for an operational amplifier. This effectively accelerates the small-signal setup speed. This addresses the drawback of existing technologies where increasing the bias current of the load current source circuit easily limits the dynamic range of the VSL, leading to performance degradation when the VSL drops to a certain level. Secondly, the charge / discharge acceleration circuit unit provides a larger transient current to accelerate the large-signal setup speed. Attached Figure Description
[0043] Figure 1 This is a schematic diagram showing the usage connection of a readout circuit provided in an embodiment of this utility model;
[0044] Figure 2 This is a schematic diagram of a pixel array unit structure of a readout circuit provided in an embodiment of the present utility model;
[0045] Figure 3 This is a schematic diagram of the parasitic impedance of a readout circuit provided in an embodiment of this utility model;
[0046] Figure 4 This is a schematic diagram of the current mirror circuit unit structure of a readout circuit provided in an embodiment of the present utility model;
[0047] Figure 5 This is a schematic diagram of the negative impedance transformation circuit unit and the charge / discharge acceleration circuit unit of a readout circuit provided in an embodiment of the present invention. Detailed Implementation
[0048] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0049] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0050] In this utility model, unless otherwise explicitly specified and limited, the terms "connection," "fixing," etc., should be interpreted broadly. For example, "fixing" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0051] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0052] Reference Figures 1 to 5In this embodiment, to address the drawback of existing technologies where increasing the bias current of the load current source circuit easily leads to a limited dynamic range of the voltage level (VSL), causing circuit performance degradation when the VSL drops to a certain level, this invention provides a readout circuit 106. The readout circuit 106 is configured with a negative impedance transformation circuit unit 1062 and a charge / discharge acceleration circuit unit 1063. On one hand, the negative impedance transformation circuit unit 1062, through its source follower and related circuit components, can generate a corresponding negative impedance to cancel the parasitic impedance of the VSL itself without the need for an operational amplifier, thereby effectively accelerating the small-signal setup speed. On the other hand, the charge / discharge acceleration circuit unit 1063 provides a larger transient current to accelerate the large-signal setup speed. This effectively solves the problem of existing technologies where increasing the bias current of the load current source circuit easily leads to a limited dynamic range of the VSL, causing circuit performance degradation when the VSL drops to a certain level.
[0053] Specifically, in its first aspect, this utility model provides a readout circuit 106, which is electrically connected to the pixel array unit 100 in the pixel driving module 101. The readout circuit 106 includes a current mirror circuit unit 1061, a negative impedance transformation circuit unit 1062, and a charge / discharge acceleration circuit unit 1063. The current mirror circuit unit 1061 is electrically connected to the pixel driving module 101 and is used to provide a bias current. The current mirror circuit unit 1061 includes a common-source, common-gate current mirror. Specifically, the common-source, common-gate current mirror can be formed by two N-channel field-effect transistors (i.e., N-channel field-effect transistor 10611 and N-channel field-effect transistor 10612) connected via a common source, common gate. The gate of the N-channel field-effect transistor connected via the common source, common gate is connected to a bias voltage, and the source of the N-channel field-effect transistor connected via the common source, common gate is electrically connected to the pixel array unit 100, the negative impedance transformation circuit unit 1062, and the charge / discharge acceleration circuit unit 1063, respectively. The negative impedance transformation circuit unit 1062 is electrically connected to the current mirror circuit unit 1061. The negative impedance transformation circuit unit 1062 is used to generate negative impedance to cancel out the parasitic impedance of the VSL itself. The charge / discharge acceleration circuit unit 1063 is used to provide charge / discharge current during VSL setup.
[0054] Reference Figure 2 , Figure 3 and Figure 4In this embodiment, multiple pixel array units 100 may be provided, each including: a photodiode 1001, an N-channel field-effect transistor 1002, an N-channel field-effect transistor 1003, an N-channel field-effect transistor 1004, and an N-channel field-effect transistor 1005. When exposed to light, the photodiode 1001 completes photoelectric conversion, generating photoelectrons. During reset, the gate connection signal RST of the N-channel field-effect transistor 1003 is set high, the N-channel field-effect transistor 1003 is turned on, and the potential of the floating diffusion point FD (Floating Diffusion) 1006 is reset to a level slightly lower than the power supply VDD. Subsequently, the RST signal is set low, ending the reset operation. When signal reading is performed, the gate connection signal TX of the N-channel MOSFET 1002 is set high, and the N-channel MOSFET 1002 is turned on. Since the potential of the floating diffusion point FD1006 is higher than that of the positive terminal of the photodiode 1001, the photogenerated electrons generated by the photodiode 1001 move towards the floating diffusion point FD1006 through the N-channel MOSFET 1002, causing its voltage to drop. At this time, if the pixel row where the pixel unit 1000 is located is in the readout state, the gate connection signal SEL of the N-channel MOSFET 1005 is set high. The N-channel MOSFET 1004 is in the source follower state when the N-channel MOSFET 1005 is turned on. When the potential of the floating diffusion point FD1006 drops, it causes the voltage of the vertical signal line node VSL1007 to drop slightly less than the voltage change of the floating diffusion point FD1006. At this time, the voltage change of the vertical signal line node VSL1007 corresponds to the signal amount brought by the photogenerated electrons. Additionally, the parasitic resistance 1101 of the metal trace of the vertical signal line node VSL1007 can be represented by resistor R0, its parasitic capacitance 1102 can be represented by capacitor C0, the load current source can be represented by ideal current source 1104, and the vertical signal line output node connected to the load current source 1104 is VSL_OUT1103.
[0055] Reference Figure 5In this embodiment, to facilitate understanding of how the negative impedance transformation circuit unit 1062 generates negative impedance to cancel out the parasitic impedance (such as parasitic capacitance) on the VSL itself, the following explanation is provided. Specifically, the negative impedance transformation circuit unit 1062 further includes: a first capacitor 10621, a third N-channel field-effect transistor 10622, and a fourth N-channel field-effect transistor 10623. The first capacitor 10621 is electrically connected to the pixel array unit 100; the gate voltage of the third N-channel field-effect transistor 10622 is... The circuit is biased by a voltage; the gate of the fourth N-channel field-effect transistor 10623 is electrically connected to the pixel array unit, the drain of the fourth N-channel field-effect transistor 10623 is connected to a power supply, and the source of the fourth N-channel field-effect transistor 10623 is electrically connected to the drain of the third N-channel field-effect transistor 10622; wherein, one end of the first capacitor 10621 is electrically connected to the source of the fourth N-channel field-effect transistor 10623, and the other end of the first capacitor 10621 is electrically connected to the current mirror circuit unit 1061. In this embodiment, within the negative impedance transformation circuit unit 1062, the third N-channel field-effect transistor 10622 serves as the bias current source for the fourth N-channel field-effect transistor 10623; the fourth N-channel field-effect transistor 10623 functions as a source follower, with its gate connected to the vertical signal line output node VSL_OUT1103, its drain connected to the power supply, and its source connected to the drain of the third N-channel field-effect transistor 10622 and one end of the first capacitor 10621. The other end of the first capacitor 10621 is connected to the source of an N-channel field-effect transistor 10611 within the common-source common-gate current mirror circuit unit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 decreases to Vin = V1, assuming the input current is Iin and ignoring the body effect of the fourth N-channel field-effect transistor 10623 (e.g., connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately equal to 1. At this time, for the negative impedance transformation circuit unit 1062 in this embodiment, the transconductance of one N-channel field-effect transistor 10611 in the common-source cascode current mirror circuit unit 1061 is gm1, and its source voltage change is Vx. The source voltage change of the fourth N-channel field-effect transistor 10623 is Vy, the output impedance of the third N-channel field-effect transistor 10622 is Ro, and the transconductance of the fourth N-channel field-effect transistor 10623 is gm2. Then, according to Kirchhoff's current-voltage theorem, we can obtain:
[0056] gm2*(Vi n-Vy)+(Vx-Vy) / (1 / (s*C_N I))=Vy / Ro;
[0057] I in=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI));
[0058] After transforming and simplifying the above system of equations, we can approximately obtain:
[0059] Z in=Vi n / I in=[gm1+gm1*gm2*Ro+s*C_N I*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_N I;
[0060] In the formula, C_NI is the first capacitor. As can be seen from the above formula, at this time, the equivalent input impedance of the negative impedance transformation circuit unit 1062 at low frequency is the sum of negative resistance and negative capacitance, and the equivalent input impedance at high frequency is negative resistance, but the resistance value is small. Therefore, gm2 and Ro can be reasonably designed according to the actual situation, so that the negative impedance transformation circuit unit 1062 has a negative capacitance that can cancel the parasitic capacitance 1102, thereby accelerating the establishment speed of small signals.
[0061] Reference Figure 5In this embodiment, the charging and discharging acceleration circuit 1063 includes a voltage-to-current conversion circuit and a current amplification circuit. One end of the voltage-to-current conversion circuit is connected to a drain power supply voltage, and the voltage-to-current conversion circuit is used to perform voltage-to-current conversion. The current amplification circuit is electrically connected to the voltage-to-current conversion circuit, and the current amplification circuit is used to amplify the voltage-to-current conversion current. In this embodiment, the voltage-to-current conversion circuit includes a first P-channel field-effect transistor 10636, a second P-channel field-effect transistor 10631, a capacitor 10632, and a third P-channel field-effect transistor 10633. One end of the first P-channel field-effect transistor 10636 is connected to the drain power supply voltage, and the first P-channel field-effect transistor 10636 is used to provide a current source; one end of the second P-channel field-effect transistor 10631 is also connected to the drain power supply voltage, and the second P-channel field-effect transistor 10631 is used to provide bias current; the capacitor 10632 is disposed on one side of the second P-channel field-effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field-effect transistor 10631. The capacitor 10632 is a bypass capacitor for the second P-channel field-effect transistor 10631 (i.e., reducing the noise and voltage fluctuations generated by the second P-channel field-effect transistor 10631); the gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, and the source of the third P-channel field-effect transistor 10633 is connected to the second P-channel field-effect transistor 10631. The current amplification circuit includes a first N-channel field-effect transistor 10634 and a second N-channel field-effect transistor 10635. The first N-channel field-effect transistor 10634 is connected to the second P-channel field-effect transistor 10631, and the drain of the first N-channel field-effect transistor 10634 is connected to the third P-channel field-effect transistor 10633. The second N-channel field-effect transistor 10635 and the first N-channel field-effect transistor 10634 form a current mirror to achieve current amplification. In this embodiment, the first P-channel field-effect transistor 10636 and the second P-channel field-effect transistor 10631 can act as current sources, and the capacitor 10632 can act as a bypass capacitor for the second P-channel field-effect transistor 10631. The second P-channel field-effect transistor 10631 provides bias current to the third P-channel field-effect transistor 10633 and the first N-channel field-effect transistor 10634.The gate of the third P-channel field-effect transistor 10633 is connected to the vertical signal line output node VSL_OUT1103. The drain of the third P-channel field-effect transistor 10633 and the first N-channel field-effect transistor 10634, together with the second N-channel field-effect transistor 10635, form a current mirror. The current mirror ratio is determined by the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to that of the first N-channel field-effect transistor 10634. The current of the first P-channel field-effect transistor 10636, acting as a current source, is set to be slightly equal to the saturation current of the second N-channel field-effect transistor 10635. During the fall-out setup of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field-effect transistor 10633 drops by ΔV. At this time, the third P-channel field-effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI = C1 * dΔV / dt for the second P-channel field-effect transistor 10631. This transient current is amplified by the current mirror composed of the first N-channel field-effect transistor 10634 and the second N-channel field-effect transistor 10635. The amplification factor is as described above, which is the ratio of the width-to-length ratio of the second N-channel field-effect transistor 10635 to the first N-channel field-effect transistor 10634.
[0062] K=(W / L)_10635 / (W / L)_10634.
[0063] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field-effect transistor 10635 is K*ΔI. Since the first P-channel field-effect transistor 10636 is set to constant current operation, this transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103. If the current source current is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment period can be expressed as I+K*ΔI, and its magnitude can be adjusted by adjusting the capacitance value and the current mirror ratio K. Therefore, in this embodiment, the charge-discharge acceleration circuit 1063 accelerates the large signal establishment speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment period. It should be noted that in the charge-discharge acceleration circuit 1063 of this embodiment, all field-effect transistors operate in saturation.
[0064] Reference Figure 1The second aspect of this utility model provides a readout system employing a readout circuit 106 as described in any one of the first aspects. The readout system further includes: a pixel driving module 101, a pixel noise detection module 102, and a reference ramp generation module 103. The pixel driving module 101 includes: a plurality of pixel array units 100, which are used for photoelectric conversion; the pixel noise detection module 102 is electrically connected to the pixel driving module 101 and is used to detect the pixel array units 100 in the pixel driving module 101; the reference ramp generation module 103 is electrically connected to the pixel driving module 101; a comparator 107 is electrically connected to both the readout circuit 106 and the reference ramp generation module 103; a counter 108 is electrically connected to the comparator 107; and a data transmission module 109 is electrically connected to the counter 108. The readout system 106, equipped with a negative impedance transformation circuit unit 1062 and a charge-discharge transformation circuit unit 1063 with source followers, effectively accelerates the small-signal setup speed by utilizing the negative impedance transformation circuit unit 1062. This is achieved through the connection of its source follower and related circuit components, eliminating the need for operational amplifiers and generating a corresponding negative impedance to cancel out the parasitic impedance of the VSL itself. This effectively addresses the shortcomings of existing technologies where increasing the load current source circuit bias current easily limits the dynamic range of the VSL, leading to performance degradation when the VSL drops to a certain level. Furthermore, the charge-discharge acceleration circuit unit 1063 provides a larger transient current to accelerate the large-signal setup speed.
[0065] In some implementations, the readout system can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks. The functionality described above herein can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.
[0066] The third aspect of this utility model provides a solid-state imaging device, employing a readout circuit as described in any one of the first aspects or a readout system as described in the second aspect. Specifically, in the solid-state imaging device, the VSL signal can be established by using the aforementioned medium-current mirror circuit unit 1061, negative impedance transformation circuit unit 1062, and charge / discharge acceleration circuit unit 1063. On one hand, the negative impedance transformation circuit unit 1062, through its source follower and related circuit components, can generate a corresponding negative impedance to cancel the parasitic impedance of the VSL itself without the need for an operational amplifier, thereby effectively accelerating the small signal establishment speed. This effectively solves the problem in the prior art where increasing the bias current of the load current source circuit easily leads to a limited dynamic range of the VSL, causing the circuit performance to deteriorate when the VSL drops to a certain level. On the other hand, the charge / discharge acceleration circuit unit 1063 provides a larger transient current to accelerate the large signal establishment speed, thus meeting the imaging readout requirements.
[0067] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0068] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.
Claims
1. A readout circuit, which is electrically connected with a pixel array unit in a pixel driving module, characterized in that, The application relates to a pixel driving circuit, which comprises the following units: a current mirror circuit unit, which is electrically connected with a pixel driving module, and is used for providing a bias current; wherein the current mirror circuit unit comprises a common-source common-gate current mirror; a negative impedance conversion circuit unit, which is electrically connected with the current mirror circuit unit, and is used for generating a negative impedance to offset the parasitic impedance of VSL itself; wherein the negative impedance conversion circuit unit comprises a source follower; a charge-discharge acceleration circuit unit, which is used for providing a charge-discharge current during VSL establishment.
2. A sense circuit according to claim 1, wherein The common-source common-gate current mirror comprises: two N-channel field effect transistors which are connected through a common-source common-gate connection, the N-channel field effect transistor gate of the common-source common-gate connection is connected with a bias voltage, and the N-channel field effect transistor source of the common-source common-gate connection is electrically connected with the pixel driving module, the negative impedance conversion circuit unit and the charge-discharge acceleration circuit unit respectively.
3. A sense circuit according to claim 1, wherein The negative impedance conversion circuit unit further comprises: a first capacitor which is electrically connected with the pixel array unit; a third N-channel field effect transistor whose gate is electrically connected with a bias voltage; a fourth N-channel field effect transistor whose gate is electrically connected with the pixel array unit, whose drain is connected with a power supply, and whose source is electrically connected with the third N-channel field effect transistor drain; wherein one end of the first capacitor is electrically connected with the fourth N-channel field effect transistor source, and the other end of the first capacitor is electrically connected with the current mirror circuit unit.
4. A sense circuit according to claim 3, wherein The third N-channel field effect transistor is a bias current source of the fourth N-channel field effect transistor, and the fourth N-channel field effect transistor is a source follower.
5. A sense circuit according to claim 1, wherein The charge-discharge acceleration circuit unit comprises: a voltage-current conversion circuit, one end of which is connected with a drain power supply voltage, and which is used for voltage-current conversion; a current amplification circuit, which is electrically connected with the voltage-current conversion circuit, and which is used for amplifying the voltage-current conversion current.
6. A sense circuit according to claim 5, wherein, The voltage-current conversion circuit comprises: a first P-channel field effect transistor, one end of which is connected with a drain power supply voltage, and which is used for providing a current source; a second P-channel field effect transistor, one end of which is also connected with a drain power supply voltage, and which is used for providing a bias current; a capacitor, which is arranged on one side of the second P-channel field effect transistor, and which is electrically connected with the second P-channel field effect transistor, and is a bypass capacitor of the second P-channel field effect transistor. A third P-channel field effect transistor, a gate of the third P-channel field effect transistor being connected with a vertical signal line signal output node, a source of the third P-channel field effect transistor being connected with the second P-channel field effect transistor.
7. A sense circuit according to claim 6, wherein, The current amplification circuit comprises: A first N-channel field effect transistor, the first N-channel field effect transistor being connected with the second P-channel field effect transistor, the first N-channel field effect transistor being connected with a drain of the third P-channel field effect transistor; A second N-channel field effect transistor, the second N-channel field effect transistor and the first N-channel field effect transistor constituting a current mirror.
8. A readout system for image sensing, characterized in that, An image sensing readout circuit is adopted.
9. A readout system according to claim 8, characterised in that, The readout system further comprises: A pixel driving module, the pixel driving module comprising a plurality of pixel array units; A pixel noise detection module, the pixel noise detection module being electrically connected with the pixel driving module, the pixel noise detection module being used for detecting the pixel array units in the pixel driving module; A reference ramp generation module, the reference ramp generation module being electrically connected with the pixel driving module; A comparator, the comparator being electrically connected with the readout circuit and the reference ramp generation module respectively; A counter, the counter being electrically connected with the comparator; A data transmission module, the data transmission module being electrically connected with the counter.
10. A solid-state imaging device, characterized by comprising: An image sensing readout circuit is adopted or an image sensing readout system is adopted.