DSSD packaging structure sealed by parallel MOSFETs

Abstract

The utility model discloses a DSSD packaging structure sealed by parallel MOSFETs, and the structure comprises a metal substrate which carries the parallel MOSFETs packaged in a combined manner. The first drain electrode welding frame and the second drain electrode welding frame are symmetrically arranged on the metal substrate up and down, a plurality of groups of parallel MOSFETs are arranged above the first drain electrode welding frame and the second drain electrode welding frame, and the first drain electrode welding frame and the second drain electrode welding frame are respectively connected with drain electrodes of each group of parallel MOSFETs; the first grid electrode welding frame and the second grid electrode welding frame are arranged at the edge of the metal substrate, the first grid electrode welding frame and the second grid electrode welding frame are linearly connected with the grid electrodes of each group of parallel MOSFETs through grid electrode welding lines respectively, and grid electrode pins are arranged at the edges of the first grid electrode welding frame and the second grid electrode welding frame respectively; and the source electrode welding frame is arranged at the edge of the metal substrate, the source electrode welding frame is linearly connected with the source electrode of each group of parallel MOSFETs through a source electrode welding wire, and the source electrode welding frame is connected with the source electrode pin and is used for acquiring the common driving voltage of the MOSFETs. All the parallel MOSFETs share one driving voltage, and the design complexity and cost of the driving circuit are reduced.

Description

Technical Field

[0001] This utility model relates to the field of multi-MOSFET encapsulation technology, and in particular to a DSSD package structure for encapsulating parallel MOSFETs. Background Technology

[0002] With the rapid development of electronic devices, the demand for power devices in high-current, high-power applications is increasing. For example, in battery management systems (BMS) and other high-current applications, the high current demand leads to a significant increase in the operating temperature of power MOSFET devices. The on-resistance of MOSFETs increases with temperature, which can further lead to overheating and device failure. Therefore, achieving efficient heat dissipation and reducing temperature rise is a significant technical challenge in current electronic device design.

[0003] Current solutions typically integrate multiple MOSFET chips within a single device, distributing current and heat through parallel connection of multiple MOSFETs. However, existing MOSFET packaging solutions have limitations in achieving both heat dissipation and efficient current flow. For example, ... Figure 1 and Figure 2 As shown, existing SDDS (Source-to-Source shorted) packaged products have weak heat dissipation capabilities in high-current applications and require two different drive voltages (VG1S1 and VG2S2), which increases the complexity and cost of the drive circuit. Furthermore, existing package designs often limit the number of source wires within the frame structure, further limiting the overcurrent capability and failing to meet higher current requirements.

[0004] On the other hand, most existing packaging solutions employ multi-layered designs in their modular structures, including copper sheets, ceramic silicon wafers (such as alumina), frames, chip connections, lead soldering, and molding compounds. While this modular structure may be relatively mature in manufacturing, its internal structure is complex, and the current path deviates from a straight line, resulting in uneven current distribution. Furthermore, the heat dissipation design of existing packages is mostly limited to the bottom of the device, failing to fully utilize the top of the device for cooling, leading to uneven heat dissipation and limiting its potential for high-current applications.

[0005] The purpose of this invention is to design a parallel MOSFET co-encapsulated DSSD package structure to address the problems existing in the prior art. Utility Model Content

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a DSSD package structure for parallel MOSFET co-encapsulation, which can solve the above-mentioned technical problems.

[0007] This utility model provides a DSSD package structure for parallel MOSFET co-encapsulation, comprising:

[0008] A metal substrate supporting a combined package of parallel MOSFETs;

[0009] The first drain bonding frame D1 and the second drain bonding frame D2 are symmetrically arranged on the metal substrate. Several groups of parallel MOSFETs are arranged above the first drain bonding frame D1 and the second drain bonding frame D2. The first drain bonding frame D1 and the second drain bonding frame D2 are respectively connected to the drain of each group of parallel MOSFETs. Several drain pins are respectively arranged on the edges of the first drain bonding frame D1 and the second drain bonding frame D2.

[0010] The first gate bonding frame G1 and the second gate bonding frame G2 are disposed on the edge of the metal substrate. The first gate bonding frame G1 and the second gate bonding frame G2 are respectively connected to the gate of each group of parallel MOSFETs through gate bonding wires. Gate pins are respectively disposed at the edges of the first gate bonding frame G1 and the second gate bonding frame G2.

[0011] The source bonding frame S is disposed at the edge of the metal substrate. The source bonding frame S is directly connected to the source of each group of parallel MOSFETs through source bonding wires. The source bonding frame S is connected to the source pins and is used to obtain the common drive voltage of the MOSFETs.

[0012] Furthermore, the width of each drain pin is 7-9 mm, the width of each drain pin is greater than the width of the source pin, and the width of each drain pin is greater than the width of the gate pin.

[0013] Furthermore, the first gate bonding frame G1 and the second gate bonding frame G2 are disposed between the first drain bonding frame D1 and the second drain bonding frame D2, and both the first gate bonding frame G1 and the second gate bonding frame G2 are L-shaped bonding frames.

[0014] The source bonding frame S is disposed between the first gate bonding frame G1 and the second gate bonding frame G2, and the source bonding frame S is a T-shaped bonding frame.

[0015] Furthermore, two drain pins are respectively provided on the edges of the first drain bonding frame D1 and the second drain bonding frame D2.

[0016] Furthermore, the first gate bonding frame G1 is disposed between the first drain bonding frame D1 and the second drain bonding frame D2, the first gate bonding frame G1 is an L-shaped bonding frame, and the second gate bonding frame G2 is disposed between the second drain bonding frame D2 and the first gate bonding frame G1.

[0017] Furthermore, the source electrode bonding frame S is disposed at the edge of the first drain electrode bonding frame D1.

[0018] Furthermore, two drain pins are provided on the edge of the first drain bonding frame D1, and three drain pins are provided on the edge of the second drain bonding frame D2.

[0019] Furthermore, a ceramic silicon strip and a copper strip are attached sequentially from bottom to top above the first drain bonding frame D1 near the source bonding frame S. The ceramic silicon strip and the copper strip form a source wiring bonding frame, which serves as the source wiring of the MOSFET.

[0020] The second drain bonding frame D2 is attached with a ceramic silicon wafer strip and a copper strip from bottom to top near the top of the second gate bonding frame G2. The ceramic silicon wafer strip and the copper strip form the first gate trace bonding frame, which serves as any one of the gate traces in the parallel MOSFET.

[0021] This utility model has the following advantages:

[0022] First, the symmetrical layout of the first drain bonding frame D1 and the second drain bonding frame D2, along with a linear current path design, effectively reduces redundant resistance in the current path. The increased number of drain pins and the optimized width design ensure high current transfer capability. This addresses the problems in traditional packages where the number of source wires is limited, the current path is complex and deviates from a straight line, leading to uneven current distribution and insufficient overcurrent capacity.

[0023] Secondly, a DSSD (Drain-to-Source) structure is adopted, where all parallel MOSFETs share a single Source terminal and a single drive power supply. The first gate bonding frame G1 and the second gate bonding frame G2 are directly connected to the gates of each group of parallel MOSFETs via bonding wires, and the pin layout is optimized through an L-shaped design. This achieves a single drive power supply design, significantly simplifying the drive circuit and reducing the complexity and cost of the peripheral circuitry. It also solves the problem that traditional SDDS packages require two different drive voltages (VG1S1 and VG2S2), which increases the design complexity and cost of the drive circuit.

[0024] Third, without changing the original pin layout, the internal bonding frame position is changed, and a source routing bonding frame and a second gate routing bonding frame are added to the drain bonding frame. The source routing bonding frame and the second gate routing bonding frame are made by attaching a strip of ceramic silicon wafer on the drain bonding frame, and then attaching a copper strip on the ceramic silicon wafer. The source routing bonding frame is used to connect the source of the MOSFET and the source pad through bonding wires, and the second gate routing bonding frame is used to connect the gate of the MOSFET and the second gate pad through bonding wires. The common driving voltage of the parallel MOSFETs is directly connected through a source pad, thereby realizing the module packaging of DSSD and achieving the same technical effect as in Embodiment 1. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a circuit diagram of an existing SDDS package structure.

[0027] Figure 2 This is a diagram of the existing SDDS packaging structure.

[0028] Figure 3 This is a circuit diagram of the DSSD package structure in Example 1.

[0029] Figure 4 This is a diagram of the DSSD packaging structure in Example 1.

[0030] Figure 5 This is a wire bonding diagram of the DSSD packaging structure in Example 1.

[0031] Figure 6 This is a pin structure diagram of the DSSD package in Example 1.

[0032] Figure 7 This is a diagram of the DSSD packaging structure in Example 2.

[0033] Figure 8 This is a wire bonding diagram of the DSSD packaging structure in Example 2.

[0034] Figure 9 This is a pin structure diagram of the DSSD package in Embodiment 2. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the present invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Example 1

[0037] like Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, this embodiment provides a DSSD package structure with parallel MOSFETs, including:

[0038] A metal substrate supporting a combined package of parallel MOSFETs;

[0039] The first drain bonding frame D1 and the second drain bonding frame D2 are symmetrically arranged on the metal substrate. Several groups of parallel MOSFETs are arranged above the first drain bonding frame D1 and the second drain bonding frame D2. The first drain bonding frame D1 and the second drain bonding frame D2 are respectively connected to the drain of each group of parallel MOSFETs. Several drain pins are respectively arranged on the edges of the first drain bonding frame D1 and the second drain bonding frame D2.

[0040] The first gate bonding frame G1 and the second gate bonding frame G2 are disposed on the edge of the metal substrate. The first gate bonding frame G1 and the second gate bonding frame G2 are respectively connected to the gate of each group of parallel MOSFETs through gate bonding wires. Gate pins are respectively disposed at the edges of the first gate bonding frame G1 and the second gate bonding frame G2.

[0041] The source bonding frame S is disposed at the edge of the metal substrate. The source bonding frame S is directly connected to the source of each group of parallel MOSFETs through source bonding wires. The source bonding frame S is connected to the source pins and is used to obtain the common drive voltage of the MOSFETs.

[0042] Furthermore, the first gate bonding frame G1 and the second gate bonding frame G2 are disposed between the first drain bonding frame D1 and the second drain bonding frame D2, and both the first gate bonding frame G1 and the second gate bonding frame G2 are L-shaped bonding frames.

[0043] The source bonding frame S is disposed between the first gate bonding frame G1 and the second gate bonding frame G2, and the source bonding frame S is a T-shaped bonding frame.

[0044] Furthermore, two drain pins are respectively provided on the edges of the first drain bonding frame D1 and the second drain bonding frame D2.

[0045] Furthermore, the width of each drain pin is 7-9 mm, the width of each drain pin is greater than the width of the source pin, and the width of each drain pin is greater than the width of the gate pin.

[0046] In this embodiment, the number of source wires is limited in traditional packaging, and the current path is complex and deviates from a straight line, resulting in uneven current distribution and insufficient overcurrent capacity. By employing a symmetrical layout of the first drain bonding frame D1 and the second drain bonding frame D2, along with a straight current path design, redundant resistance in the current path is effectively reduced. Increasing the width of the drain pins and ensuring high current transfer capability through a specific width design also contributes to this improvement.

[0047] Traditional SDDS packages require two different drive voltages (VG1S1 and VG2S2), increasing the design complexity and cost of the drive circuit. By employing a DSSD (Drain to Source shorted) structure, all parallel MOSFETs share a single Source terminal and a single drive power supply. The first gate bonding frame G1 and the second gate bonding frame G2 are directly connected to the gates of each group of parallel MOSFETs via bonding wires, and the pin layout is optimized through an L-shaped design. This achieves a single drive power supply design, significantly simplifying the drive circuit and reducing the complexity and cost of peripheral circuitry.

[0048] Example 2

[0049] The difference between this embodiment and Embodiment 1 is that the positions of the first gate bonding frame G1, the second gate bonding frame G2, and the source bonding frame S on the metal substrate are different. Due to the different positions, it is also necessary to add a source wiring bonding frame and a second gate wiring bonding frame to realize the bonding wire connection between the source and the gate.

[0050] Specifically, such as Figure 7 , Figure 8 , Figure 9 As shown, the first gate bonding frame G1 is disposed between the first drain bonding frame D1 and the second drain bonding frame D2. The first gate bonding frame G1 is an L-shaped bonding frame, and the second gate bonding frame G2 is disposed between the second drain bonding frame D2 and the first gate bonding frame G1.

[0051] Furthermore, the source electrode bonding frame S is disposed at the edge of the first drain electrode bonding frame D1.

[0052] Furthermore, two drain pins are provided on the edge of the first drain bonding frame D1, and three drain pins are provided on the edge of the second drain bonding frame D2.

[0053] Furthermore, a ceramic silicon strip and a copper strip are attached sequentially from bottom to top above the first drain bonding frame D1 near the source bonding frame S. The ceramic silicon strip and the copper strip form the source wiring bonding frame 1, which serves as the source wiring of the MOSFET.

[0054] The second drain bonding frame D2 is topped with a ceramic silicon wafer strip and a copper strip from bottom to top near the second gate bonding frame G2. The ceramic silicon wafer strip and the copper strip form the first gate trace bonding frame 2, which serves as the gate trace of the MOSFET.

[0055] In this embodiment, the pin layout is the same as the existing one. While changing the pin definitions, only the internal bonding frame position needs to be changed. Simultaneously, a source routing bonding frame and a second gate routing bonding frame are added to the drain bonding frame. The source and second gate routing bonding frames are insulated by attaching a strip of ceramic silicon wafer onto the drain bonding frame, and then attaching a copper strip on top of the ceramic silicon wafer. Figure 7As shown, the source wiring frame is used to connect the source of the MOSFET and the source pad through the bonding wire, and the second gate wiring frame is used to connect the gate of the MOSFET and the second gate pad through the bonding wire. The common driving voltage of the parallel MOSFETs is directly connected through a source pad, thereby realizing the module packaging of the DSSD and achieving the same technical effect as in Embodiment 1.

[0056] The above description is only a part of the embodiments of this utility model, and does not limit the scope of protection of this utility model. Any equivalent device or equivalent process transformation made based on the content of this utility model specification and drawings, or direct or indirect application in other related technical fields, are similarly included in the patent protection scope of this utility model.

Claims

1. A parallel MOSFET-encapsulated DSSD package structure, characterized by, include: A metal substrate supporting a combined package of parallel MOSFETs; The first drain bonding frame D1 and the second drain bonding frame D2 are symmetrically arranged on the metal substrate. Several groups of parallel MOSFETs are arranged above the first drain bonding frame D1 and the second drain bonding frame D2. The first drain bonding frame D1 and the second drain bonding frame D2 are respectively connected to the drain of each group of parallel MOSFETs. Several drain pins are respectively arranged on the edges of the first drain bonding frame D1 and the second drain bonding frame D2. The first gate bonding frame G1 and the second gate bonding frame G2 are disposed on the edge of the metal substrate. The first gate bonding frame G1 and the second gate bonding frame G2 are respectively connected to the gate of each group of parallel MOSFETs through gate bonding wires. Gate pins are respectively disposed at the edges of the first gate bonding frame G1 and the second gate bonding frame G2. The source bonding frame S is disposed at the edge of the metal substrate. The source bonding frame S is directly connected to the source of each group of parallel MOSFETs through source bonding wires. The source bonding frame S is connected to the source pins and is used to obtain the common drive voltage of the MOSFETs.

2. The parallel MOSFET-encased DSSD package structure of claim 1, wherein, The width of each drain pin is 7-9 mm, the width of each drain pin is greater than the width of the source pin, and the width of each drain pin is greater than the width of the gate pin.

3. The parallel MOSFET-encased DSSD package structure of claim 1, wherein, The first gate bonding frame G1 and the second gate bonding frame G2 are disposed between the first drain bonding frame D1 and the second drain bonding frame D2, and both the first gate bonding frame G1 and the second gate bonding frame G2 are L-shaped bonding frames. The source bonding frame S is disposed between the first gate bonding frame G1 and the second gate bonding frame G2, and the source bonding frame S is a T-shaped bonding frame.

4. The parallel MOSFET-encased DSSD package structure of claim 3, wherein, Two drain pins are respectively provided on the edges of the first drain bonding frame D1 and the second drain bonding frame D2.

5. The parallel MOSFET-encased DSSD package structure of claim 1, wherein, The first gate bonding frame G1 is disposed between the first drain bonding frame D1 and the second drain bonding frame D2. The first gate bonding frame G1 is an L-shaped bonding frame, and the second gate bonding frame G2 is disposed between the second drain bonding frame D2 and the first gate bonding frame G1.

6. The parallel MOSFET-encased DSSD package structure of claim 5, wherein, The source electrode bonding frame S is located at the edge of the first drain electrode bonding frame D1.

7. The parallel MOSFET-encased DSSD package structure of claim 6, wherein, The first drain bonding frame D1 has two drain pins on its edge, and the second drain bonding frame D2 has three drain pins on its edge.

8. The parallel MOSFET-encased DSSD package structure of claim 7, wherein, The first drain bonding frame D1 is attached with a ceramic silicon strip and a copper strip from bottom to top above the source bonding frame S. The ceramic silicon strip and the copper strip form a source wiring bonding frame (1) as the source wiring of the MOSFET. The second drain bonding frame D2 is attached with a ceramic silicon wafer strip and a copper strip from bottom to top near the top of the second gate bonding frame G2. The ceramic silicon wafer strip and the copper strip form the first gate trace bonding frame (2), which serves as any one of the gate traces in the parallel MOSFET.

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