Electronic package

Abstract

An electronic package is characterized in that a protective layer is formed on a non-acting surface of an electronic component embedded in a cladding layer, and an insulating protective layer on the cladding layer is combined through the protective layer, so that the bonding property between the electronic component and the insulating protective layer can be improved, and the problem of delamination can be effectively avoided; therefore, the normal electrical conduction between the conductive element on the insulating protection layer and the conductive through hole of the interposer embedded in the cladding layer is ensured.

Description

Technical Field

[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package that can improve reliability. Background Technology

[0002] To ensure the continued miniaturization and versatility of electronic products and communication equipment, semiconductor packaging needs to evolve towards smaller dimensions to facilitate multi-pin connections, high-speed operation, and high functionality. For example, in advanced process packaging, commonly used packaging types include fan-out wiring combined with embedded component processes.

[0003] Figure 1A This is a cross-sectional schematic diagram of an existing semiconductor package 1a. (See diagram below.) Figure 1A As shown, a conventional semiconductor package 1a includes: a cover layer 15, a bridging chip 11 embedded in the cover layer 15, an intermediary chip 12 embedded in the cover layer 15, a plurality of conductive pillars 13 embedded in the cover layer 15, a plurality of functional chips 16 disposed on one surface 15b of the cover layer 15, and a plurality of solder balls 19 disposed on the other surface 15a of the cover layer 15. Any two functional chips 16 are electrically bridged to each other through the electrode pads 110 on the working surface 11a of the bridging chip 11, and any two functional chips 16 are electrically bridged to each other through the conductive vias 120 of the intermediary chip 12.

[0004] However, in the existing semiconductor package 1a manufacturing method, before implanting the solder balls 19, a leveling process of the surface 15a of the cladding layer 15 is required. At this time, there is a problem that the materials to be removed are too different, such as semiconductor materials (bridging wafer 11 and interposer 12), insulating materials (cladding layer 15) and copper materials (conductive pillars 13 and conductive vias 120), which makes it difficult to grind, resulting in an uneven grinding surface (for example, the surface of the interposer 12, the end face of the conductive via 120, the surface 15a of the cladding layer 15, the end face of the conductive pillar 13 and the surface of the bridging wafer 11 are not flush). This results in an uneven grinding surface, which is not conducive to the subsequent alignment and bonding of the solder balls 19, and thus causes poor reliability and yield of the semiconductor package 1a.

[0005] Furthermore, the back surface 11b of the bridging chip 11 has no circuit structure, thus forming a dummy region. Its silicon material is different from that of the insulating protective layer 14 used to position the solder ball 19, resulting in poor bonding between the bridging chip 11 and the insulating protective layer 14. This makes it easy for the two to delaminate, so the solder ball 19 is prone to misalignment or falling off, resulting in poor reliability and yield of the semiconductor package 1a.

[0006] Therefore, to solve the problem of solder ball 19 misalignment or falling off, the industry has added a circuit structure 112 to the back side 11b of the bridging chip 11, such as... Figure 1B As shown, the solder ball 19 is bonded to the circuit structure 112 by taking advantage of the easy bonding properties of metal.

[0007] However, the circuit structure 112 is made of copper, which causes the back side 11b of the bridging chip 11 to lose its passivation effect, resulting in copper migration. Therefore, electrical short circuits are likely to occur between the electrode pads 110 on the working surface 11a of the bridging chip 11, causing the electrical function of the bridging chip 11 to malfunction, resulting in poor reliability and yield of the semiconductor package 1.

[0008] Furthermore, such as Figure 1B The semiconductor package 1b shown still has the problem of the solder balls 19 being difficult to align and bond due to the uneven grinding surface.

[0009] Therefore, overcoming the various problems of the existing technologies has become a pressing issue for the industry. Utility Model Content

[0010] In view of the various deficiencies of the prior art, this application provides an electronic package, comprising: a cover layer having opposing first and second surfaces; an electronic component embedded in the cover layer as a bridging element, having opposing active and non-active surfaces, wherein the active surface faces the second surface of the cover layer and has a plurality of electrode pads; an intermediary element embedded in the cover layer as a bridging element, having a plurality of conductive vias; and a protective layer embedded in the first surface of the cover layer and bonded to the non-active surface of the electronic component, and not placed on the intermediary element.

[0011] This application also provides a method for manufacturing an electronic package, comprising: providing an electronic module, comprising: a cover layer having opposing first and second surfaces, an electronic component embedded in the cover layer as a bridging element, and an intermediate element embedded in the cover layer as a bridging element, wherein the electronic component has opposing active and non-active surfaces, and the active surface faces the second surface of the cover layer and has a plurality of electrode pads, while the intermediate element has a plurality of conductive vias, and a protective layer embedded in the first surface of the cover layer is disposed on the non-active surface of the electronic component and the intermediate element; and performing a leveling process on the first surface of the cover layer to remove the protective layer on the intermediate element while retaining the protective layer on the electronic component.

[0012] In the aforementioned electronic package and its manufacturing method, an insulating protective layer with multiple openings is formed on the first surface of the protective layer and the covering layer, so as to form multiple conductive blind holes in the multiple openings for connecting multiple conductive components.

[0013] In the aforementioned electronic package and its manufacturing method, an insulating protective layer with multiple openings is provided on the first surface of the intermediate element and the covering layer, so that the multiple openings correspond to the multiple conductive through holes, and a conductive blind hole electrically connected to the conductive through hole is formed in each of the openings for placing conductive elements.

[0014] In the aforementioned electronic package and its manufacturing method, a wiring structure is provided on the first surface of the protective layer and the covering layer.

[0015] In the aforementioned electronic package and its manufacturing method, the intermediate element and the first surface of the covering layer are provided with a wiring structure electrically connected to the plurality of conductive through holes.

[0016] In the aforementioned electronic package and its manufacturing method, the width of the conductive perforation is greater than 11 micrometers.

[0017] In the aforementioned electronic package and its manufacturing method, the width of the conductive perforation is less than 11 micrometers.

[0018] In the aforementioned electronic package and its manufacturing method, a circuit structure electrically connecting the electrode pad is provided on the second surface of the encapsulation layer and the functional surface of the electronic component. For example, multiple functional elements are provided on the circuit structure so that the electronic component and / or the intermediate element are electrically bridged to the multiple functional elements through the circuit structure.

[0019] In the aforementioned electronic package and its manufacturing method, a passivation structure is formed on the intermediate element to cover the ends of the plurality of conductive through holes, and the end faces of the plurality of conductive through holes are exposed in the passivation structure.

[0020] As can be seen from the above, the electronic package of this application mainly provides a protective layer embedded in the first surface of the coating layer on both the non-functional surface of the electronic component and the intermediate component. This reduces the difference in material to be removed during the leveling process of the first surface of the coating layer. Therefore, compared with the prior art, this application can avoid the problem of uneven grinding surface and form a flat grinding surface, which is beneficial to the subsequent alignment and bonding of the conductive component, thereby improving the reliability and yield of the electronic package.

[0021] Furthermore, since the non-functional surface of the electronic component has no circuit structure, it does not suffer from the existing copper migration problem. Therefore, compared with the prior art, this application can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component, thereby improving the reliability and yield of the electronic package.

[0022] In addition, although the non-functional surface of the electronic component has no circuit structure, the protective layer can improve the bonding between the electronic component and the insulating protective layer. Therefore, compared with the prior art, this application can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component and the conductive via, thereby improving the reliability and yield of the electronic package. Attached Figure Description

[0023] Figure 1A This is a cross-sectional schematic diagram of an existing semiconductor package.

[0024] Figure 1B This is a cross-sectional schematic diagram of another existing semiconductor package.

[0025] Figures 2A to 2C This is a cross-sectional schematic diagram illustrating the manufacturing method of the first embodiment of the electronic package of this application.

[0026] Figures 3A to 3F This is a cross-sectional schematic diagram illustrating the manufacturing method of a second embodiment of the electronic package of this application.

[0027] Explanation of reference numerals in the attached figures

[0028] 1a, 1b Semiconductor packages

[0029] 11 Bridge chip

[0030] 11a,21a Working surfaces

[0031] 11b Back

[0032] 110, 210 electrode pads

[0033] 112 Circuit Structure

[0034] 12 Intermediate Chips

[0035] 120, 220, 320 conductive vias

[0036] 13,23 Conductive pillars

[0037] 14,24 Insulation protective layer

[0038] 15,25 coating layers

[0039] Surfaces 15a, 15b

[0040] 16-functional chip

[0041] 19 Solder balls

[0042] 2,3 Electronic packages

[0043] 2a, 3a electronic modules

[0044] 20. Circuit Structure

[0045] 200 dielectric layers

[0046] 201 Line Layer

[0047] 21 Electronic Components

[0048] 21b Non-operating surface

[0049] 211, 221 Protective film

[0050] 212,222 Conductors

[0051] 22,32 Intermediate elements

[0052] 223 contacts

[0053] 240 opening

[0054] 241 Conductive blind hole

[0055] 25a First Surface

[0056] 25b Second Surface

[0057] 26 Functional Components

[0058] 260 conductive bumps

[0059] 261 base rubber

[0060] 27 Encapsulation layer

[0061] 28, 28a, 28b Protective layers

[0062] 29 Conductive elements

[0063] 290 Under-bump metal layer

[0064] 32a passivation structure

[0065] 321, 322 Passivation layers

[0066] 34 Wiring Structure

[0067] 340 insulation layer

[0068] 341 Wiring Layer

[0069] 342 Electrical contact pad

[0070] D,R width

[0071] S recess. Detailed Implementation

[0072] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0073] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0074] Figures 2A to 2C This is a cross-sectional schematic diagram of the manufacturing method of the first embodiment of the electronic package 2 of this application.

[0075] like Figure 2A As shown, an electronic module 2a is provided, which includes: a covering layer 25, at least one electronic component 21, at least one intermediate component 22, at least one conductive post 23, a circuit structure 20, and at least one functional component 26.

[0076] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

[0077] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin. For example, the coating layer 25 can be formed by methods such as liquid compounding, injection, lamination, or compression molding.

[0078] The electronic component 21 is embedded in the covering layer 25. The electronic component 21 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, or an inductor.

[0079] In this embodiment, the electronic component 21 is a semiconductor wafer with opposing active surfaces 21a and non-active surfaces 21b. The active surface 21a faces the second surface 25b and has multiple electrode pads 210 for bonding and electrically connecting multiple conductors 212. The conductors 212 are covered with a protective film 211, such as a passivation material. For example, the conductors 212 may be conductive lines, spherical solder balls, columnar metal materials such as copper pillars or solder bumps, or stud conductive parts made by a wire bonding machine, but are not limited to these.

[0080] Furthermore, a protective layer 28a is disposed on the non-functional surface 21b of the electronic component 21, embedded in the first surface 25a of the cladding layer 25. For example, the protective layer 28a is in the form of a die-attach film (DAF) and is exposed on the first surface 25a of the cladding layer 25.

[0081] The intermediate element 22 is a semiconductor material such as silicon substrate, having at least one conductive via 220, such as a through-silicon via (TSV).

[0082] In this embodiment, the conductive via 220 is a large-diameter specification, and its width D (e.g., Figure 2B The conductive via 220 (as shown) is larger than 11 micrometers (µm), and has a contact 223 on one end face of the intermediate element 22 to connect and electrically link multiple conductors 222, and is covered with a protective film 221 such as a passivating material. For example, the conductor 222 may be a conductive line, a spherical solder ball, or a columnar metal material such as a copper pillar or solder bump, or a stud conductive part made by a wire bonding machine, but is not limited to these.

[0083] Furthermore, a protective layer 28b is disposed on the other side of the intermediary element 22, embedded in the first surface 25a of the cover layer 25. For example, the protective layer 28b is in the form of a die attach film (DAF), which covers the other end face of the conductive via 220 and is exposed on the first surface 25a of the cover layer 25.

[0084] It should be understood that there are many embodiments of the conductive perforation 220, such as the outer periphery being covered with insulating material, and there are no particular limitations.

[0085] The conductive post 23 is embedded in the covering layer 25, and the material forming the conductive post 23 is a metal material such as copper or a solder material.

[0086] In this embodiment, one end face of the conductive post 23 is exposed on the first surface 25a of the covering layer 25.

[0087] The circuit structure 20 is disposed on the second surface 25b of the cladding layer 25 and electrically connects the conductive post 23 and the conductors 212, 222.

[0088] In this embodiment, the circuit structure 20 includes multiple dielectric layers 200 and circuit layers 201 disposed on the dielectric layers 200, such as a redistribution layer (RDL) specification. The outermost dielectric layer 200 can serve as a solder resist layer, and the outermost circuit layer 201 is exposed above the solder resist layer to serve as an electrical contact pad. Alternatively, the circuit structure 20 may also include only a single dielectric layer 200 and a single circuit layer 201.

[0089] Furthermore, the material forming the circuit layer 201 is copper, and the material forming the dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or a solder resist material such as green paint or ink.

[0090] The functional element 26 is disposed on the outermost layer of the circuit structure 20 and electrically connected to the circuit layer 201, such that the cladding layer 25, conductive pillar 23, electronic component 21 and intermediate element 22 are disposed on one side of the circuit structure 20, and the functional element 26 is disposed on the other side. The functional element 26 is an active element, a passive element or a combination of both, and the active element is, for example, a semiconductor wafer, while the passive element is, for example, a resistor, a capacitor and an inductor.

[0091] In this embodiment, the functional element 26 is a semiconductor wafer, which is electrically connected to the circuit layer 201 via multiple conductive bumps 260 using a flip-chip method, and then the conductive bumps 260 are covered with an adhesive base 261; alternatively, the functional element 26 can also be electrically connected to the circuit layer 201 via multiple bonding wires (not shown) in a wire bonding manner; or, the functional element 26 can directly contact the circuit layer 201. If the functional element 26 is a passive element, it can be electrically connected to the circuit layer 201 via conductive bumps 260. It should be understood that there are no particular limitations on the method by which the functional element 26 is electrically connected to the circuit layer 201.

[0092] Furthermore, the circuit structure 20 is provided with a plurality of functional elements 26, and the electronic element 21 and / or the intermediate element 22 can serve as a bridge die, so that the electronic element 21 and / or the intermediate element 22 are electrically connected to the circuit layer 201 of the circuit structure 20 via the conductors 212, 222, so as to electrically bridge the plurality of functional elements 26.

[0093] Additionally, an encapsulation layer 27 can be formed on the outermost layer of the circuit structure 20 to cover the functional element 26 and the primer 261. If the conductive bumps 260 are covered by the encapsulation layer 27, then the primer 261 is not required. For example, the encapsulation layer 27 can be an insulating material, such as polyimide (PI), dry film, epoxy resin, or an epoxy resin encapsulating compound, which can be formed by lamination or molding. It should be understood that the material of the covering layer 25 can be the same as or different from the material of the encapsulation layer 27.

[0094] Alternatively, the encapsulation layer 27 may cover the top surface of the functional element 26. Or, as required, the outer surface of the encapsulation layer 27 may be flush with the top surface of the functional element 26, so that the top surface of the functional element 26 is exposed by the encapsulation layer 27.

[0095] like Figure 2B As shown, a planarization process is performed on the first surface 25a of the covering layer 25 to remove the protective layer 28b on the intermediary element 22, while retaining the protective layer 28 on the electronic component 21, so that the conductive via 220 is exposed to the intermediary element 22, and the intermediary element 22 and its conductive via 220 are exposed to the first surface 25a of the covering layer 25. The thickness of the protective layer 28a is different from the thickness of the protective layer 28b (that is, the thickness of the electronic component 21 is different from the thickness of the intermediary element 22), wherein the thickness of the protective layer 28a on the electronic component 21 is greater than the thickness of the protective layer 28b on the intermediary element 22.

[0096] In this embodiment, a leveling process is performed to remove a portion of the material from the protective layer 28b on the intermediary element 22, the first surface 25a of the covering layer 25, the conductive pillar 23, and the protective layer 28a of the electronic component 21, so that the outer surface of the intermediary element 22, the end face of the conductive via 220, the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, and the outer surface of the protective layer 28 on the electronic component 21 are flush. For example, this leveling process employs a grinding method to thin the protective layer 28 on the electronic component 21.

[0097] It should be understood that there are many removal methods that can be used in this leveling process, and it is not limited to grinding.

[0098] like Figure 2C As shown, a plurality of conductive elements 29 electrically connected to the conductive pillar 23 and the conductive through-hole 220 are formed on the first surface 25a of the covering layer 25.

[0099] In this embodiment, the conductive element 29 is a solder ball or a metal bump such as a copper bump. For example, the conductive element 29 is a C4 type solder ball, so that the electronic package 2 is connected to an electronic device (not shown) such as a circuit board through the conductive elements 29.

[0100] Furthermore, an insulating protective layer 24 with multiple openings 240 can be formed on the first surface 25a of the covering layer 25, and the openings 240 expose the protective layer 28, conductive pillars 23 and conductive through holes 220. Then, multiple conductive blind holes (vias) 241 are formed in the openings 240 to connect the multiple conductive elements 29.

[0101] Therefore, the manufacturing method of this embodiment mainly involves providing a protective layer 28a embedded in the first surface 25a of the covering layer 25 on the non-functional surface 21b of the electronic component 21, and also providing a protective layer 28b embedded in the first surface 25a of the covering layer 25 on the intermediate element 22. This reduces the difference in materials that need to be removed during the leveling process of the first surface 25a of the covering layer 25, such as insulating materials (covering layer 25 and protective layers 28a, 28b) and copper materials (conductive materials). The conductive pillar 23 is easy to grind, so compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of uneven grinding surface, so as to form a flat grinding surface (for example, the outer surface of the intermediate element 22, the end face of the conductive through hole 220, the first surface 25a of the covering layer 25, the end face of the conductive pillar 23 and the outer surface of the protective layer 28 on the electronic component 21 are flush), which is beneficial to the subsequent alignment and bonding of the conductive element 29, thereby improving the reliability and yield of the electronic package.

[0102] Furthermore, a protective layer 28 is provided on the non-functional surface 21b of the electronic component 21, thus avoiding the existing copper migration problem. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component 21, thereby improving the reliability and yield of the electronic package 2.

[0103] In addition, the protective layer 28 can effectively improve the bonding between the electronic component 21 and the insulating protective layer 24. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component 29 and the conductive through-hole 220 (or the conductive post 23), thereby improving the reliability and yield of the electronic package 2.

[0104] Figures 3A to 3F This is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package 3 of this application. The difference between this embodiment and the first embodiment lies in the specifications of the intermediate element 32, so the similarities will not be repeated below.

[0105] like Figure 3A As shown, a general example is provided. Figure 2A The main difference of the electronic module 3a shown is that the conductive through-hole 320 of the intermediate element 32 has a small diameter, with a width R of less than 11 micrometers (um).

[0106] like Figure 3B As shown, proceed as follows Figure 2B The leveling process shown is used to remove the protective layer 28b on the intermediary element 32 so that the conductive through-hole 320 is exposed on the intermediary element 32 and the intermediary element 32 is exposed on the first surface 25a of the covering layer 25, wherein the surface of the intermediary element 32, the first surface 25a of the covering layer 25, the end face of the conductive post 23 and the outer surface of the protective layer 28 of the electronic component 21 are flush.

[0107] like Figure 3C As shown, a recess S is formed on the intermediate element 32, so that the end of the conductive through hole 320 protrudes from the bottom surface of the recess S.

[0108] In this embodiment, the recess S is formed by etching silicon material, but the method of forming the recess S is not limited to the above.

[0109] like Figure 3D As shown, a passivation structure 32a is formed in the recess S to cover the end of the conductive through hole 320, and the end face of the conductive through hole 320 is exposed in the passivation structure 32a.

[0110] In this embodiment, the passivation structure 32a includes at least one or more passivation layers 321, 322. For example, the passivation layers 321, 322 are oxide layers or nitride layers, such as silicon nitride (SiN) and / or silicon oxide (SiO2), but are not limited to the above.

[0111] Furthermore, the process of the passivation structure 32a can first form at least one passivation layer 321, 322 on the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, the protective layer 28, and the wall and bottom surfaces of the recess S, and then remove the passivation layers 321, 322 on the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, the protective layer 28, and the wall surfaces of the recess S, leaving only the passivation layers 321, 322 on the bottom surface of the recess S. For example, by a leveling process, a portion of the material of the first surface 25a of the cladding layer 25 and its passivation layers 321, 322, a portion of the material of the conductive pillar 23 and its passivation layers 321, 322, and a portion of the material of the protective layer 28 and its passivation layers 321, 322 are removed by grinding, so that the surface of the passivation structure 32a, the first surface 25a of the cladding layer 25, the end face of the conductive pillar 23 and the outer surface of the protective layer 28 on the electronic component 21 are flush, so that the passivation structure 32a and the end face of its conductive through-hole 320 are exposed on the first surface 25a of the cladding layer 25.

[0112] It should be understood that there are many ways to manufacture the passivation structure 32a, and it is not limited to the above.

[0113] like Figure 3E As shown, a wiring structure 34 is formed on the first surface 25a of the covering layer 25, so that the wiring structure 34 is electrically connected to the conductive post 23 and the conductive through-hole 320 of the intermediate element 32.

[0114] In this embodiment, the wiring structure 34 includes at least one insulating layer 340 and a wiring layer 341 disposed on the insulating layer 340 and electrically connecting the conductive post 23 and the conductive via 320. For example, in a redistribution layer (RDL) specification, the outermost insulating layer 340 can serve as a solder resist layer, and the outermost wiring layer 341 is exposed above the solder resist layer to serve as an electrical contact pad 342. Alternatively, the wiring structure 34 may also include only a single insulating layer 340 and a single wiring layer 341.

[0115] Furthermore, the wiring layer 341 is made of copper, and the insulating layer 340 is made of dielectric materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or solder resist materials such as green paint or ink.

[0116] like Figure 3F As shown, a plurality of conductive elements 29 electrically connected to the wiring layer 341 are formed on each of the electrical contact pads 342, so that the electronic package 3 is connected to an electronic device (not shown) such as a circuit board through the conductive elements 29.

[0117] In this embodiment, the conductive element 29 is a C4 type solder ball, and a bump under metal layer (UBM) 290 for bonding the conductive element 29 can be formed on the electrical contact pad 342.

[0118] Therefore, the manufacturing method of this embodiment mainly involves providing a protective layer 28a embedded in the first surface 25a of the covering layer 25 on the non-functional surface 21b of the electronic component 21, and also providing a protective layer 28b embedded in the first surface 25a of the covering layer 25 on the intermediate element 32. This minimizes the difference in materials that need to be removed during the leveling process of the first surface 25a of the covering layer 25, such as insulating materials (covering layer 25 and protective layers 28a, 28b) and copper materials (conductive pillars 23), making grinding easier. Therefore, compared to the prior art, the manufacturing method of this embodiment can effectively avoid the problem of uneven grinding surfaces, forming a flat grinding surface (for example, the outer surface of the intermediate element 32, the end face of the conductive through-hole 320, the first surface 25a of the covering layer 25, the end face of the conductive pillar 23, and the outer surface of the protective layer 28 on the electronic component 21 are flush). Figure 3B As shown in the figure, this facilitates the subsequent alignment and bonding of the wiring structure 34 and the conductive element 29, thereby improving the reliability and yield of the electronic package.

[0119] Furthermore, the non-functional surface 21b of the electronic component 21 is provided with a protective layer 28, thus avoiding the existing copper migration problem. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of electrical short circuit, so as to ensure the normal electrical function of the electronic component 21, thereby improving the reliability and yield of the electronic package 3.

[0120] In addition, the protective layer 28 can improve the bonding between the electronic component 21 and the insulating layer 340 of the wiring structure 34. Therefore, compared with the prior art, the manufacturing method of this embodiment can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the wiring layer 341 of the wiring structure 34 and the conductive via 220 (or the conductive post 23), thereby improving the reliability and yield of the electronic package 3.

[0121] This application also provides an electronic package 2,3, including: a cover layer 25, at least one electronic component 21 embedded in the cover layer 25, at least one intermediate component 22,32 embedded in the cover layer 25, and a protective layer 28 embedded in the cover layer 25.

[0122] The coating layer 25 has a first surface 25a and a second surface 25b opposite to each other.

[0123] The electronic component 21 serves as a bridging element, having an opposing active surface 21a and a non-active surface 21b, with the active surface 21a facing the second surface 25b of the covering layer 25 and having a plurality of electrode pads 210.

[0124] The aforementioned intermediate elements 22 and 32 serve as bridging elements and have at least one through conductive via 220 or 320.

[0125] The protective layer 28 is embedded in the first surface 25a of the covering layer 25 and bonded to the non-functional surface 21b of the electronic component 21, but is not provided on the intermediate element 22, 32.

[0126] In one embodiment, an insulating protective layer 24 with a plurality of openings 240 is provided on the first surface 25a of the protective layer 28 and the covering layer 25, so as to form a plurality of conductive blind holes 241 in the plurality of openings 240 for connecting a plurality of conductive elements 29.

[0127] In one embodiment, an insulating protective layer 24 with a plurality of openings 240 is provided on the first surface 25a of the intermediary element 22 and the covering layer 25, so that the plurality of openings 240 correspond to the conductive through-holes 220, and a conductive blind hole 241 electrically connected to the conductive through-holes 220 is formed in the openings 240 for connecting the conductive element 29.

[0128] In one embodiment, a wiring structure 34 is provided on the first surface 25a of the protective layer 28 and the covering layer 25.

[0129] In one embodiment, the intermediary element 32 and the first surface 25a of the covering layer 25 are provided with a wiring structure 34 electrically connected to the conductive through-hole 320.

[0130] In one embodiment, the width D of the conductive via 220 is greater than 11 micrometers.

[0131] In one embodiment, the width R of the conductive via 320 is less than 11 micrometers.

[0132] In one embodiment, a circuit structure 20 electrically connecting the electrode pad 210 is provided on the second surface 25b of the covering layer 25 and the working surface 21a of the electronic component 21. For example, a plurality of functional elements 26 are provided on the circuit structure 20 so that the electronic component 21 and / or the intermediate elements 22, 32 are electrically bridged to the plurality of functional elements 26 through the circuit structure 20.

[0133] In one embodiment, a passivation structure 32a is formed on the intermediate element 32 to cover the end of the conductive through-hole 320, and the end face of the conductive through-hole 320 is exposed in the passivation structure 32a.

[0134] In summary, the electronic package of this application has a protective layer (with different thicknesses) embedded in the first surface of the coating layer on both the non-functional surface of the electronic component and the intermediate component. This reduces the difference in material to be removed during the leveling process of the first surface of the coating layer. Therefore, this application can effectively avoid the problem of uneven grinding surface and form a flat grinding surface, which is beneficial to the subsequent alignment and bonding of the conductive component, thereby improving the reliability and yield of the electronic package.

[0135] Furthermore, the non-functional surface of the electronic component is provided with a protective layer, thus avoiding the existing copper migration problem. Therefore, this application can effectively avoid the problem of electrical short circuit, ensuring the normal electrical function of the electronic component, thereby improving the reliability and yield of the electronic package.

[0136] In addition, the protective layer can improve the bonding between the electronic component and the insulating protective layer. Therefore, this application can effectively avoid the problem of delamination, so as to ensure normal electrical conduction between the conductive component and the conductive via, thereby improving the reliability and yield of the electronic package.

[0137] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.

Claims

1. An electronic package, characterized by The application relates to a semiconductor device, comprising: a cladding layer having opposite first and second surfaces; an electronic element embedded in the cladding layer as a bridging element and having opposite active and non-active surfaces, the active surface facing the second surface of the cladding layer; an intermediate element embedded in the cladding layer as a bridging element and having a plurality of conductive perforations; and a protective layer embedded in the first surface of the cladding layer and bonded to the non-active surface of the electronic element, and not disposed on the intermediate element.

2. The electronic package of claim 1, wherein, The protective layer and the first surface of the cladding layer are provided with an insulating protective layer having a plurality of openings, and a plurality of conductive blind holes are formed in the plurality of openings for accommodating a plurality of conductive elements.

3. The electronic package of claim 1, wherein, The intermediate element and the first surface of the cladding layer are provided with an insulating protective layer having a plurality of openings, the plurality of openings correspond to the plurality of conductive perforations, and a conductive blind hole electrically connected to the conductive perforation is formed in each of the openings for accommodating a conductive element.

4. The electronic package of claim 1, wherein, The protective layer and the first surface of the cladding layer are provided with a wiring structure.

5. The electronic package of claim 1, wherein, The intermediate element and the first surface of the cladding layer are provided with a wiring structure electrically connected to the plurality of conductive perforations.

6. The electronic package of claim 1, wherein, The width of the conductive perforation is greater than 11 microns.

7. The electronic package of claim 1, wherein, The width of the conductive perforation is less than 11 microns.

8. The electronic package of claim 1, wherein, The second surface of the cladding layer and the active surface of the electronic element are provided with a circuit structure electrically connected to the electronic element.

9. The electronic package of claim 8, wherein, A plurality of functional elements are arranged on the circuit structure, so that the electronic element and / or the intermediate element electrically bridge the plurality of functional elements through the circuit structure.

10. The electronic package of claim 1, wherein, The intermediate element is provided with a passivation structure covering the end of the plurality of conductive perforations, and the end surface of the plurality of conductive perforations is exposed to the passivation structure.

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