Analog-to-digital conversion circuit, circuit system and electronic equipment
By employing a non-binary arranged capacitor array and a weighted conversion adder module in the SAR ADC, the power drive and rate limitation problems caused by excessively large capacitor values in high-bit SAR ADCs are solved, and an efficient analog-to-digital conversion circuit design is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-03-17
AI Technical Summary
In high-bit SAR ADCs, excessively large capacitor values lead to high power supply drive requirements and limited operating speed, affecting the performance of the analog-to-digital conversion circuit.
A non-binary capacitor array is used, which splits the highest-order capacitor into multiple small-value capacitors and performs potential switching during the quantization comparison stage. Combined with a weighted conversion addition module and a register module, efficient digital signal conversion is achieved.
It reduces power drive requirements, improves operating speed and system fault tolerance, reduces capacitor array area and power consumption, and improves sampling linearity.
Smart Images
Figure CN224006704U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of digital circuits, and particularly to an analog-to-digital conversion circuit, a circuit system and an electronic device. Background Technique
[0002] In a traditional SAR ADC (Successive Approximation Register Analog-to-Digital Converter), the capacitance values of capacitors in a binary-weighted CDAC (Capacitive Digital-to-Analog Converter) increase exponentially with the increase in the number of bits. For example, in a 10-bit SAR ADC, the highest-bit capacitor in the CDAC is equivalent to 9 2 unit capacitors. This results in a very large capacitance value for the highest-bit capacitor in a high-bit SAR ADC.
[0003] However, an overly large capacitance value not only requires extremely high power supply driving capabilities, thereby increasing circuit power consumption, but also greatly prolongs the time for switching the potential of the highest-bit capacitor, thus limiting the operating speed of the SAR ADC. Content of the Utility Model
[0004] Embodiments of the utility model provide an analog-to-digital conversion circuit, a circuit system and an electronic device to solve the power supply driving problem and the operating speed problem existing in high-bit analog-to-digital conversion circuits.
[0005] To solve the above technical problems, the technical solution of the utility model provides an analog-to-digital conversion circuit. The number of bits of the analog-to-digital conversion circuit is N, and the analog-to-digital conversion circuit is used to convert an externally input signal into an N-bit digital signal. The analog-to-digital conversion circuit includes:
[0006] A capacitor array for:
[0007] Sampling the externally input signal according to a group of sampling signals;
[0008] Switching the potentials of each capacitor according to a group of quantization control signals and outputting corresponding quantization voltages. The capacitor array includes N + M capacitors, and the total capacitance value of the N + M capacitors is equal to the total capacitance value of N capacitors distributed in binary starting from 1. The ratio between M and N is less than or equal to a set threshold. The highest-bit capacitance value among the N + M capacitors is less than the sum of the capacitance values of 2N unit capacitors. The unit capacitor is used to represent the capacitance value of the first capacitor. The set threshold and the highest-bit capacitance value among the N + M capacitors are jointly used to make the operating speed of the analog-to-digital conversion circuit meet a preset operating speed. Both N and M are positive integers, 1 < M < N, and N ≥ 10;
[0009] The comparison module has its non-inverting input terminal coupled to the output terminal of the capacitor array and its inverting input terminal connected to the reference voltage. The comparison module is used to perform N+M comparisons between the quantized voltage and the reference voltage, and output the corresponding comparison result signal according to the comparison result of each comparison. The quantized voltage corresponding to each comparison is controlled by the quantization control signal group.
[0010] The capacitor potential switching module is used to output the corresponding quantization control signal group according to the comparison result signal each time;
[0011] The weight conversion addition module is used to perform weight conversion addition operations on N+M comparison result signals and output the N-bit digital signal.
[0012] The register module is used to store the N-bit digital signal and output it synchronously.
[0013] Optionally, the capacitor array further includes N+M potential switching switches, each of which corresponds to one of the N+M capacitors. The first end of each potential switching switch is connected to the lower plate of the corresponding capacitor, and the second, third, and fourth ends of each potential switching switch are connected to the external input signal, the power supply voltage, and the ground voltage, respectively. The upper plate of each capacitor is connected to the non-inverting input of the comparator module.
[0014] A common-mode voltage sampling switch, wherein the first terminal of the common-mode voltage sampling switch is connected to the non-inverting input terminal of the comparator module and the upper plate of all capacitors respectively, and the second terminal of the common-mode voltage sampling switch is connected to the reference voltage;
[0015] The sampling signal group includes a first sampling signal and a second sampling signal. The first sampling signal is used to control the first terminal of all the potential switching switches to be connected to their own second terminal during the sampling phase. The second sampling signal is used to control the common-mode voltage sampling switch to be turned on during the sampling phase.
[0016] The quantization control signal group includes N+M first quantization control signals and N+M second quantization control signals. The first quantization control signals and the second quantization control signals communicate to control the first terminal of the corresponding potential switching switch to connect to its own third or fourth terminal during the quantization comparison stage.
[0017] Optionally, the potential switching switch is specifically a single-pole triple-throw switch. The first terminal of the single-pole triple-throw switch corresponds to the first terminal of the potential switching switch, the first output terminal of the single-pole triple-throw switch corresponds to the second terminal of the potential switching switch, the second output terminal of the single-pole triple-throw switch corresponds to the third terminal of the potential switching switch, and the third output terminal of the single-pole triple-throw switch corresponds to the fourth terminal of the potential switching switch. The control terminal of the single-pole triple-throw switch is connected to the first sampling signal during the sampling phase and to the corresponding quantization control signal during the quantization comparison phase.
[0018] Optionally, the common-mode voltage sampling switch includes a first NMOS transistor, the drain of the first NMOS transistor serves as the first terminal of the common-mode voltage sampling switch, the source of the first NMOS transistor serves as the second terminal of the common-mode voltage sampling switch, and the gate of the first NMOS transistor is connected to the second sampling signal.
[0019] Optional, N equals 12, M equals 2, and the capacitance of the eleventh capacitor is equal to 2. 9 The capacitance value of the twelfth capacitor is equal to 2. 9 The capacitance of the thirteenth capacitor is equal to 2. 10 The capacitance value of the fourteenth capacitor is equal to 2. 10 The capacitance value of a unit capacitor.
[0020] Optional, N equals 12, M equals 1, and the capacitance of the eleventh capacitor is 2. 10 The capacitance value of the twelfth capacitor is equal to 2. 10 The capacitance of the thirteenth capacitor is equal to 2. 10 The capacitance value of a unit capacitor.
[0021] Optionally, the weight transformation addition module includes a weight transformation adder.
[0022] Optionally, the reference voltage generation circuit includes: a first resistor, a second resistor, and an operational amplifier. The first end of the first resistor is connected to the power supply voltage. The second end of the first resistor is connected to the non-inverting input of the operational amplifier and the first end of the second resistor, respectively. The second end of the second resistor is connected to ground. The output of the operational amplifier is connected to its own inverting input. The output of the operational amplifier outputs the reference voltage.
[0023] The present invention also provides a circuit system, including the analog-to-digital conversion circuit.
[0024] The present invention also provides an electronic device, including the aforementioned circuit system.
[0025] Compared with the prior art, the technical solution provided by this utility model has the following beneficial effects:
[0026] The analog-to-digital converter (ADC) circuit provided by this invention uses a capacitor array to switch the potential of each capacitor and output the corresponding quantization voltage according to the quantization control signal group during the quantization comparison stage. N+M capacitors are arranged in a non-binary configuration, with the total capacitance of the N+M capacitors equal to the total capacitance of the N capacitors arranged in a binary configuration. The ratio between M and N is less than or equal to a set threshold, and the maximum capacitance among the N+M capacitors is less than the capacitance of 2N unit capacitors. The set threshold and the highest-order capacitance among the N+M capacitors are used together to ensure that the operating speed of the ADC circuit meets a preset operating speed. Because this invention rationally splits the highest-order capacitor among the N capacitors arranged in a binary configuration, it not only avoids the operating speed of the ADC circuit in the quantization comparison stage being limited by the excessively large capacitance of the highest-order capacitor, but also avoids the operating speed being limited by the excessive number of capacitors split, and reduces the driving requirements of the power supply voltage. Simultaneously, the additional M capacitors also improve the fault tolerance of the circuit in the quantization comparison stage.
[0027] Furthermore, this invention employs a single-ended input capacitor array, saving half the number of capacitors, thereby significantly reducing the layout area and power consumption of the capacitor array. Simultaneously, this invention also enables the N+M capacitors to sample external input signals from the lower plate, thereby improving the linearity of the sampling. Attached Figure Description
[0028] Figure 1 A module structure diagram of the analog-to-digital conversion circuit provided in this embodiment of the utility model;
[0029] Figure 2 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 1 ;
[0030] Figure 3 Waveforms of various parameters of the analog-to-digital conversion circuit provided in this embodiment of the present invention during the sampling stage;
[0031] Figure 4 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 2 ;
[0032] Figure 5 A schematic diagram of the circuit structure of the reference voltage generation circuit provided in the embodiment of this utility model;
[0033] Figure 6 A waveform diagram of the quantization voltage during the quantization comparison stage provided in an embodiment of this utility model;
[0034] Figure 7 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 3 ;
[0035] Figure 8 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 4 ;
[0036] Figure 9 A schematic diagram of the circuit structure of the potential switching circuit provided in the embodiment of this utility model. Detailed Implementation
[0037] As described in the background section, when the number of bits in a SAR ADC is too large, such as 10 bits or more, the SAR ADC will greatly increase the power supply drive capability requirements and greatly prolong the switching potential time of the highest bit capacitor due to the excessive capacitance value of the internal high-bit capacitor.
[0038] In view of this, the present invention provides an analog-to-digital converter circuit, wherein the number of bits in the analog-to-digital converter circuit is N, and the analog-to-digital converter circuit is used to convert an external input signal into an N-bit digital signal.
[0039] Figure 1 A module structure diagram of the analog-to-digital conversion circuit provided in this embodiment of the utility model.
[0040] Please refer to Figure 1 The analog-to-digital conversion circuit includes:
[0041] Capacitor array 10, used for:
[0042] The external input signal VIN is sampled according to the sampling signal group v1{..};
[0043] The potential of each capacitor is switched according to the quantization control signal group v2{..} and the corresponding quantization voltage Vp is output. The capacitor array 10 includes N+M capacitors. The total capacitance of the N+M capacitors is equal to the total capacitance of the N capacitors distributed in binary order starting from 1. The ratio between M and N is less than or equal to a set threshold. The highest bit capacitance of the N+M capacitors is less than the sum of the capacitance values of 2N unit capacitors. The unit capacitor is used to characterize the capacitance value of the first capacitor. The set threshold and the highest bit capacitance of the N+M capacitors are used together to make the operating rate of the analog-to-digital conversion circuit meet the preset operating rate. N and M are both positive integers, 1≤M<N, and N≥10.
[0044] The comparison module 20 has its non-inverting input terminal coupled to the output terminal of the capacitor array 10 and its inverting input terminal connected to the reference voltage Vcm. The comparison module 20 is used to perform N+M comparisons between the quantization voltage Vp and the reference voltage Vcm, and output the corresponding comparison result signal according to the comparison result of each comparison.
[0045] The capacitor potential switching module 30 is used to output the corresponding quantization control signal group v2{..} according to the comparison result signal each time;
[0046] The weight conversion addition module 40 is used to perform weight conversion addition operations on N+M comparison result signals and output the N-bit digital signal VN.
[0047] The register module 50 is used to store the N-bit digital signal VN and output it synchronously.
[0048] In a SARADC, the larger the capacitance value of the capacitors in capacitor array 10, the longer the potential switching time is required during the quantization and comparison phase, thus prolonging the quantization and comparison phase. When the SARADC has a large number of bits, for example, 10 bits, the capacitance value of the most significant bit capacitor in capacitor array 10 is 2. 9 Because the highest-order capacitor has a very long switching time for a safe potential, the quantization comparison phase is significantly prolonged, severely limiting the operating speed of the SAR ADC. This embodiment of the invention redundantly splits the highest-order capacitor, dividing the original large capacitor into several smaller capacitors while maintaining the total capacitance. This avoids the severe limitation on the SAR ADC's operating speed caused by the excessively large capacitance of the highest-order capacitor, allowing the high-bit SAR ADC to meet the preset operating speed while ensuring complete potential switching of each capacitor. Simultaneously, the redundant capacitors also improve the system fault tolerance of the SAR ADC. Of course, besides splitting the highest-order capacitor, the second-highest-order capacitor or other bit capacitors can also be split according to the bit size of the SAR ADC; this is not limited here.
[0049] For example, when the SAR ADC has 12 bits, the original 12th-bit capacitor is split into two capacitors of equal capacitance, that is, the original 2048-unit capacitor of the 12th bit is split into a 13th-bit capacitor and a 14th-bit capacitor of equal capacitance, with the capacitance of the 13th-bit and 14th-bit capacitors both being 1024 units. Similarly, the original 11th-bit capacitor is split into two capacitors of equal capacitance, that is, the original 1024-unit capacitor of the 11th bit is split into an 11th-bit capacitor and a 12th-bit capacitor of equal capacitance, with the capacitance of the 11th-bit capacitor and the 12th-bit capacitor both being 512 units. The capacitance of the remaining bits remains unchanged. Therefore, the original binary 12-bit capacitor array 10 is split into a non-binary 14-bit capacitor array 10, i.e., M equals 2. After the comparison module 20 completes 14 comparisons, the comparison result of each comparison is weighted and added by the weight conversion addition module 40 to convert the 14-bit output of the comparison module 20 into a 12-bit output. Finally, the 12-bit output is stored and output by the register module 50.
[0050] It should be noted that splitting an additional capacitor increases the number of comparisons performed by the comparison module 20, thus increasing the overall time of the quantization comparison phase. Splitting the high-value capacitors can reduce the time spent on potential switching during quantization comparison, thereby reducing the overall time of the quantization comparison phase. Therefore, a trade-off needs to be made between the number and size of the high-value capacitors to ensure that the analog-to-digital converter (ADC) operates at the preset operating rate. Specifically: if a complete potential switch of the original highest-value capacitor would cause the SAR ADC to fail to meet the preset operating rate, then the original highest-value capacitor is split in half. If a complete potential switch of the split highest-value capacitor still causes the SAR ADC to fail to meet the preset operating rate, then the current highest-value capacitor is split in half to ensure that the SAR ADC meets the preset operating rate. Of course, the splitting of the capacitor can be set according to the actual situation. For example, if the SAR ADC has 12 bits, in addition to splitting the original 12th-bit capacitor and the original 11th-bit capacitor in half, the original 12th-bit capacitor can also be split in half, and the original 11th-bit capacitor can be split into 256 unit capacitors and 768 unit capacitors, or the original 12th-bit capacitor can be split into 256 unit capacitors, 768 unit capacitors, and 1024 unit capacitors without splitting the original 11th-bit capacitor. Therefore, as long as the operating rate of the SAR ADC meets the preset operating rate, there is no limitation on the number of bits, the number of splits, or the size of the split capacitor.
[0051] To make the above-mentioned objectives, features, and beneficial effects of this utility model more apparent and understandable, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0052] Figure 2 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 1 . Figure 3 The waveform diagrams of various parameters of the analog-to-digital conversion circuit provided in this embodiment of the present invention during the sampling stage.
[0053] Please refer to Figure 2 In one specific embodiment, the capacitor array 10 further includes N+M potential switching switches SW1, which correspond one-to-one with the N+M capacitors C. The first end of the potential switching switch SW1 is connected to the lower plate of the corresponding capacitor C. The second, third and fourth ends of the potential switching switch SW1 are connected to the external input signal VIN, the power supply voltage VDD and the ground voltage VSS, respectively. The upper plate of the capacitor C is connected to the non-inverting input of the comparator module 20.
[0054] A common-mode voltage sampling switch SW2, the first terminal of which is connected to the non-inverting input terminal of the comparator module 20 and the upper plate of all capacitors C, and the second terminal of which is connected to the reference voltage Vcm;
[0055] The sampling signal group v1{..} includes a first sampling signal v1{1} and a second sampling signal v1{2}. The first sampling signal v1{1} is used to control the first terminal of all the potential switching switches SW1 to be connected to their own second terminal during the sampling phase. The second sampling signal v1{2} is used to control the common-mode voltage sampling switch SW2 to be turned on during the sampling phase.
[0056] The quantization control signal group v2{..} includes N+M first quantization control signals v2{1} and N+M second quantization control signals v2{2}. The first quantization control signals v2{1} and the second quantization control signals v2{2} communicate to control the first terminal of the corresponding potential switching switch SW1 to connect to its own third or fourth terminal during the quantization comparison stage.
[0057] Please refer to Figure 2 and Figure 3 The specific working process of the capacitor array 10 is as follows:
[0058] At the first moment t1 of the sampling phase, the first sampling signal v1{1} transitions from low to high, causing the first terminals of all the potential switching switches SW1 to connect to their second terminals, thereby connecting the external input signal VIN to the lower plates of all capacitors C. The second sampling signal v1{2} also transitions from low to high, turning on the common-mode voltage sampling switch SW2, thereby connecting the reference voltage Vcm to both the upper plate of the capacitor C and the non-inverting input of the comparison module 20.
[0059] At the second moment t2 of the sampling phase, the second sampling signal v1{2} transitions from a high level to a low level to turn off the common-mode voltage sampling switch SW2. Due to the law of conservation of charge, the voltage difference between the upper and lower plates of all capacitors C is fixed, thereby completing the sampling of the external input signal VIN.
[0060] At the third moment t3 of the sampling phase, the first sampling signal v1{1} also jumps from high level to low level to disconnect the connection between the first terminal of the potential switching switch SW1 and its own second terminal, thereby ending the sampling phase.
[0061] During the quantization comparison phase, the first quantization control signal v2{1} and the second quantization control signal v2{2} in the quantization control signal group v2{..} control the first terminal of the corresponding potential switching switch SW1 to connect to its third or fourth terminal. Since the third terminal of the potential switching switch SW1 is connected to the power supply voltage VDD, and the fourth terminal of the potential switching switch SW1 is connected to the ground voltage VSS, the first quantization control signal v2{1} and the second quantization control signal v2{2} are used together to control the lower plate of the corresponding capacitor C to switch between the power supply voltage VDD and the ground voltage VSS. The specific switching principle will be explained in detail below and will not be repeated here.
[0062] Since this embodiment uses a single-input capacitor array 10 and samples the external input signal VIN through the lower plate of capacitor C, it effectively suppresses the nonlinearity of external input signal VIN sampling caused by charge injection while reducing the power consumption of capacitor array 10 and the circuit layout area, thereby improving the accuracy of external input signal VIN sampling.
[0063] Please refer to Figure 2 Specifically: the potential switching switch SW1 includes a single-pole triple-throw switch, the first terminal of the single-pole triple-throw switch corresponds to the first terminal of the potential switching switch SW1, the first output terminal of the single-pole triple-throw switch corresponds to the second terminal of the potential switching switch SW1, the second output terminal of the single-pole triple-throw switch corresponds to the third terminal of the potential switching switch SW1, the third output terminal of the single-pole triple-throw switch corresponds to the fourth terminal of the potential switching switch SW1, the control terminal of the single-pole triple-throw switch is connected to the first sampling signal v1{1} during the sampling stage, and the control terminal of the single-pole triple-throw switch is connected to the corresponding quantization control signal during the quantization comparison stage.
[0064] Figure 4 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 2 .
[0065] Please refer to Figure 4 Specifically: the common-mode voltage sampling switch SW2 includes a first NMOS transistor MN1, the drain of the first NMOS transistor MN1 serves as the first terminal of the common-mode voltage sampling switch SW2, the source of the first NMOS transistor MN1 serves as the second terminal of the common-mode voltage sampling switch SW2, and the gate of the first NMOS transistor MN1 is connected to the second sampling signal v1{2}.
[0066] The single-pole three-throw switch specifically includes a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The gate of the second NMOS transistor MN2 is connected to the first sampling signal v1{1}, the gate of the third NMOS transistor MN3 is connected to the first quantization control signal v2{1}, and the gate of the fourth NMOS transistor MN4 is connected to the second quantization control signal v2{2}. The sources of the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all connected to the lower plate of the corresponding capacitor C. The drain of the second NMOS transistor MN2 is connected to the external input signal VIN, the drain of the third NMOS transistor MN3 is connected to the power supply voltage VDD, and the drain of the fourth NMOS transistor MN4 is connected to the ground voltage VSS.
[0067] certainly, Figure 4 The circuit structure shown is only one specific implementation of the single-pole three-throw switch and the common-mode voltage sampling switch. Other circuit structures with the same function are also within the protection scope of this utility model and are not limited here.
[0068] Figure 5 A schematic diagram of the circuit structure of the reference voltage generation circuit provided in the embodiment of this utility model.
[0069] Please refer to Figure 5 In one specific implementation, the reference voltage Vcm generation circuit includes: a first resistor R1, a second resistor R2, and an operational amplifier AMP. The first end of the first resistor R1 is connected to the power supply voltage VDD. The second end of the first resistor R1 is connected to the non-inverting input terminal of the operational amplifier AMP and the first end of the second resistor R2. The second end of the second resistor R2 is connected to ground. The output terminal of the operational amplifier AMP is connected to its own inverting input terminal. The output terminal of the operational amplifier AMP outputs the reference voltage Vcm.
[0070] Of course, besides Figure 5 Other circuit structures capable of generating the reference voltage, besides the circuit structure shown, are all within the protection scope of this utility model and are not limited here.
[0071] In one specific implementation, the comparison module 20 is a comparator, with its non-inverting input and its inverting input serving as the inverting input of the comparator. When the quantization voltage Vp is greater than the reference voltage Vcm, the comparator outputs a high level. When the quantization voltage Vp is less than the reference voltage Vcm, the comparator outputs a low level.
[0072] As one specific implementation, the internal structure of the capacitor potential switching module is determined by the potential switching strategy of each capacitor in the capacitor array. The potential switching strategies of each capacitor in the capacitor array typically include: traditional CDAC switching strategy, monotonic switching strategy, Sanyal switching strategy, and Vcm-Based switching strategy, etc. Constructing the corresponding capacitor potential switching module according to the corresponding switching strategy is a conventional technical means for those skilled in the art. Therefore, the specific structure of the capacitor potential switching module will not be described in detail.
[0073] In one specific implementation, the control timing of the capacitor potential switching module, the comparison module, and the capacitor array adopts synchronous timing logic. Since the synchronous timing logic is a common technique in this field, it will not be described in detail here.
[0074] In one specific implementation, the weight conversion addition module is composed of several full adders. The number of full adders is determined by the method of splitting the high-order capacitors.
[0075] For example, if the digital signal output by the analog-to-digital converter circuit is 12 bits, then the capacitor array includes 12 capacitors distributed in binary. To avoid the highest and second-highest bit capacitors affecting the operating speed of the analog-to-digital converter circuit in the quantization comparison stage, this embodiment of the invention splits the original 12th bit capacitor into two capacitors with a capacitance of 210 units each, and splits the original 11th bit capacitor into two capacitors with a capacitance of 29 units each. Therefore, the current number of bits in the capacitor array is 14, and the capacitance values of the 10th, 11th, and 12th bit capacitors are the same, as are the capacitance values of the 13th and 14th bit capacitors. In this embodiment, the weight conversion addition module consists of 5 full adders, and its working principle is as follows:
[0076] The first full adder adds the 10-bit digital signal output from the first 10-bit capacitor comparison and the digital signal output from the 11th-bit capacitor comparison, and outputs the first local result and the first carry result.
[0077] The second full adder adds the first carry result and the digital signal output from the comparison of the 13th bit capacitor, and outputs the second local result and the second carry result.
[0078] The third full adder adds the first local result and the digital signal output from the comparison of the 12th bit capacitor, and outputs the third local result and the third carry result.
[0079] The fourth full adder adds the second local result, the digital signal output from the 14th-bit capacitor comparison, and the third carry result, and outputs the fourth local result and the fourth carry result.
[0080] The fifth full adder adds the second carry result and the fourth carry result, and outputs the fifth base result.
[0081] Therefore, the final output of the weight conversion addition module consists of a 12-bit digital signal composed of the fifth-bit result, the fourth-bit result, the third-bit result, and the 9-bit digital signal output from the comparison of the first 9 bits of capacitors.
[0082] Since the method and number of original high-order capacitors are not fixed, the number of full adders in the weight conversion addition module and the specific addition principle also vary adaptively and are not limited here.
[0083] The following is Figure 2 Combination Figure 4 Taking the circuit structure shown as an example, the working process of the analog-to-digital conversion circuit provided in this embodiment of the present invention will be described in detail:
[0084] During the sampling phase: the operation of the analog-to-digital conversion circuit is the same as that of the capacitor array 10 described above, and will not be repeated here.
[0085] In the quantitative comparison phase:
[0086] During the first quantization comparison, the capacitor potential switching module 30 first sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest-order capacitor C to high and low levels, respectively, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the capacitors below the highest-order capacitor C to low and high levels, respectively, so that the lower plate of the highest-order capacitor C is connected to the power supply voltage VDD, and the lower plates of the capacitors below the highest-order capacitor C are all grounded to the ground voltage VSS. The upper plates of all capacitors C in the capacitor array 10 jointly output the first quantization voltage Vp. The comparison module 20 compares the first quantization voltage Vp with the reference voltage Vcm. If the first quantization voltage Vp is greater than the reference voltage Vcm, the comparison module 20 outputs a high level, and the capacitor potential switching module 30 controls the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest-order capacitor C to low and high levels, respectively, so that the lower plate of the highest-order capacitor C is connected to the ground voltage VSS. If the first quantization voltage Vp is less than the reference voltage Vcm, the comparison module 20 outputs a low level, and the capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest-order capacitor C unchanged according to the low level, so as to keep the lower plate of the highest-order capacitor C connected to the power supply voltage VDD.
[0087] During the second quantization comparison, the capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the highest-order capacitor C unchanged, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second-highest-order capacitor C to be high level and low level respectively, and sets the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the capacitors below the second-highest-order capacitor C to be low level and high level respectively, so that the lower plate of the second-highest-order capacitor C is connected to the power supply voltage VDD, and the lower plates of the capacitors below the second-highest-order capacitor C are all grounded to the ground terminal voltage VSS, and the upper plates of all capacitors C in the capacitor array 10 jointly output the second quantization voltage Vp. The comparison module 20 compares the second quantized voltage Vp with the reference voltage Vcm. If the second quantized voltage Vp is greater than the reference voltage Vcm, the comparison module 20 outputs a high level. The capacitor potential switching module 30 controls the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second-highest capacitor C to be at low and high levels respectively, so that the lower plate of the second-highest capacitor C is connected to the ground voltage VSS. If the second quantized voltage Vp is less than the reference voltage Vcm, the comparison module 20 outputs a low level. The capacitor potential switching module 30 keeps the first quantization control signal v2{1} and the second quantization control signal v2{2} corresponding to the second-highest capacitor C unchanged, so that the lower plate of the second-highest capacitor C is connected to the power supply voltage VDD.
[0088] The quantization comparison process for the remaining bits is the same as the process described above, and will not be repeated here.
[0089] After completing the comparison of all bits, the weight conversion addition module 40 adds the comparison result signals output by the comparison module 20 for each comparison according to the weight size, so as to output the digital signal of the corresponding number of bits.
[0090] The register module 50 stores and outputs the digital signal output by the weight conversion addition module 40.
[0091] It should be added that the formula for the change in quantization voltage Vp during each quantization comparison is as follows:
[0092]
[0093] Where, ΔV I The quantization voltage is used to characterize the change in the quantization voltage during the first quantization comparison. CdacI is used to characterize the capacitance value of the first capacitor, Ctot is used to characterize the sum of the capacitance values of all capacitors, and VDD is used to characterize the power supply voltage. I is a positive integer, and 1≤I≤N+M.
[0094] Figure 6 The waveform of the quantization voltage during the quantization comparison stage is provided for an embodiment of this utility model.
[0095] Please refer to Figure 6 Taking N+M as 14 as an example, Figure 6 The waveform of the quantized voltage Vp output by the capacitor array 10 is shown as it continuously approaches the reference voltage Vcm during 14 quantization comparisons. Figure 6 The vertical axis of the waveform graph shown represents voltage in volts, and the horizontal axis represents time in microseconds.
[0096] Since the quantization comparison stage in the above workflow requires resetting the voltage of the capacitor corresponding to the number of bits before each quantization comparison, thereby increasing the logic complexity and circuit power consumption, in another embodiment, the workflow of the analog-to-digital conversion circuit in the quantization comparison stage is as follows:
[0097] After sampling the external input signal, this embodiment of the invention first sets the lower plates of all capacitors to a comparison reference voltage, so that the upper plates of all capacitors in the capacitor array jointly output a first quantized voltage. Then, the comparison module compares the first quantized voltage with the reference voltage. If the first quantized voltage is greater than the reference voltage, the comparison module outputs a high level, and the capacitor potential switching module controls the lower plate of the highest-order capacitor to switch from the comparison reference voltage to the ground voltage based on the high level. If the first quantized voltage is less than the reference voltage, the comparison module outputs a low level, and the capacitor potential switching module controls the lower plate of the highest-order capacitor to switch from the comparison reference voltage to the power supply voltage based on the low level.
[0098] During the second quantization comparison process, the upper plates of all capacitors in the capacitor array collectively output a second quantization voltage based on the potential voltage of their lower plates from the previous comparison process. Then, the comparison module compares the second quantization voltage with the reference voltage. If the second quantization voltage is greater than the reference voltage, the comparison module outputs a high level, and the capacitor potential switching module controls the lower plate of the second-highest capacitor to switch from the comparison reference voltage to the ground voltage based on the high level. If the second quantization voltage is less than the reference voltage, the comparison module outputs a low level, and the capacitor potential switching module controls the lower plate of the second-highest capacitor to switch from the comparison reference voltage to the power supply voltage based on the low level.
[0099] The quantization comparison process for the remaining bits is the same as the process described above, and will not be repeated here.
[0100] After completing the comparison of all bits, the weight conversion addition module adds the comparison result signals output by the comparison module for each comparison according to the weight size, so as to output the digital signal of the corresponding number of bits.
[0101] The register module stores and outputs the digital signal output by the weight conversion and addition module.
[0102] It should be added that the formula for the change in quantization voltage during each quantization comparison is as follows:
[0103]
[0104] Where, ΔV I The quantization voltage Vp is used to characterize the change in the quantization voltage during the first quantization comparison. CdacI is used to characterize the capacitance value of the first capacitor C. Ctot is used to characterize the sum of the capacitance values of all capacitors C. VREF is used to characterize the comparison reference voltage. I is a positive integer, and 1≤I≤N+M.
[0105] Figure 7 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 3 .
[0106] Please refer to Figure 7 In another embodiment, the single-pole triple-throw switch in the potential switching switch SW1 can be replaced with a single-pole double-throw switch, and the corresponding quantization control signal group v2{..} is replaced with N+M third quantization control signals v2{3} and N+M fourth quantization control signals v2{4}. The first terminal of the single-pole double-throw switch is connected to the lower plate of the corresponding capacitor C, the second terminal of the single-pole double-throw switch is connected to the external input signal VIN, and the third terminal of the single-pole double-throw switch is connected to the power supply voltage VDD or the ground voltage VSS. The third quantization control signal v2{3} is used to control the first terminal of the single-pole double-throw switch to connect to its own third terminal during the quantization comparison stage.
[0107] Figure 8 Schematic diagram of the circuit structure of the capacitor array provided in the embodiment of this utility model Figure 4 .
[0108] Please refer to Figure 8The single-pole double-throw switch specifically includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The gate of the fifth NMOS transistor MN5 is connected to the first sampling signal v1{1}, the drain of the fifth NMOS transistor MN5 is connected to the external input signal VIN, the gate of the sixth NMOS transistor MN6 is connected to the third quantization control signal v2{3}, and the drain of the sixth NMOS transistor MN6 is connected to the power supply voltage VDD or the ground voltage VSS. The sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both connected to the lower plate of the corresponding capacitor C. The third quantization control signal v2{3} is high during the quantization comparison phase.
[0109] certainly, Figure 8 The circuit structure shown is only one specific implementation of the single-pole double-throw switch. Other circuit structures with the same function are also within the protection scope of this utility model and are not limited here.
[0110] In this embodiment, the potential switching circuit corresponding to the drain of the sixth NMOS transistor MN6 is as follows: Figure 9 As shown, the switching circuit includes a first PMOS transistor MP1 and a seventh NMOS transistor MN7. The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD. The drain of the first PMOS transistor MP1 is connected to the drain of the seventh NMOS transistor MN7 and the drain of the sixth NMOS transistor MN6. The source of the seventh NMOS transistor MN7 is connected to the ground voltage VSS. The gates of the first PMOS transistor MP1 and the seventh NMOS transistor MN7 are both connected to the corresponding fourth quantization control signal v2{4}. Each fourth quantization control signal v2{4} is controlled to be high or low by the capacitor potential switching module 30. The level switching method of each fourth quantization control signal v2{4} is the same as the method of controlling whether the lower plate of each capacitor C is connected to the power supply voltage VDD or the ground voltage VSS in the previous embodiment, and will not be described again here.
[0111] Since the structure and working principle of the comparison module, the capacitor potential switching module, the weight conversion addition module and the register module are the same as those in the previous embodiment, they will not be described again here.
[0112] In summary, the analog-to-digital converter circuit provided in this embodiment of the invention redundantly splits the highest-order capacitor, dividing the original large capacitor into several smaller-value capacitors while maintaining the total capacitance value. This avoids severely limiting the operating speed of the SAR ADC due to the excessively large capacitance value of the highest-order capacitor, thus enabling the high-bit SAR ADC to meet the preset operating speed while allowing complete potential switching among all capacitors. Simultaneously, the redundant capacitors also improve the system fault tolerance of the SAR ADC. Of course, besides splitting the highest-order capacitor, the second-highest-order capacitor or other bit capacitors can also be split according to the bit size of the SAR ADC; this is not limited here.
[0113] Furthermore, this embodiment of the invention employs a single-ended input capacitor array, saving half the number of capacitors, thereby significantly reducing the layout area and power consumption of the capacitor array. Simultaneously, this invention also enables the N+M capacitors to sample external input signals from the lower plate, thereby improving the linearity of the sampling.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.
Claims
1. An analog-to-digital conversion circuit, characterized by The bit number of the analog-to-digital conversion circuit is N, the analog-to-digital conversion circuit is used for converting an external input signal into a digital signal of N bits, and the analog-to-digital conversion circuit comprises: a capacitor array, configured to: sample the external input signal according to a sampling signal group; switch the potential of each capacitor according to a quantization control signal group and output a corresponding quantization voltage, the capacitor array comprising N+M capacitors, the total capacitance of the N+M capacitors being equal to the total capacitance of N capacitors distributed in binary from 1, the ratio between M and N being less than or equal to a set threshold, the highest bit capacitance in the N+M capacitors being less than the sum of the capacitances of 2N unit capacitors, the unit capacitor being used to represent the capacitance of the first bit capacitor, the set threshold and the highest bit capacitance in the N+M capacitors being used together to make the working rate of the analog-to-digital conversion circuit meet a preset working rate, N and M being positive integers, 1≤M<N, and N≥10; a comparison module, whose non-inverting input end is connected to the output end of the capacitor array and whose inverting input end is connected to a reference voltage, the comparison module being used for comparing the quantization voltage and the reference voltage N+M times and outputting a corresponding comparison result signal according to the comparison result of each time, the corresponding quantization voltage of each time being controlled by the quantization control signal group; a capacitor potential switching module, configured to output the corresponding quantization control signal group according to the comparison result signal of each time; a weight conversion addition module, configured to perform weight conversion addition operation on the N+M comparison result signals and output the digital signal of N bits; a register module, configured to store and synchronously output the digital signal of N bits.
2. The analog-to-digital conversion circuit of claim 1, wherein, The capacitor array further comprises N+M potential switching switches, the N+M potential switching switches and the N+M capacitors corresponding one-to-one, the first end of the potential switching switch being connected to the lower plate of the corresponding capacitor, the second end, the third end and the fourth end of the potential switching switch being connected to the external input signal, a power voltage and a ground voltage in turn, and the upper plate of the capacitor being connected to the non-inverting input end of the comparison module; a common-mode voltage sampling switch, the first end of the common-mode voltage sampling switch being connected to the non-inverting input end of the comparison module and the upper plate of all capacitors respectively, and the second end of the common-mode voltage sampling switch being connected to the reference voltage; the sampling signal group comprising a first sampling signal and a second sampling signal, the first sampling signal being used for controlling the first end of all the potential switching switches to be connected to the second end of itself in a sampling stage, and the second sampling signal being used for controlling the common-mode voltage sampling switch to be turned on in the sampling stage; the quantization control signal group comprising N+M first quantization control signals and N+M second quantization control signals, the first quantization control signal and the second quantization control signal being used for controlling the first end of the corresponding potential switching switch to be connected to the third end or the fourth end of itself in a quantization comparison stage.
3. The analog-to-digital conversion circuit of claim 2, wherein, The potential switching switch is specifically a single-pole three-throw switch, a first end of the single-pole three-throw switch corresponds to a first end of the potential switching switch, a first output end of the single-pole three-throw switch corresponds to a second end of the potential switching switch, a second output end of the single-pole three-throw switch corresponds to a third end of the potential switching switch, a third output end of the single-pole three-throw switch corresponds to a fourth end of the potential switching switch, and a control end of the single-pole three-throw switch is connected with the first sampling signal in a sampling stage and connected with the corresponding quantization control signal in a quantization comparison stage.
4. The analog-to-digital conversion circuit of claim 2, wherein, The common-mode voltage sampling switch comprises a first NMOS tube, a drain of the first NMOS tube serving as a first end of the common-mode voltage sampling switch, a source of the first NMOS tube serving as a second end of the common-mode voltage sampling switch, and a gate of the first NMOS tube connected with the second sampling signal.
5. The analog-to-digital conversion circuit of claim 1, wherein, N is equal to 12, M is equal to 2, the value of the eleventh capacitor is equal to 2 9 times the value of a unit capacitor, the value of the twelfth capacitor is equal to 2 9 times the value of a unit capacitor, the value of the thirteenth capacitor is equal to 2 10 times the value of a unit capacitor, the value of the fourteenth capacitor is equal to 2 10 times the value of a unit capacitor.
6. The analog-to-digital conversion circuit of claim 1, wherein, N is equal to 12, M is equal to 1, the value of the eleventh capacitor is equal to 2 10 units of capacitance, the value of the twelfth capacitor is equal to 2 10 units of capacitance, the value of the thirteenth capacitor is equal to 2 10 units of capacitance.
7. The analog-to-digital conversion circuit of claim 1 or 5 or 6, characterized by The weight conversion addition module comprises a weight conversion adder.
8. The analog-to-digital conversion circuit of claim 1, wherein, The reference voltage generation circuit comprises a first resistor, a second resistor and an operational amplifier, a first end of the first resistor is connected with a power supply voltage, a second end of the first resistor is connected with a non-inverting input end of the operational amplifier and a first end of the second resistor respectively, a second end of the second resistor is connected with a ground end, an output end of the operational amplifier is connected with a self-inverting input end, and the output end of the operational amplifier outputs the reference voltage.
9. Circuitry, characterized by The analog-to-digital conversion circuit comprises the circuit system.
10. An electronic device, comprising: The circuit system comprises the circuit system.