SIP radio frequency surface-mounted IQ quadrature demodulator

Abstract

The utility model discloses an SIP radio frequency surface-mounted IQ quadrature demodulator, which relates to the technical field of semiconductor demodulator devices, and comprises a substrate and a phase-locked loop circuit arranged on the substrate, the phase-locked loop circuit is connected with a power divider and a differential buffer output unit, the power divider and the differential buffer output unit are connected with a front-end filter, and the front-end filter is connected with a power divider and a differential buffer output unit. The front-end filter is connected with a quadrature device, the quadrature device is connected with a first multiplier and a second multiplier, the first multiplier is connected with a first signal input end and a first tail-end filter, the second multiplier is connected with a second signal input end and a second tail-end filter, the first tail-end filter is connected with a first signal output end, and the second tail-end filter is connected with a second signal output end. And the second tail end filter is connected with the second signal output end. The device provided by the utility model has the advantages of small size, integration, multiple functions and good orthogonal demodulation effect.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor demodulation device technology, specifically to a SIP RF surface-mount IQ quadrature demodulator. Background Technology

[0002] Existing SIP (System-in-Package) RF surface-mount IQ (In-phase and Quadrature) demodulators are mainly implemented using discrete components or modular architectures. While discrete component architectures offer basic demodulation functionality, they suffer from drawbacks such as non-adjustable amplitude and phase balance (phase deviation typically exceeds ±2°, amplitude deviation is greater than ±1dB), limited functionality (supporting only fixed demodulation modes), and lack of digital control, making them unsuitable for the dynamic requirements of complex communication systems. Modular architectures, while improving performance through integrated circuitry, generally have a size exceeding 30×30×10mm. 3 This results in low system integration, high power consumption, and reliance on imported chip technology, posing supply chain risks. In addition, the insufficient matching accuracy between the final stage filter and the multiplier in traditional solutions leads to a deterioration in carrier rejection ratio and sideband rejection ratio, affecting the quality of intermediate frequency signals.

[0003] To address the aforementioned issues, there is an urgent need for a solution that combines miniaturization, high-precision amplitude and phase balance (phase error ≤ ±0.5°, amplitude error ≤ ±0.5dB), multi-functionality and configurability (supporting 0.3GHz-4GHz broadband operation and up / down conversion modes), and complete domestic integration, in order to overcome the bottlenecks of existing technologies in terms of integration, flexibility, and reliability. Utility Model Content

[0004] To address the shortcomings of existing technologies, this utility model provides a SIP RF surface-mount IQ quadrature demodulator.

[0005] A SIP (Surface Mount IQ) quadrature demodulator includes a substrate and a phase-locked loop (PLL) circuit disposed on the substrate. The PLL circuit is connected to a power divider and a differential buffer output unit. The power divider and differential buffer output unit are connected to a front-end filter. The front-end filter is connected to a quadrature unit. The quadrature unit is connected to a first multiplier and a second multiplier. The first multiplier is connected to a first signal input terminal and a first terminal filter. The second multiplier is connected to a second signal input terminal and a second terminal filter. The first terminal filter is connected to a first signal output terminal, and the second terminal filter is connected to a second signal output terminal. The PLL circuit receives an external reference signal and forms an initial carrier signal based on the external reference signal, then inputs the initial carrier signal to the power divider and differential buffer output unit. The power divider and differential buffer output unit distribute the initial carrier signal and form a carrier signal to be processed, and then... A carrier signal is input to a front-end filter; the front-end filter outputs the filtered carrier signal to an orthogonalizer; the orthogonalizer separates the filtered carrier signal into a first orthogonal carrier signal and a second orthogonal carrier signal, the phase difference between the first and second orthogonal carrier signals being 90°; a first multiplier mixes the first orthogonal carrier signal with a radio frequency input signal from a first signal input terminal to generate a first intermediate frequency signal and outputs it to a first terminal filter; a second multiplier mixes the second orthogonal carrier signal with a radio frequency input signal from a second signal input terminal to generate a second intermediate frequency signal and outputs it to a second terminal filter; the first and second terminal filters respectively filter the first and second intermediate frequency signals and output the filtered first and second intermediate frequency signals to a first signal output terminal and a second signal output terminal, respectively.

[0006] Optionally, the phase-locked loop circuit includes a third signal input terminal, an LLP, a PFD, an LLCP, and an N-fold down-converting unit connected in sequence. The N-fold down-converting unit is connected to the power divider and the differential buffer output unit. The PFD is connected to a current-type charge pump, which is connected to a VCO. The VCO is connected to the power divider and the differential buffer output unit. The third signal input terminal is used to input an external reference signal to the LLP.

[0007] Optionally, a first diode is provided between the power divider and the differential buffer output unit and the front-end filter. The cathode of the first diode is connected to the power divider and the differential buffer output unit, and the anode of the first diode is connected to the front-end filter.

[0008] Optionally, a second diode is provided between the first end filter and the first signal output terminal, with the cathode of the second diode connected to the first end filter and the anode of the first diode connected to the first signal output terminal.

[0009] Optionally, a third diode is provided between the second end filter and the second signal output terminal, wherein the cathode of the third diode is connected to the second end filter and the anode of the third diode is connected to the second signal output terminal.

[0010] Optionally, the N-fold down-frequency unit includes an integer divider and a fractional divider.

[0011] Optionally, the substrate is a multilayer ceramic substrate, and the package size is 16×16×4mm. 3 .

[0012] The beneficial effects of this utility model are reflected in:

[0013] In the entire SIP RF surface-mount IQ quadrature demodulator, firstly, the quadrature unit adopts a 90° phase power divider structure, combined with a symmetrical layout design of the gallium arsenide mixer, to ensure phase consistency from a hardware perspective. Dynamic screening (e.g., device matching with phase ±0.1° and amplitude ±0.2dB) is performed on the multiplier and final-stage filter to compensate for errors caused by process fluctuations, meeting the stringent IQ balance requirements of high-order modulation (e.g., 256QAM). Furthermore, a QFN type SIP package (16×16×4mm) is used. 3 This device integrates a silicon-based CMOS phase-locked loop (PLL), a gallium arsenide mixer, and ceramic filters, among other multi-process die components, supporting surface-mount (SMD) mounting for high-density communication equipment. Furthermore, the PLL supports a wideband output from 0.3GHz to 4GHz, covering L-band to C-band. The PLL division ratio and filter frequency band can be configured via an MCU, enabling multi-mode switching such as single-mode demodulation, quadrature demodulation, and up / down conversion. It supports broadband applications such as 5G and satellite communication. Additionally, the final-stage filter suppresses image frequencies, and the dual-balanced mixer suppresses carrier residual components through common-mode feedback, achieving a carrier rejection ratio (CR) >50dBc, a sideband rejection ratio (SNR) >40dBc, and an output intermediate frequency signal-to-noise ratio (SNR) >70dB. Attached Figure Description

[0014] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0015] Figure 1This is a connection diagram of the SIP RF surface-mount IQ quadrature demodulator of this utility model;

[0016] Figure 2 The product IQ quadrature waveform of the SIP RF surface-mount IQ quadrature demodulator of this utility model;

[0017] Figure 3 This is the circuit schematic diagram of the SIP RF surface-mount IQ quadrature demodulator of this utility model.

[0018] Figure label:

[0019] 1-Phase-locked loop circuit, 11-Third signal input terminal, 2-Power divider and differential buffer output unit, 3-Front-end filter, 4-Quadrature circuit, 5-First multiplier, 6-Second multiplier, 7-First signal input terminal, 8-First end filter, 8-Second signal input terminal, 9-Second end filter, 10-First signal output terminal, 12-Second signal output terminal, 13-First diode, 14-Second diode, 15-Third diode. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can typically be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] like Figure 1 , Figure 2 and Figure 3As shown, a SIP (Surface Mount IQ) quadrature demodulator is provided, including a substrate and a phase-locked loop (PLL) circuit disposed on the substrate. The PLL circuit is connected to a power divider and a differential buffer output unit. The power divider and differential buffer output unit are connected to a front-end filter. The front-end filter is connected to a quadrature unit. The quadrature unit is connected to a first multiplier and a second multiplier. The first multiplier is connected to a first signal input terminal and a first terminal filter. The second multiplier is connected to a second signal input terminal and a second terminal filter. The first terminal filter is connected to a first signal output terminal, and the second terminal filter is connected to a second signal output terminal. The PLL circuit receives an external reference signal and forms an initial carrier signal based on the external reference signal, then inputs the initial carrier signal to the power divider and differential buffer output unit. The power divider and differential buffer output unit distribute the initial carrier signal and form a carrier signal to be processed, and then... The carrier signal to be processed is input to a front-end filter; the front-end filter outputs the filtered carrier signal to be processed to an orthogonalizer; the orthogonalizer separates the filtered carrier signal into a first orthogonal carrier signal and a second orthogonal carrier signal, the phase difference between the first orthogonal carrier signal and the second orthogonal carrier signal being 90°; the first multiplier mixes the first orthogonal carrier signal with the radio frequency input signal from the first signal input terminal to generate a first intermediate frequency signal and outputs it to a first terminal filter; the second multiplier mixes the second orthogonal carrier signal with the radio frequency input signal from the second signal input terminal to generate a second intermediate frequency signal and outputs it to a second terminal filter; the first terminal filter and the second terminal filter respectively filter the first intermediate frequency signal and the second intermediate frequency signal, and output the filtered first intermediate frequency signal and the second intermediate frequency signal to the first signal output terminal and the second signal output terminal, respectively.

[0024] In this embodiment, it should be noted that during the entire electrical signal flow process, firstly, the phase-locked loop (PLL) circuit generates an initial carrier signal; furthermore, the power divider and differential buffer output unit distribute the carrier signal. The initial carrier signal output from the PLL is input to the power divider and differential buffer output unit, which divides the carrier signal into multiple paths (e.g., three paths) and enhances the signal driving capability through the differential buffer circuit, generating the carrier signal to be processed (one of the paths). Preferably, a power divider using gallium arsenide compound semiconductor technology is employed to achieve low loss (<0.5dB) and high isolation (>30dB), avoiding amplitude imbalance caused by signal crosstalk. Further, The front-end filter eliminates out-of-band interference. The carrier signal to be processed passes through the front-end filter (ceramic chip filter) for out-of-band spurious suppression, filtering out high-frequency harmonics and noise in the phase-locked loop output signal, retaining a clean carrier signal input to the quadrature. Preferably, the high Q-value characteristic of the ceramic filter improves the carrier signal quality and reduces phase noise in the subsequent mixing process. Further, the quadrature generates a high-precision quadrature carrier signal. The filtered carrier signal is input to the quadrature (90° phase power divider), which separates the single-channel carrier signal into a first quadrature carrier signal (I-channel) and a second quadrature carrier signal (Q-channel). The two signals satisfy the following performance: a phase difference of 90° ± 0.5°. (Achieved through device selection and phase compensation design), amplitude difference ±0.5dB (optimized through gallium arsenide mixer matching), breaking through the bottleneck of ±2° phase deviation and ±1dB amplitude deviation of traditional discrete devices, significantly improving demodulation accuracy; furthermore, the double-balanced mixer achieves quadrature demodulation, where I path: the first quadrature carrier signal and the RF signal from the first signal input terminal (splied by a power divider) are input to the first multiplier (double-balanced mixer), and Q path: the second quadrature carrier signal and the RF signal from the second signal input terminal are input to the second multiplier. The multiplier down-converts the RF signal to the intermediate frequency (e.g., 150MHz) through nonlinear mixing, generating the first intermediate frequency signal (I) and the second quadrature carrier signal (Q). The intermediate frequency (IF) signal (Q) is processed by a dual-balanced mixer using gallium arsenide (GaAs) technology to achieve high linearity (IIP3 > 20 dBm) and low noise figure (NF < 10 dB), while suppressing carrier leakage (> 40 dBc). Finally, a final-stage filter optimizes the IF signal quality. The mixed IF signal is input to the final-stage filter (bandpass filter) to filter out image frequencies and out-of-band spurious signals generated during mixing, retaining the target IF signal. The output level is then boosted by an amplifier. The final-stage filter and multiplier work together to optimize the signal, achieving ±0.4° phase error and ±0.3 dB amplitude error compensation through screening. The final output quadrature IF signal has a phase error ≤ ±0.5° and an amplitude error ≤ ±0.5 dB.

[0025] Meanwhile, the quadrature circuit adopts a 90° phase power divider structure, combined with the symmetrical layout design of the gallium arsenide mixer, to ensure phase consistency from a hardware perspective; the multiplier and the final stage filter are dynamically screened (such as device matching with phase ±0.1° and amplitude ±0.2dB) to compensate for errors caused by process fluctuations; therefore, the quadrature signal phase difference is 90°±0.5° and the amplitude difference is ±0.5dB, which meets the stringent requirements of IQ balance for high-order modulation (such as 256QAM).

[0026] In summary, this technical solution addresses the shortcomings of traditional RF IQ demodulators in terms of amplitude and phase balance, size, and functional flexibility through SIP multi-process integration, high-precision quadrature design, dynamic device selection, and domestic process chain.

[0027] In one embodiment, the phase-locked loop circuit includes a third signal input terminal, an LLP, a PFD, an LLCP, and an N-fold down-converting unit connected in sequence. The N-fold down-converting unit is connected to the power divider and the differential buffer output unit. The PFD is connected to a current-type charge pump, which is connected to a VCO. The VCO is connected to the power divider and the differential buffer output unit. The third signal input terminal is used to input an external reference signal to the LLP.

[0028] In this embodiment, it should be noted that in the phase-locked loop (PLL) circuit, the external reference signal (such as a 10MHz reference clock) is noise-suppressed by the PLL circuit's reference low-pass filter (LLP), and then input to the phase-frequency discriminator (PFD). The PFD compares the phase of the reference signal with the frequency-division feedback signal (after an integer / fractional divider) of the voltage-controlled oscillator (VCO) output signal. An error voltage is generated by the charge pump (CP) and the loop divider filter (LLCP), dynamically adjusting the VCO frequency, and finally outputting an initial carrier signal of 0.3GHz-4GHz. Preferably, the PLL uses silicon-based CMOS technology, supports frequency steps of less than 10Hz and fast frequency locking (power-on), solving the problems of insufficient frequency stability and flexibility of traditional discrete devices.

[0029] In one embodiment, a first diode is disposed between the power divider and the differential buffer output unit and the front-end filter. The cathode of the first diode is connected to the power divider and the differential buffer output unit, and the anode of the first diode is connected to the front-end filter.

[0030] In this embodiment, it should be noted that the first diode can be a PIN diode. By utilizing the nonlinear characteristics of the diode, high-frequency harmonic components (such as second harmonics) in the output signal of the power divider are suppressed, thereby reducing the out-of-band rejection pressure of the front-end filter.

[0031] Furthermore, by utilizing the unidirectional conduction characteristic, the influence of the reflected signal from the front-end filter on the power divider is blocked, improving the forward transmission efficiency from the power divider to the filter (insertion loss optimized to <0.2dB), while also enhancing system stability. The bias voltage of the diode is adaptively adjusted through an embedded resistor network in the substrate, avoiding additional power supply requirements.

[0032] In one embodiment, a second diode is disposed between the first end filter and the first signal output terminal, the cathode of the second diode being connected to the first end filter and the anode of the first diode being connected to the first signal output terminal.

[0033] In this embodiment, it should be noted that the second diode can be a Schottky diode. By utilizing the low turn-on voltage (0.3V) characteristic of the Schottky diode, the electrostatic pulse at the output terminal (such as HBM>8kV) can be quickly discharged, protecting the final stage filter and mixer from damage.

[0034] Furthermore, it blocks DC offset voltage that may be introduced by external devices, ensuring pure AC coupling of the intermediate frequency signal and avoiding amplifier saturation. A diode is connected in parallel between the signal path and ground, using a common-mode configuration, which does not affect the integrity of the differential signal.

[0035] In one embodiment, a third diode is disposed between the second end filter and the second signal output terminal, wherein the cathode of the third diode is connected to the second end filter and the anode of the third diode is connected to the second signal output terminal.

[0036] In this embodiment, it should be noted that the third diode can be a TVS diode. When the output terminal encounters a surge voltage (such as lightning strike induction), the TVS diode clamps the voltage to a safe value (such as ±15V) with a nanosecond-level response speed to prevent the back-end circuit from burning out.

[0037] Furthermore, the parasitic capacitance of the diode (<0.5pF) is used to compensate for the output impedance of the filter, thereby optimizing the standing wave ratio (VSWR<1.5) of the intermediate frequency signal under a 50Ω load and improving signal transmission efficiency. The diode and the filter are connected by a microstrip line impedance gradient structure to avoid high-frequency signal reflection.

[0038] In one implementation, the N-fold down-frequency unit includes an integer divider and a fractional divider.

[0039] In this embodiment, it should be noted that the integer divider adopts an asynchronous counter structure with a programmable division ratio N = 1 to 255 for coarse frequency adjustment; the fractional divider uses Σ-Δ modulation technology to achieve the fractional part of the division ratio (e.g., N + 0.1), achieving a resolution of 0.01Hz and eliminating the spurious emission problem of traditional fractional dividers. The outputs of both dividers are selected by a multiplexer (MUX) and fed back to the PFD. Combined with the automatic calibration algorithm of the phase-locked loop, gapless coverage across the entire frequency band (0.3GHz-4GHz) and spurious emission suppression >70dBc are achieved, significantly outperforming a single divider architecture.

[0040] In one embodiment, the substrate is a multilayer ceramic substrate, and the package size is 16×16×4mm. 3 .

[0041] In this embodiment, it should be noted that the substrate is a multilayer ceramic substrate manufactured using a high-temperature co-fired ceramic (HTCC) process, with dimensions of 16mm × 16mm × 4mm, containing 6 layers of metal interconnects and 2 layers of ground planes. The substrate surface integrates silicon-based CMOS phase-locked loop dies, gallium arsenide mixer dies, ceramic filter dies, and gold wire bonding interconnect structures (0.018μm wire diameter). Through three-dimensional stacking packaging technology, dies from different processes are vertically interconnected, shortening the signal path to <1mm and reducing parasitic inductance (<0.1nH) and crosstalk (<-60dB). A QFN-type pad array (0.5mm spacing) is provided at the bottom of the substrate, supporting reflow soldering surface mount mounting. The coefficient of thermal expansion (CTE) matches the PCB, ensuring solder joint reliability across the entire temperature range (-40℃~125℃). Metallized sidewalls are provided at the substrate edges to enhance electromagnetic shielding (shielding effectiveness >40dB), meeting military-grade EMC requirements.

[0042] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0043] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0044] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model, and they should all be covered within the scope of the claims and specification of this utility model.

Claims

1. A SIP radio frequency table IQ quadrature demodulator comprising a substrate and a phase locked loop circuit disposed on the substrate, characterized by, The phase-locked loop circuit is connected with a power divider and a differential buffer output unit, the power divider and the differential buffer output unit are connected with a front-end filter, the front-end filter is connected with a quadrature generator, the quadrature generator is connected with a first multiplier and a second multiplier, the first multiplier is connected with a first signal input end and a first end filter, the second multiplier is connected with a second signal input end and a second end filter, the first end filter is connected with a first signal output end, and the second end filter is connected with a second signal output end. The phase-locked loop circuit is used for receiving an external reference signal and forming an initial carrier signal according to the external reference signal, and inputting the initial carrier signal to the power divider and the differential buffer output unit. The power divider and the differential buffer output unit are used for completing distribution of the initial carrier signal and forming a to-be-processed carrier signal, and inputting the to-be-processed carrier signal to the front-end filter. The front-end filter is used for outputting the to-be-processed carrier signal after filtering to the quadrature generator. The quadrature generator is used for separating the to-be-processed carrier signal after filtering into a first quadrature carrier signal and a second quadrature carrier signal, and the phase difference between the first quadrature carrier signal and the second quadrature carrier signal is 90°. The first multiplier is used for mixing the first quadrature carrier signal with a radio frequency input signal from the first signal input end, generating a first intermediate frequency signal and outputting the first intermediate frequency signal to the first end filter. The second multiplier is used for mixing the second quadrature carrier signal with a radio frequency input signal from the second signal input end, generating a second intermediate frequency signal and outputting the second intermediate frequency signal to the second end filter. The first end filter and the second end filter are respectively used for filtering the first intermediate frequency signal and the second intermediate frequency signal, and outputting the filtered first intermediate frequency signal and the filtered second intermediate frequency signal to the first signal output end and the second signal output end respectively.

2. The SIP RF table IQ quadrature demodulator of claim 1, wherein, The phase-locked loop circuit comprises a third signal input end, an LLP, a PFD, an LLCP and an N times frequency reduction unit connected in sequence, the N times frequency reduction unit is connected with the power divider and the differential buffer output unit, the PFD is connected with a current type charge pump, the current type charge pump is connected with a VCO, and the VCO is connected with the power divider and the differential buffer output unit; wherein the third signal input end is used for inputting an external reference signal to the LLP.

3. The SIP RF table IQ quadrature demodulator of claim 1, wherein, A first diode is arranged between the power divider and the differential buffer output unit and the front-end filter, the cathode direction of the first diode is connected with the power divider and the differential buffer output unit, and the anode direction of the first diode is connected with the front-end filter.

4. The SIP RF table IQ quadrature demodulator of claim 3, wherein, A second diode is arranged between the first end filter and the first signal output end, the cathode direction of the second diode is connected with the first end filter, and the anode direction of the first diode is connected with the first signal output end.

5. The SIP RF table IQ quadrature demodulator of claim 1, wherein, A third diode is arranged between the second end filter and the second signal output end, the cathode direction of the third diode is connected with the second end filter, and the anode direction of the third diode is connected with the second signal output end.

6. The SIP RF table IQ quadrature demodulator of claim 2, wherein, The N times frequency reduction unit comprises an integer frequency divider and a fractional frequency divider.

7. The SIP RF table IQ quadrature demodulator of claim 1, wherein, The substrate is a multilayer ceramic substrate, and the package size is 16 x 16 x 4 mm 3 .

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