MOSFET layout and MOSFET device
By optimizing the MOSFET layout, adjusting the number and size of the gate polysilicon contact holes, and adopting a symmetrical structure, the problems of poor contact and leakage current in medium and high voltage SGT MOSFET devices were solved, achieving better contact performance and reduced resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-03-17
AI Technical Summary
When the pitch size of a medium- or high-voltage SGT MOSFET device is large, the gate polysilicon etching forms a V-shaped opening, causing the contact hole to be in a critical state, which may lead to poor contact, IGSS leakage, and poor gate resistance Rg test results.
By optimizing the MOSFET layout, adjusting the number and size of the gate polysilicon contact holes, and adopting a symmetrical structure, two symmetrical gate contact holes are set in each trench region to prevent the contact holes from shifting to the most concave position in the middle, thereby increasing the contact area and reducing the gate contact resistance.
It effectively avoids the risks of poor contact and IGSS leakage, reduces gate contact resistance, and improves device reliability.
Smart Images
Figure CN224006997U_ABST
Abstract
Description
Technical Field
[0001] This application relates to various embodiments in the field of semiconductor technology, and particularly to a MOSFET layout and MOSFET device. Background Technology
[0002] Power SGT MOSFETs are a new type of power semiconductor device that combines the low conduction losses of traditional deep trench MOSFETs with even lower switching losses. SGT MOSFETs are core power control components used in motor drive systems, inverter systems, and power management systems in new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances. For medium- and high-voltage SGT MOSFETs (shielded gate trench MOSFETs), to achieve lower costs and save on masking, the gate polysilicon is typically etched directly instead of chemical mechanical polishing (CMP). While the morphology of most devices remains unaffected, for medium- and high-voltage SGT devices with larger pitch sizes, the trench width is greater, resulting in more gate polysilicon etching and a V-shaped morphology. This can cause the gate contact hole to be in a critical state, potentially preventing it from reaching the gate polysilicon. When voltage is applied, this situation can easily lead to IGSS leakage between the gate and source, and poor gate resistance (Rg) testing. Summary of the Invention
[0003] In order to solve or alleviate the problems in the prior art, this invention provides an improved MOSFET layout and MOSFET device with improved gate polysilicon contact holes, which improves the position of the contact holes, avoids poor contact, and reduces the gate contact resistance to a certain extent.
[0004] In a first aspect, this application provides a MOSFET layout, including: a termination region and a cell region, wherein the termination region is disposed around the cell region;
[0005] The cell region includes a plurality of spaced-apart first trench regions;
[0006] The terminal area includes multiple spaced-apart second trench areas;
[0007] A source electrode contact hole area is provided between multiple first trenches;
[0008] Each of the first trench regions has two spaced-apart gate contact hole regions.
[0009] In a preferred embodiment of this application, the two gate contact hole regions have the same area.
[0010] In a preferred embodiment of this application, the two gate contact hole regions in each of the first trench regions are located at relative positions within the first trench regions.
[0011] In a preferred embodiment of this application, two gate contact holes are disposed at symmetrical positions in the first trench region.
[0012] Compared with the prior art, the MOSFET layout provided in this application provides two spaced gate contact hole regions in each of the first trench regions. By optimizing the layout, that is, adjusting the number and size of the gate polysilicon contact holes, improving the position of the gate contact holes, and adopting a symmetrical structure, the contact holes are prevented from shifting to the most concave position in the middle, which would lead to poor contact. This increases the gate contact area and reduces the gate contact resistance.
[0013] Secondly, this application also provides a MOSFET device, fabricated according to the layout described in the first aspect, the device including a plurality of first trenches;
[0014] Multiple first trenches are disposed in the epitaxial layer;
[0015] Each of the first trenches is provided with a gate polysilicon and a source polysilicon, which are isolated by a dielectric layer;
[0016] The gate polysilicon is provided with two gate contact holes spaced apart to lead out the gate; a source contact hole is provided between each of the two adjacent first trenches to lead out the source.
[0017] Compared with the prior art, the beneficial effects of the MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here. Attached Figure Description
[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0019] Figure 1 This is a schematic diagram of a MOSFET layout provided in this application;
[0020] Figure 2 This is a schematic diagram of the structure of a MOSFET device provided in this application; Detailed Implementation
[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0022] like Figure 1 As shown, in a first aspect, this application provides a MOSFET layout, including: a termination region and a cell region, wherein the termination region is disposed around the cell region;
[0023] The cell region includes a plurality of spaced-apart first trench regions 1;
[0024] The terminal area includes multiple spaced-apart second trench areas 2;
[0025] A source electrode contact hole region 3 is provided between multiple first trenches 1;
[0026] Each of the first trench regions 1 is provided with two spaced-apart gate contact hole regions 4.
[0027] In a preferred embodiment of this application, the two gate contact hole regions 4 have the same area.
[0028] In a preferred embodiment of this application, the two gate contact hole regions 4 in each of the first trench regions 1 are located at relative positions to each other in the first trench region 1.
[0029] In a preferred embodiment of this application, two gate contact holes 4 are disposed at symmetrical positions in the first trench region 1.
[0030] This application provides two spaced gate contact hole regions 4 in each of the first trench regions 1. By optimizing the layout, i.e. adjusting the number and size of the gate polysilicon contact holes, the position of the gate contact holes is improved. A symmetrical structure is adopted to avoid the contact holes shifting to the most concave position in the middle, which would lead to poor contact. This increases the gate contact area and reduces the gate contact resistance.
[0031] like Figure 2 As shown, in a second aspect, this application also provides a MOSFET device, fabricated according to the layout described in the first aspect, the device including a plurality of first trenches 5;
[0032] Multiple first trenches 5 are disposed in the epitaxial layer 11;
[0033] Each of the first trenches 5 is provided with a gate polysilicon 8 and a source polysilicon 6, which are isolated by a dielectric layer 9.
[0034] The gate polysilicon 8 is provided with two gate contact holes 7 spaced apart to lead out the gate; a source contact hole 6 is provided between each of the two adjacent first trenches 5 to lead out the source.
[0035] In addition, in this embodiment, the source contact hole 6 leads out the source through the source metal 9, and the gate contact hole 7 leads out the gate through the gate metal 10. The back side of the epitaxial layer 11 is the drain metal 12 of the entire device to lead out the drain.
[0036] Compared with the prior art, the beneficial effects of the MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here.
[0037] This application optimizes the layout by adjusting the number and size of the gate polysilicon contact holes, improving the position of the contact holes, adopting a symmetrical structure, and appropriately reducing the size of the contact holes to avoid the gate contact holes shifting to the most concave position in the middle, which would lead to poor contact.
[0038] This application employs an improved gate contact hole 7, which effectively contacts the gate polysilicon, avoiding the risks of poor contact, IGSS, and Rg electrical defects. The increased number of gate polysilicon contact holes 7 increases the contact area and also reduces gate contact resistance. For high-voltage devices in power SGTs with large pitch sizes, the traditional gate polysilicon, after etching, forms a severe V-shaped opening, making the contact hole prone to a critical state, leading to risks such as IGSS leakage and poor Rg testing.
[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A MOSFET layout, characterized in that, Comprising: a terminal region and a cell region, the terminal region being disposed around the cell region; the cell region comprising a plurality of first trench regions disposed at intervals; the terminal region comprising a plurality of second trench regions disposed at intervals; a source contact hole region being disposed between a plurality of the first trenches; two gate contact hole regions disposed at intervals being disposed in each of the first trench regions.
2. A MOSFET layout as defined in claim 1, wherein, The two gate contact hole regions are of the same area.
3. The MOSFET layout of claim 1, wherein, The two gate contact hole regions in each of the first trench regions are disposed at opposite positions of the first trench region.
4. The MOSFET layout of claim 1, wherein, The two gate contact hole regions are disposed at symmetrical positions of the first trench region.
5. A MOSFET device, characterized by, According to the layout preparation of any one of claims 1 to 3, the device comprises a plurality of first trenches; a plurality of the first trenches are disposed in an epitaxial layer; gate polysilicon and source polysilicon are disposed in each of the first trenches, the gate polysilicon and the source polysilicon being isolated by a dielectric layer; two gate contact holes disposed at intervals are disposed in the gate polysilicon to lead out the gate; a source contact hole is disposed between adjacent two of the first trenches to lead out the source.