Controller

Abstract

The utility model provides a controller, which at least comprises a main chip unit, a voltage dividing unit and an IO cascade expansion unit of a to-be-identified type, an electric signal input end of the voltage dividing unit is electrically connected with a to-be-expanded IO end of the main chip unit, the voltage dividing unit comprises at least two voltage dividing branches, the equivalent resistance values of the voltage dividing branches are different, and the equivalent resistance values of the voltage dividing branches are different. And one voltage division branch is electrically connected with one type of IO cascade expansion unit. According to the technical scheme, due to the fact that the equivalent resistance values of all the voltage dividing branches are different, one type of IO cascade expansion unit is connected with one executing mechanism. The main chip unit acquires different electric signals due to different equivalent resistance values of all voltage division branches of the voltage division unit, and the IO port to be expanded of the controller can automatically identify different types of IO cascade expansion units in communication connection, so that different execution mechanisms are identified, and rapid decision making, data interaction and the like are carried out on the execution mechanisms.

Description

Technical Field

[0001] This application relates to the field of air conditioning control systems, specifically to a controller. Background Technology

[0002] The main chip MCU acts as the brain of the controller, storing the control program. This program detects input signals and controls the load accordingly. As the controller's control requirements increase, the main chip needs to collect more information and control more functions. Therefore, it is necessary to add I / O cascade expansion units to the main chip's I / O signal terminals to expand the I / O ports.

[0003] As customers' demands for air conditioning functions increase, the number of controllable operations also grows. This includes controlling the compressor, fan, and inverter. Taking compressor control as an example, it requires controlling the compressor's power, temperature, voltage / current parameters, and motor parameters. The controller needs to obtain these parameter information and make corresponding judgments and operation commands, thus involving a large amount of data uploading and downloading. Different actuators require different configurations of I / O cascade expansion circuits.

[0004] As the inventors know, when the I / O port to be expanded is connected to different types of I / O cascade expansion circuits, the I / O port to be expanded cannot identify which actuator the data it receives belongs to, and it is also unable to determine how to make a decision and perform data interaction. Utility Model Content

[0005] In response, this application provides a controller whose I / O ports to be expanded can automatically identify different types of I / O cascade expansion units connected to the communication, thereby identifying different actuators and enabling rapid decision-making and data interaction with the actuators.

[0006] To achieve the above objectives, the technical solution provided in this application is as follows:

[0007] This application provides a controller, which includes at least a main chip unit, a voltage divider unit, and an I / O cascade expansion unit of a type to be identified. The electrical signal input terminal of the voltage divider unit is electrically connected to the I / O terminal to be expanded of the main chip unit. The voltage divider unit includes at least two voltage divider branches, each with a different equivalent resistance value. One voltage divider branch is electrically connected to an I / O cascade expansion unit of a certain type.

[0008] In the above technical solution, the electrical signal input terminal of the voltage divider unit is electrically connected to the I / O terminal to be expanded of the main chip unit. The equivalent resistance values ​​of each voltage divider branch in the voltage divider unit are different, and each voltage divider branch is electrically connected to one type of I / O cascade expansion unit. Because the equivalent resistance values ​​of each voltage divider branch are different, one type of I / O cascade expansion unit is connected to one actuator. Because the equivalent resistance values ​​of each voltage divider branch in the voltage divider unit are different, the main chip unit acquires different electrical signals. The I / O port to be expanded of the controller can automatically identify the different types of I / O cascade expansion units connected for communication, thereby identifying different actuators and enabling rapid decision-making and data interaction with the actuators. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0010] Figure 1 A controller hardware block diagram provided for an embodiment of this application;

[0011] Figure 2 This application provides an embodiment of one type of IO cascade expansion unit;

[0012] Figure 3 This application provides another type of IO cascade expansion unit embodiment. Detailed Implementation

[0013] To provide a clearer and more complete description of the technical solutions in this application, the following explanation will be based on the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. All other technical solutions obtained by those skilled in the art based on the technical solutions in this application without inventive effort are within the scope of protection of this application.

[0014] To address the problems existing in the background art, embodiments of this application provide a controller, such as... Figure 1 As shown, it includes at least: a main chip unit 100, a voltage divider unit 200, and an I / O cascade expansion unit of the type to be identified. Taking this application as an example, there are two I / O cascade expansion units of the type to be identified, namely an I / O cascade expansion unit 301 of the first type and an I / O cascade expansion unit 302 of the second type. The different types of I / O cascade expansion units are connected to different actuators.

[0015] The main chip unit 100 here can be an MCU chip, which needs to be connected to the corresponding basic circuit when in use. The voltage divider unit 200 has two or more voltage divider branches, each with a different equivalent resistance value. One voltage divider branch is electrically connected to a type of IO cascade expansion unit. The electrical signal input terminal of the voltage divider unit 200 is electrically connected to the IO terminal to be expanded in the main chip unit 100.

[0016] In this embodiment, the voltage divider unit 200 may include two voltage divider branches connected in series with resistors R1 and R2 of different resistance values, and the resistance values ​​of resistors R1 and R2 are different. The resistance in the voltage divider branch mentioned here is the equivalent resistance of the voltage divider branch. The first voltage divider branch and the second voltage divider branch are connected in parallel. The parallel connection terminal serves as the electrical signal input terminal of the voltage divider unit and is electrically connected to the I / O terminal to be expanded of the main chip unit. The first voltage divider branch is electrically connected to a first type of I / O cascade expansion unit, and the second voltage divider branch is connected to a second type of I / O cascade expansion unit. The first voltage divider branch is connected to the first type of I / O cascade expansion unit 301, and the second voltage divider branch is connected to the second type of I / O cascade expansion unit 302.

[0017] In this technical solution, because the equivalent resistance value of each voltage divider branch is different, one type of IO cascade expansion unit is connected to one actuator. Because the equivalent resistance value of each voltage divider branch of the main chip unit 100 is different, the electrical signals acquired are different. This allows the main chip unit 100 to automatically identify the type of IO cascade expansion unit connected to each voltage divider branch, thereby identifying different actuators and enabling rapid decision-making and data interaction with the actuators.

[0018] According to the above technical solution, one of the I / O ports of the main control chip unit to be expanded can automatically identify the different types of I / O cascade expansion units connected to it, and identify the connected actuators.

[0019] The main control chip unit 100 can have more than one I / O port to be expanded. Each port to be expanded uses the above method to identify the type of I / O cascade expansion unit. This allows for the simultaneous identification of different types of I / O cascade expansion units and the corresponding connected actuators.

[0020] In practice, the cascaded expansion unit for the type to be identified is obtained by cascading at least two expansion chips. The cascading methods are (1) parallel input, serial output; (2) serial input, parallel output. In an cascaded expansion unit, it is not necessary for all expansion chips to have the same configuration and model. Two different types of cascaded expansion units refer to two cascaded expansion units where the configuration and model of the expansion chips are different.

[0021] In one embodiment, the main chip unit 100, the voltage divider unit 200, and the IO cascade expansion unit of the type to be identified are all disposed on the substrate, and the signal output port of one voltage divider branch is electrically connected to the signal receiving port of one IO cascade expansion unit of the type to be identified.

[0022] In practice, the substrate can have multiple different types of IO cascade expansion units, such as Figure 1 The first type of IO cascade expansion unit 301 and the second type of IO cascade expansion unit 302 are provided. Each type of IO cascade expansion unit has a corresponding signal receiving port. The voltage divider unit 200 can electrically connect the signal receiving ports of different types of IO cascade expansion units through different voltage divider branches.

[0023] In another embodiment, the main chip unit 100 and voltage divider unit 200 of this application can be disposed on a substrate, and the I / O cascade expansion unit of the type to be identified is disposed on an expansion board. Here, there can be multiple I / O cascade expansion units of different types on the expansion board, each corresponding to a different signal receiving port. Alternatively, one type of I / O cascade expansion unit can be assigned to one expansion board. The signal output port of one voltage divider branch of the voltage divider unit 200 is electrically connected to a corresponding signal receiving port of the expansion board.

[0024] As an optimization solution, to achieve controller miniaturization, this application stacks the substrate and the expansion board. Specifically, the substrate and expansion board are stacked vertically, for example, with the expansion board above the substrate or the substrate above the expansion board. This way, the internal space of the controller only occupies the surface area of ​​one of the substrate or expansion board.

[0025] To achieve stacking, this application provides two stacking structures as examples, but these do not constitute structural limitations. All structures with the same function are within the scope of protection of this application.

[0026] In one embodiment, the substrate and the expansion board are stacked via a plug-in structure. The plug-in structure includes pins and sockets. For example, if the substrate uses pins as the signal output port of the voltage divider branch of the voltage divider unit 200, then the expansion board uses sockets as the signal receiving port. Alternatively, if the substrate uses sockets as the signal receiving port, then the expansion board uses pins as the signal output port of the voltage divider branch. For stable installation, double-row or multi-row pins and sockets can be used.

[0027] In another embodiment, the substrate and the expansion board are stacked via bolted connections, which are conventional connections and therefore not illustrated. Here, whether an expansion board has multiple different types of cascaded I / O expansion units or only one type of cascaded I / O expansion unit, electrical connections can be made using, for example, serial lines.

[0028] The substrate and the expansion board can be stacked either with the substrate on top of the expansion board or with the expansion board on top of the substrate.

[0029] As described above, the cascading methods of IO cascade expansion units are (1) parallel input, serial output; (2) serial input, parallel output.

[0030] In method (1), the IO cascade expansion unit includes at least N expansion chips, N≥2, where N is a positive integer greater than or equal to 2. The IO cascade expansion unit of the type to be identified is used to expand the signal input port of the main chip unit 100. The IO port to be expanded of the main chip unit 100 is its signal input port. Then, the output signal port of each expansion chip is cascaded with the output signal port of the next expansion chip, and the output IO signal port of the first expansion chip is electrically connected to the signal input port of the main chip unit 100. The input IO signal ports of each expansion chip are used as the signal input ports of the main chip unit 100.

[0031] For example Figure 2 The A-75HC165 chip is used as the expansion chip. When three expansion chips are cascaded, 24 signal input ports can be added. Each expansion chip includes at least a control enable signal port SH / LD, an input clock signal port CLK, and a serial output signal port QH, which are electrically connected to the signal input ports of the main chip unit 100. The output I / O signal port SER of the expansion chip is connected to the serial output signal port QH of the next-level expansion chip.

[0032] It is understandable that by using only 3 I / O ports of the main chip unit 100, the signal input ports of the main chip unit 100 can be expanded to meet the application environments with greater I / O port requirements.

[0033] In practical applications, when the expansion chip is the last-level expansion chip, that is... Figure 2 When the expansion chip is the third-level expansion chip, the serial input signal port SER of the first expansion chip U1 is left floating; when the expansion chip is the first-level expansion chip, the output IO signal port QH of the first expansion chip U1 is electrically connected to the signal input port of the main chip unit 100.

[0034] It should be noted that, with Figure 2 Taking the illustrated I / O port expansion control circuit as an example, the first expansion chip U1 includes eight input I / O signal ports, namely E, F, G, H, D, C, B, and A, which can receive eight input signals. These input signals can be detection signals; specifically, the detection signals can be switch signals or DIP switches, depending on the application environment and user requirements, all of which are within the scope of protection of this application.

[0035] It should also be noted that when multiple expansion chips are used... Figure 2 After cascading as shown, data from each expansion chip can be pushed serially to the previous stage, that is, data can be pushed from the third expansion chip to the second expansion chip, and then from the second expansion chip to the first expansion chip.

[0036] In method (2), the IO cascade expansion unit includes at least N expansion chips, N≥2, where N is a positive integer greater than or equal to 2. The IO cascade expansion unit of the type to be identified is used to expand the signal output port of the main chip unit. The IO port to be expanded of the main chip unit 100 is its signal output port. Then, the input signal port of each expansion chip is cascaded with the input signal port of the next expansion chip. The input IO signal port of the first expansion chip is electrically connected to the signal output port of the main chip unit 100, and the output IO signal port of each expansion chip is used as the signal output port of the main chip unit 100.

[0037] For example Figure 3 The A-74HC595 chip is used as the expansion chip. When three expansion chips are cascaded, 24 signal output ports can be expanded. Each expansion chip includes at least an input clock signal port SRCLK, a serial input signal port SER, an enable clock signal port RCLK, and an enable signal port OE, which are electrically connected to the signal output ports of the main chip unit 100.

[0038] It is understandable that by using only four I / O ports of the main chip unit 100, the signal output ports of the main chip unit 100 can be expanded to meet the application environments with greater I / O port requirements.

[0039] In practical applications, when the expansion chip is the last-level expansion chip, that is... Figure 3 When the second expansion chip IC1 is the third-level expansion chip, its serial output signal port QH' is left floating; when the expansion chip is the first-level expansion chip, its serial input signal port SER is electrically connected to the signal output port of the main chip unit.

[0040] It should be noted that, with Figure 3 Taking the output IO port expansion control circuit as an example, the second expansion chip IC1 includes 8 output IO signal ports, namely QA, QB, QC, QD, QE, QF, QG, and QH, which can output 8 output signals.

[0041] It should also be noted that when multiple expansion chips are used... Figure 3 After being cascaded as shown, the data from each expansion chip can be serially pushed to the output control load of the next expansion chip, that is, it can be pushed from the first expansion chip to the second expansion chip, and then from the second expansion chip to the third expansion chip.

[0042] The principles and implementation methods of this utility model have been illustrated above using specific examples. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solution and core ideas of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A controller, characterized in that, At least including: Main chip unit, voltage divider unit, and I / O cascade expansion unit for the type to be identified; The electrical signal input terminal of the voltage divider unit is electrically connected to the expansion I / O terminal of the main chip unit. The voltage divider unit includes at least two voltage divider branches, each with a different equivalent resistance value. One voltage divider branch is electrically connected to a type of I / O cascade expansion unit.

2. The controller according to claim 1, characterized in that, The main chip unit, the voltage divider unit, and the IO cascade expansion unit of the type to be identified are all disposed on the substrate, and the signal output port of one voltage divider branch is electrically connected to the signal receiving port of one IO cascade expansion unit of the type to be identified.

3. The controller according to claim 1, characterized in that, The main chip unit and the voltage divider unit are mounted on the substrate. The IO cascade expansion unit of the type to be identified is mounted on the expansion board. Different types of IO cascade expansion units correspond to different signal receiving ports on the expansion board. The signal output port of one voltage divider branch of the voltage divider unit is electrically connected to a corresponding signal receiving port on the expansion board.

4. The controller according to claim 3, characterized in that, The substrate and the expansion plate are stacked together.

5. The controller according to claim 4, characterized in that, The substrate and the expansion plate are stacked together via an interlocking structure.

6. The controller according to claim 5, characterized in that, The plug-in structure includes a pin and a socket. One of the pins or sockets serves as the signal output port of the voltage divider branch of the voltage divider unit and is disposed on the substrate, while the other serves as the signal receiving port and is disposed on the expansion board.

7. The controller according to claim 4, characterized in that, The base plate and the expansion plate bolt connection are stacked.

8. The controller according to any one of claims 1-7, characterized in that, The IO cascade expansion unit of the type to be identified has at least N expansion chips, where N is a positive integer greater than or equal to 2; The IO cascade expansion unit of the type to be identified is used to expand the signal input port of the main chip unit. The IO port to be expanded of the main chip unit is its signal input port. Then, the output signal port of each expansion chip is cascaded with the output signal port of the next expansion chip, and the output IO signal port of the first expansion chip is electrically connected to the signal input port of the main chip unit. The input IO signal ports of each expansion chip serve as the signal input ports expanded by the main chip unit.

9. The controller according to any one of claims 1-7, characterized in that, The IO cascade expansion unit of the type to be identified has at least N expansion chips, where N is a positive integer greater than or equal to 2; The IO cascade expansion unit of the type to be identified is used to expand the signal output port of the main chip unit. The IO port to be expanded of the main chip unit is its signal output port. Then, the input signal port of each expansion chip is cascaded with the input signal port of the next expansion chip. The input IO signal port of the first expansion chip is electrically connected to the signal output port of the main chip unit, and the output IO signal ports of each expansion chip serve as the signal output ports expanded by the main chip unit.

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