Override trip prevention protection device

Abstract

The utility model relates to the technical field of electric power, in particular to an override trip prevention protection device which comprises a device body, a plurality of interfaces are embedded in the upper side of the device, and the interfaces comprise an input interface and an output interface. A processor and a self-adaptive control module are arranged in the device, and pins of the processor, the self-adaptive control module and the input interface are mutually connected in pairs; the self-adaptive control module is connected with a pin of the output interface; the adaptive control module comprises a detection circuit and a timing circuit, the detection circuit is respectively connected with the pins of the input interface and the detection circuit, and the timing circuit is respectively connected with the processor and the pins of the output interface; the detection circuit detects whether the current received by the input interface exceeds a threshold value, and outputs a first control signal or a second control signal to the timing circuit according to a detection result; the technical problem that in an existing override trip prevention device, a shunt circuit breaker depends on a single trigger signal, so that the operation refusal risk is caused, and then the override trip phenomenon occurs is solved.

Description

Technical Field

[0001] This utility model relates to the field of power technology, and more specifically, to a protection device for preventing over-level tripping. Background Technology

[0002] In a multi-level protection power system, when a fault occurs in a branch circuit, if the circuit breaker of that branch circuit fails to trip in time to clear the fault, the upstream main circuit breaker will trip due to detecting overcurrent or short circuit. In this case, the fault that should have been handled by the branch circuit breaker is instead handled by the main circuit breaker, thus triggering a cascading trip. A cascading trip causes the main circuit breaker to disconnect the entire circuit, extending the power outage that was originally only in the faulty branch circuit to the entire power supply area, affecting other normally operating branches. This not only causes inconvenience to users in these areas but may also damage their production equipment, living facilities, and even cause safety accidents.

[0003] Existing anti-cascading tripping devices, while able to suppress cascading tripping to some extent through the differential coordination between branch circuits and the main circuit, still have significant drawbacks: First, branch circuit protection relies on a single trigger signal, which is prone to failure to operate due to electromagnetic interference or signal attenuation, forcing the main circuit to respond passively; Second, existing devices lack a fault classification and early warning mechanism, making it difficult for maintenance personnel to locate faulty branch circuits in a timely manner, thus delaying repair efficiency; Third, the backup protection logic of the main circuit is simple, often using a fixed delay threshold, which is difficult to adapt to branch circuit failure scenarios under complex operating conditions, and still carries the risk of false tripping or excessive disconnection.

[0004] Therefore, designing a device to prevent cascading trips is of great significance in order to improve the reliability of branch circuit operation, systematically block cascading trips, and reduce the probability of unnecessary power outages. Utility Model Content

[0005] The purpose of this application is to provide a protection device against over-level tripping, which solves the technical problem in existing protection devices against over-level tripping where the branch circuit breaker relies on a single trigger signal, leading to the risk of failure to operate and thus over-level tripping.

[0006] To solve the above-mentioned technical problems, the solution adopted in this application is as follows:

[0007] This utility model provides an anti-over-trip protection device, including a device body, with multiple interfaces embedded on the upper side of the device, including an input interface and an output interface; characterized in that: the device is internally equipped with a processor and an adaptive control module, and the pins of the processor, the adaptive control module, and the input interface are interconnected in pairs; the pins of the adaptive control module and the output interface are connected.

[0008] The adaptive control module includes a detection circuit and a timing circuit. The detection circuit is connected to the pins of the input interface and the timing circuit, respectively. The timing circuit is connected to the processor and the pins of the output interface, respectively.

[0009] The detection circuit detects whether the current received by the input interface exceeds the threshold, and outputs a first control signal or a second control signal to the timing circuit based on the detection result.

[0010] The timing circuit adjusts the delay response time of the circuit breaker according to the first control signal;

[0011] The timing circuit continuously sends a drive signal for tripping the circuit breaker to the output interface according to the second control signal; if the processor receives a feedback signal transmitted by the input interface before the timing circuit ends, the processor sends a termination signal to the timing circuit; if the processor does not receive a feedback signal, the timing circuit sends a drive signal for tripping the main circuit breaker to the output interface.

[0012] In some embodiments, the timing circuit includes a pulse generator and a counter. The output terminal of the pulse generator is connected to the counting terminal of the counter, and the reset terminal of the pulse generator is connected to the reset terminal of the counter. An input terminal for receiving a second control signal is provided here, which is connected to the detection circuit. The set terminal of the counter for receiving a first control signal is connected to the detection circuit, and the output terminal of the counter is connected to the pins of the processor and the output interface, respectively.

[0013] In some embodiments, the timing circuit further includes a latch, the detection circuit is connected to the set terminal of the counter via the latch, and the latch terminal of the latch is connected to an input terminal for receiving a second control signal.

[0014] In some embodiments, the timing circuit further includes an XNOR gate, the first input terminal of which is connected to the detection circuit, the output terminal of which is connected to the reset terminal of the pulse generator and the reset terminal of the counter, and the detection circuit transmits a second control signal through the XNOR gate; the second input terminal of which is used to receive a termination signal is connected to the processor.

[0015] In some embodiments, the detection circuit includes a first judgment circuit and a second judgment circuit, wherein the input terminal of the first judgment circuit, the input terminal of the second judgment circuit, and the pins of the input interface are connected, and the output terminal of the first judgment circuit and the output terminal of the second judgment circuit are respectively connected to the timing circuit.

[0016] The first judgment circuit outputs a first control signal, and the second judgment circuit outputs a second control signal.

[0017] In some embodiments, the first determining circuit includes a first operational amplifier, the second determining circuit includes a second operational amplifier, the input terminal of the first operational amplifier, the input terminal of the second operational amplifier, and the pins of the input interface are connected together, and the output terminal of the first operational amplifier and the output terminal of the second operational amplifier are respectively connected to the timing circuit.

[0018] In some embodiments, the first determination circuit further includes a delay circuit, and the output of the first operational amplifier is connected to the timing circuit through the delay circuit.

[0019] In some embodiments, the adaptive control module further includes an isolation circuit, and the detection circuit is connected to the timing circuit through the isolation circuit.

[0020] In some embodiments, the isolation circuit includes a transistor, an optocoupler, and a resistor. The base of the transistor is connected to the detection circuit, and the collector of the transistor is connected to the input terminal of the optocoupler and connected to a power supply through a resistor. The output terminal of the optocoupler is connected to a timing circuit.

[0021] In some embodiments, the processor includes a main control chip, the main control chip being an STM32F103RET6.

[0022] The technical solution of this application has at least the following advantages and beneficial effects:

[0023] 1. This utility model includes a device body with multiple interfaces embedded on its upper side, including input and output interfaces. The device internally houses a processor and an adaptive control module. The adaptive control module includes a detection circuit and a timing circuit. The detection circuit detects whether the current received by the input interface exceeds a threshold and outputs a first or second control signal to the timing circuit based on the detection result. The timing circuit adjusts the delay response time of the circuit breaker according to the first control signal. If the first judgment circuit determines that the current power consumption is high, it shortens the time for sending the control signal to control the circuit breaker to open. By shortening the opening time, overload situations can be prevented in time, avoiding more serious safety accidents such as line overheating and equipment damage, thereby effectively protecting the entire circuit system and connected equipment. If the first judgment circuit determines that the current power consumption is low, it appropriately extends the time for sending the control signal to control the circuit breaker to open, reducing unnecessary frequent opening operations and helping to maintain the overall stability of the circuit system.

[0024] 2. In this invention, the timing circuit continuously sends drive signals for tripping the branch circuit breakers to the output interface according to the second control signal. Before the timing circuit ends, if the processor receives a feedback signal transmitted from the input interface, the processor sends a termination signal to the timing circuit. If the processor does not receive a feedback signal, the timing circuit sends a drive signal for tripping the main circuit breaker to the output interface. By sending pulse signals to the branch circuit breakers multiple times, the reliability of the branch circuit breaker tripping is improved, the probability of branch circuit breaker failure to operate is significantly reduced, and the fault is ensured to be isolated by the branch circuit first. If multiple attempts are made to trip the branch circuit breaker but the current fault is not completely isolated, the early warning mechanism reminds the staff to pay attention and helps them quickly locate the faulty branch circuit, shortening the troubleshooting time and improving the efficiency of fault handling. The main circuit breaker only operates when the count reaches the highest value. As the last line of defense, this design ensures that the main circuit only intervenes when the branch circuit fails completely, avoiding cascading tripping due to the failure of the branch circuit to isolate the fault in time, thereby limiting the scope of the fault's impact. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0026] Figure 2 This is a bottom view of the present invention;

[0027] Figure 3 This is a top view of the present invention;

[0028] Figure 4 This is a signal flow diagram of the overall structure of this utility model;

[0029] Figure 5 This is a signal flow diagram of the adaptive control module of this utility model;

[0030] Figure 6 This is the detection circuit diagram for the adaptive control module;

[0031] Figure 7 The timing circuit diagram for the adaptive control module;

[0032] Figure 8 This is the isolation circuit diagram for the adaptive control module;

[0033] In the diagram: 1-Input interface, 2-Output interface, 3-Heat sink, 4-Power switch, 5-Grounding post. Detailed Implementation

[0034] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0035] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The terms "center," "upper," "lower," "inner," and "outer," indicating orientation or positional relationships based on the orientation or positional relationships shown in the figures, or the orientation or positional relationships commonly used when the product is in use, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on this application. It should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," and "connect" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Example 1

[0037] Please refer to Figures 1-5 This utility model provides an anti-over-level trip protection device, which is the same as the prior art. It includes a device body, and multiple interfaces are embedded on the upper side of the device, including an input interface 1 and an output interface 2.

[0038] In this embodiment, the device is provided with two input interfaces 1 and two output interfaces 2.

[0039] Furthermore, the first input interface 1 is connected to a current transmitter, and the current data detected by the current transmitter is transmitted to the device for detection through input interface 1; the second input interface 1 is connected to a branch circuit breaker, which is responsible for controlling the opening and closing of the branch circuit. Once the branch circuit breaker performs a tripping action, it will send a feedback signal to the device.

[0040] It should be noted that, in this embodiment, the current transmitter connected to the first input interface 1 is model SL-AI813-K45F. In this embodiment, the installation condition for the branch circuit breaker is that it can send a feedback signal to this device when the circuit breaker is closed; that is, any branch circuit breaker that meets this condition can be configured with this device.

[0041] Furthermore, the first output interface 2 is connected to the branch circuit breaker, and outputs a control signal to the branch circuit breaker to control the branch circuit breaker to perform a tripping action; the second output interface 2 is connected to the main circuit breaker, and outputs a control signal to the main circuit breaker to control the main circuit breaker to perform a tripping action.

[0042] In this embodiment, a positioning hole is provided on the back of the device, which allows the operator to fix the device to the rack in the electrical cabinet through the positioning hole, and the device is close to the circuit breaker in the electrical cabinet.

[0043] In this embodiment, a heat sink 3, a grounding post 5, and a switch 4 are also embedded on the lower side of the device. The switch 4 is used to control the power supply of the device, the grounding post 5 is used to ground the electronic components inside the device, and the heat sink 3 is used to help the device dissipate heat during operation and prevent performance degradation or damage caused by excessive temperature.

[0044] Unlike existing technologies, this device is equipped with a processor and an adaptive control module. The pins of the processor, the adaptive control module, and input interface 1 are connected to each other in pairs; the pins of the adaptive control module and output interface 2 are connected.

[0045] The adaptive control module includes a detection circuit and a timing circuit. The detection circuit is connected to the pins of input interface 1 and the timing circuit is connected to the processor and the pins of output interface 2.

[0046] The detection circuit detects whether the current received by input interface 1 exceeds the threshold, and outputs the first control signal or the second control signal to the timing circuit based on the detection result.

[0047] Furthermore, the detection circuit includes a first judgment circuit and a second judgment circuit. The input terminals of the first judgment circuit, the second judgment circuit, and the pins of the input interface 1 are connected together. The output terminals of the first judgment circuit and the second judgment circuit are respectively connected to the timing circuit.

[0048] The first judgment circuit outputs the first control signal, and the second judgment circuit outputs the second control signal.

[0049] Furthermore, the first judgment circuit is used to detect whether the current data received by input interface 1 exceeds the delay response time threshold, thereby determining the current power consumption of the branch circuit; the first judgment circuit outputs a first control signal to the timing circuit based on the detection result. The second judgment circuit is used to detect whether the current data received by input interface 1 is above the abnormal current threshold, that is, to determine whether the branch circuit has a short circuit, overload, or other fault; the second judgment circuit outputs a second control signal to the timing circuit based on the detection result.

[0050] It needs to be explained that when the first judgment circuit determines the current power consumption of the branch circuit:

[0051] If the first judgment circuit determines that the current power consumption is large, it shortens the time for sending control signals to control the circuit breaker to trip. This is because a large power consumption indicates that the circuit is in a dangerous early stage of high load or even close to overload, and it is necessary to quickly disconnect the circuit. By shortening the tripping time, the overload situation can be prevented in time, avoiding more serious safety accidents such as line overheating and equipment damage, thereby effectively protecting the entire circuit system and the connected equipment.

[0052] If the first judgment circuit determines that the current power consumption is low, it will appropriately extend the time for sending control signals to control the circuit breaker to open. This is because when the power consumption is low, the circuit system is relatively stable. At this time, appropriately extending the opening time can reduce unnecessary frequent opening operations, which helps to maintain the overall stability of the circuit system.

[0053] It should be explained that, under conditions of low power consumption, the appropriately extended tripping time is within the normal response time range of the circuit breaker tripping.

[0054] Furthermore, the first judgment circuit includes a first operational amplifier, the second judgment circuit includes a second operational amplifier, the input terminals of the first operational amplifier and the second operational amplifier are connected to the pins of input interface 1, and the output terminals of the first operational amplifier and the second operational amplifier are respectively connected to the timing circuit.

[0055] In this embodiment, the first judgment circuit further includes a delay circuit, and the output of the first operational amplifier is connected to the timing circuit through the delay circuit. The function of the delay circuit is that if the current data is abnormal, the second judgment circuit will prioritize transmitting a control signal to the timing circuit to ensure the normal operation of the timing circuit, and prevent the control signal issued by the first judgment circuit from changing the response time of the circuit breaker opening while the timing circuit is working, thereby causing the timing circuit to have timing errors.

[0056] Furthermore, the detection circuit includes a first operational amplifier U1, a second operational amplifier U2, resistors R1, R2, R3, R4, R5, R6, and R7, and ordinary capacitors C1, C2, and C3.

[0057] The first judgment circuit includes a first operational amplifier U1, resistors R1, R2, R3, and R7, and ordinary capacitors C1 and C; the delay circuit includes resistor R7 and capacitor C3; the second judgment circuit includes a second operational amplifier U2, resistors R4, R5, and R6, and ordinary capacitor C2.

[0058] Specifically, such as Figure 6 As shown, one end of resistor R1 is connected to pin 2 of the first operational amplifier U1 and is connected to the power supply; the other end of resistor R1, one end of resistor R3, and pin 3 of the first operational amplifier U1 are connected together; one end of resistor R2 is connected to one end of resistor R5 and is used as the T_IN input terminal; the other end of resistor R2 is connected to pin 1 of the first operational amplifier U1 and one end of ordinary capacitor C1; pin 4 of the first operational amplifier U1 is connected to one end of resistor R7; the other end of resistor R7 is connected to one end of capacitor C3 and is used as the T_OUT output terminal; the other end of resistor R5... One end of the second operational amplifier U2 is connected to pin 1 and one end of the ordinary capacitor C2. Pin 2 of the second operational amplifier U2 is connected to one end of the resistor R6 and connected to the power supply. The other end of the resistor R6, one end of the resistor R4, and pin 3 of the second operational amplifier U2 are connected. Pin 4 of the second operational amplifier U2 is set as the P_OUT output terminal. The other end of the resistor R3, the other end of the resistor R4, the other end of the ordinary capacitor C1, the other end of the ordinary capacitor C2, pin 5 of the first operational amplifier U1, pin 5 of the second operational amplifier U2, and the other end of the capacitor C3 are connected to ground.

[0059] It should be noted that both the first operational amplifier U1 and the second operational amplifier U2 are model LMV321.

[0060] It should be noted that the T_IN input terminal is connected to the pin of the first input interface 1, and the T_OUT and P_OUT output terminals are respectively connected to the timing circuit.

[0061] In this invention, the timing circuit adjusts the delay response time of the circuit breaker according to the first control signal;

[0062] In this invention, the timing circuit continuously sends a drive signal for tripping the circuit breaker to the output interface 2 according to the second control signal; before the timing circuit ends, if the processor receives a feedback signal transmitted from the input interface 1, the processor sends a termination signal to the timing circuit; if the processor does not receive a feedback signal, the timing circuit sends a drive signal for tripping the main circuit breaker to the output interface 2.

[0063] Furthermore, the timing circuit includes a pulse generator and a counter. The output terminal of the pulse generator is connected to the counting terminal of the counter, and the reset terminal of the pulse generator is connected to the reset terminal of the counter. An input terminal for receiving a second control signal is also provided here, which is connected to the detection circuit. The set terminal of the counter for receiving a first control signal is connected to the detection circuit, and the output terminal of the counter is connected to the pins of the processor and the output interface 2, respectively.

[0064] Furthermore, the timing circuit also includes a latch. The detection circuit is connected to the set terminal of the counter via the latch, and the latch terminal of the latch is connected to the input terminal for receiving the second control signal. The function of the latch is to further prevent the control signal issued by the first judgment circuit from changing the response time of the circuit breaker opening while the timing circuit is operating, thereby causing timing errors in the timing circuit.

[0065] Furthermore, the timing circuit also includes an XNOR gate. The first input of the XNOR gate is connected to the detection circuit, and the output of the XNOR gate, the reset terminal of the pulse generator, and the reset terminal of the counter are connected. The detection circuit transmits a second control signal through the XNOR gate. The second input of the XNOR gate, used to receive a stop signal, is connected to the processor. The function of the XNOR gate is to receive the control signal transmitted by the second judgment circuit and start the timing function; if the processor sends a stop signal to the XNOR gate, the XNOR gate stops the timing function.

[0066] It should be noted that the XNOR gate is composed of an XOR gate and a NOT gate.

[0067] Furthermore, the timing circuit includes an XOR gate U3, a latch U4, a pulse generator U5, a counter U6, a NOT gate U7, a general-purpose capacitor C5, a polarized capacitor C4, transistors Q1 and Q2, and resistors R8, R9, R10, R11, R12, R13, and R14.

[0068] Specifically, such as Figure 7As shown, the first input terminal of XOR gate U3 is set as P_IN1, and the second input terminal of XOR gate U3 is set as P_IN2. Pin 3 of XOR gate U3 is grounded, and pin 5 is connected to the power supply. Pin 4 of XOR gate U3 is connected to pin 2 of NOT gate U7. Pin 4 of NOT gate U7, one end of resistor R8, the base of transistor Q2, and pin 1 of latch U4 are connected. Pin 5 of NOT gate U7 is connected to the power supply, pin 3 is grounded, and the other end of resistor R8 is connected to the power supply. Pins 2 and 6 of latch U4 are connected and grounded. Pin 3 of latch U4 is set as the T_IN input terminal. Pin 5 of latch U4, one end of resistor R11, and one end of resistor R12 are connected to the power supply. Pin 4 of latch U4 is connected to the base of transistor Q1. The collector of transistor Q1 is connected to the other end of resistor R12. The emitter of transistor Q1, one end of resistor R13, and pin 4 of counter U6 are connected. The emitter of transistor Q2 is connected to the other end of resistor R11. The collector of transistor Q2, pin 2 of counter U6, and pulse generator U... Pin 4 of pulse generator U5 is connected to one end of resistor R14; pin 3 of pulse generator U5 is connected to pin 2 of counter U6; pin 8 of pulse generator U5 is connected to one end of resistor R9 and is connected to the power supply; pin 7 of pulse generator U5, the other end of resistor R9, and one end of resistor R10 are connected; the other end of resistor R10, pin 2 of pulse generator U5, pin 6 of pulse generator U5, and the positive terminal of polarized capacitor C4 are connected; pin 5 of pulse generator U5 is connected to one end of ordinary capacitor C5; polarized capacitor C4... The cathode of the counter is connected to pin 1 of the pulse generator U5 and the other end of the capacitor C5 and grounded; pins 3, 5, 6, and 8 of the counter U6, as well as the other ends of resistors R13 and R14, are connected to ground; pins 7, 9, 10, and 16 of the counter U6 are connected to the power supply; pin 13 of the counter U6 is set as the AL_OUT1 output terminal; pin 11 of the counter U6 is set as the W_OUT output terminal; and pin 15 of the counter U6 is set as the AL_OUT2 output terminal.

[0069] It should be noted that transistor Q1 is NPN type and transistor Q2 is PNP type; the pulse generator U5 is model NE555DR; the counter U6 is model 74LS161; the XOR gate U3 is model SN74LVC1G86DCKR; the latch U4 is model SN74LVC1G373DCKR; and the NOT gate U7 is model SN74LVC1G14DBVR.

[0070] It should be noted that the P_IN1 input terminal is connected to the P_OUT output terminal, the P_IN2 input terminal is connected to the processor's I / O port, and the T_IN input terminal is connected to the T_OUT output terminal; the AL_OUT1 output terminal is connected to the pin of the first output interface 2, the W_OUT output terminal is connected to the processor's I / O port, and the AL_OUT2 output terminal is connected to the pin of the second output interface 2.

[0071] It needs to be explained that when the timing circuit is working, the pulse generator continuously sends pulse signals to the counter, and the counter starts counting;

[0072] When counter U6 counts to 2, 3, 6, 7, 10, 11, 14, 15 (binary representation: 0010, 0011, 0110, 0111, 1010, 1011, 1110, 1111), pin 13 of counter U6, i.e., the AL_OUT1 output terminal, outputs a high-level pulse signal. The high-level pulse signal is output to the branch circuit breaker through the first output interface 2. At this time, the branch circuit breaker continuously receives drive signals to complete the tripping operation. The advantage of this design is that, through the repeated triggering mechanism, even if some pulse signals are interfered with, subsequent pulse signals can still be effectively transmitted to the branch circuit breaker, significantly reducing the probability of the branch circuit breaker refusing to operate.

[0073] When counter U6 counts to 8, 9, 10, 11, 12, 13, 14, 15 (represented in binary as 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111), pin 11 of counter U6, i.e., the W_OUT output terminal, outputs a high-level pulse signal to the processor. After receiving this signal, the processor transmits an alert signal to the monitoring center to remind the staff to pay attention to the branch circuit fault, helping the staff to quickly identify the branch circuit where the fault occurred and improve the efficiency of fault handling.

[0074] When counter U6 counts to 15 (represented in binary as 1111), pin 15 of counter U6, i.e., the AL_OUT2 output terminal, outputs a high-level pulse signal. The high-level pulse signal is output to the main circuit breaker through the second output interface 2. At this time, the main circuit breaker receives the drive signal and completes the tripping operation to prevent the continuous fault in the branch circuit from spreading to the entire circuit system.

[0075] In this invention, the incrementing process of counter U6 from 0 to 15 simulates the characteristics of time-delay protection. The branch circuits are triggered multiple times at the early counting points, while the main circuit operates at the final counting point, forming a time ladder to ensure that the branch circuits respond first, while the main circuit only serves as a backup, which conforms to the selective principle of relay protection.

[0076] The advantage of this design is that:

[0077] 1. By sending pulse signals to the branch circuit breaker multiple times in a priority manner, the reliability of the branch circuit breaker tripping is improved, the probability of branch circuit breaker failure to operate is significantly reduced, and the fault is ensured to be isolated by the branch circuit first.

[0078] 2. If multiple attempts are made to trip the branch circuit breaker but the current fault is not completely isolated, the early warning mechanism will alert the staff and help them quickly locate the faulty branch, shorten the troubleshooting time, and improve the efficiency of fault handling.

[0079] 3. The main circuit breaker only operates when the count reaches the highest value. As the last line of defense, this design ensures that the main circuit breaker only intervenes when a branch circuit completely fails, avoiding cascading tripping due to the failure of the branch circuit to disconnect the fault in time, thereby limiting the scope of the fault's impact.

[0080] In this embodiment, the adaptive control module further includes an isolation circuit, and the detection circuit is connected to the timing circuit through the isolation circuit.

[0081] Furthermore, the isolation circuit includes a transistor, an optocoupler, and a resistor. The base of the transistor is connected to the detection circuit, and the collector of the transistor is connected to the input terminal of the optocoupler and connected to the power supply through the resistor. The output terminal of the optocoupler is connected to the timing circuit.

[0082] Furthermore, the isolation circuit includes transistor Q3, optocoupler U8, and resistors R15, R16, and R17;

[0083] Specifically, such as Figure 8 As shown, the base of transistor Q3 is set as the Q_IN input terminal. The collector of transistor Q3, pin 2 of optocoupler U5, and one end of resistor R15 are connected together. The other end of resistor R15 is connected to one end of resistor R16 and connected to the power supply. The other end of resistor R16 is connected to pin 1 of optocoupler U8. Pin 4 of optocoupler U8 is connected to one end of resistor R17, and the Q_OUT output terminal is set here. The other end of resistor R17 is connected to the power supply. Pin 3 of optocoupler U8 is connected to the emitter of transistor Q3 and grounded.

[0084] It should be noted that transistor Q3 is an NPN type; the optocoupler model is PC357C;

[0085] In this embodiment, two isolation circuits are provided. The Q_IN input and Q_OUT output of the first isolation circuit are connected to the T_OUT output and T_IN input, respectively. The Q_IN input and Q_OUT output of the second isolation circuit are connected to the P_OUT output and P_IN1 input, respectively.

[0086] To facilitate understanding, the working principle of this device is explained below:

[0087] When the device starts working, the current sensor transmits current data to the detection circuit through the first input interface 1, and the first judgment circuit and the second judgment circuit in the detection circuit start to detect and judge.

[0088] If the first judgment circuit determines that the power consumption of the branch circuit is large, it sends a high level to latch U4. Latch U4 outputs a high level to the base of transistor Q1, turning on transistor Q1. At this time, counter U6 shortens the response time. Until the first judgment circuit determines that the power consumption of the branch circuit is small, the first judgment circuit sends a low level to latch U4. Latch U4 outputs a low level to the base of transistor Q1, turning off transistor Q1. At this time, counter U6 extends the response time.

[0089] If the second judgment circuit determines that there is an overload, short circuit, or other current fault in the branch circuit, the second judgment circuit outputs a high level to the XOR gate U3, the XOR gate U3 outputs a high level to the NOT gate U7, and the NOT gate U7 outputs a low level to the latch U4 and the transistor Q2 respectively. At this time, the latch U4 is locked and holds the original output value, the transistor Q2 is turned on, the pulse generator U5 starts sending pulse signals to the counter U6, and the counter U6 starts counting; the counter U6 continuously outputs high-level pulse signals to the branch circuit breaker.

[0090] If the circuit breaker performs a tripping operation within the preset time, the processor receives the termination signal transmitted by the circuit breaker and transmits the termination signal to the XOR gate U3. The XOR gate U3 sends a low level to the NOT gate U7, and the NOT gate U7 outputs a high level to the transistor Q2. The transistor Q2 is turned off, the timer stops and is reset.

[0091] If the branch circuit breaker does not perform the tripping operation within the preset time, counter U6 sends a control signal to the processor, and the processor transmits an alarm signal to the monitoring center based on this signal; after the counting is completed, counter U6 sends a control signal to the main circuit breaker.

[0092] In this embodiment, the processor includes a main control chip, which is an STM32F103RET6.

[0093] This embodiment also includes a communication chip connected to the main control chip. After receiving the control signal transmitted by the timing circuit, the main control chip transmits an alert signal to the monitoring center through the communication chip to remind staff of the branch circuit malfunction. The communication chip is a SIM300C.

[0094] It should be noted that the connection between the main control chip and the communication chip is existing technology, which will not be described in detail here.

[0095] It should be noted that all of the above electronic components can be purchased in domestic and international markets.

[0096] The various embodiments of this utility model have now been described in detail. To avoid obscuring the concept of this utility model, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solution of this utility model based on the above description. The scope of this utility model is defined by the appended claims.

Claims

1. A protection device for preventing over-level tripping, comprising a device body, wherein multiple interfaces are embedded on the upper side of the device, the interfaces including an input interface (1) and an output interface (2); characterized in that: The device is equipped with a processor and an adaptive control module. The pins of the processor, the adaptive control module, and the input interface (1) are connected to each other in pairs. The pins of the adaptive control module and the output interface (2) are connected. The adaptive control module includes a detection circuit and a timing circuit. The detection circuit is connected to the pins of the input interface (1) and the detection circuit, respectively. The timing circuit is connected to the processor and the pins of the output interface (2), respectively. The detection circuit detects whether the current received by the input interface (1) exceeds the threshold, and outputs a first control signal or a second control signal to the timing circuit according to the detection result; The timing circuit adjusts the delay response time of the circuit breaker according to the first control signal; The timing circuit continuously sends a drive signal for tripping the circuit breaker to the output interface (2) according to the second control signal; before the timing circuit ends, if the processor receives a feedback signal transmitted by the input interface (1), the processor sends a termination signal to the timing circuit; if the processor does not receive a feedback signal, the timing circuit sends a drive signal for tripping the main circuit breaker to the output interface (2).

2. The anti-over-trip protection device according to claim 1, characterized in that, The timing circuit includes a pulse generator and a counter. The output terminal of the pulse generator is connected to the counting terminal of the counter, and the reset terminal of the pulse generator is connected to the reset terminal of the counter. An input terminal for receiving a second control signal is provided here, which is connected to the detection circuit. The set terminal of the counter for receiving a first control signal is connected to the detection circuit. The output terminal of the counter is connected to the pins of the processor and the output interface (2).

3. The anti-over-trip protection device according to claim 2, characterized in that, The timing circuit also includes a latch, and the detection circuit is connected to the set terminal of the counter through the latch. The latch terminal of the latch is connected to the input terminal for receiving a second control signal.

4. The anti-over-trip protection device according to claim 2, characterized in that, The timing circuit also includes an XNOR gate, the first input of which is connected to the detection circuit, and the output of which is connected to the reset terminal of the pulse generator and the reset terminal of the counter. The detection circuit transmits a second control signal through the XNOR gate. The second input of the XNOR gate, which is used to receive a termination signal, is connected to the processor.

5. The anti-over-trip protection device according to claim 1, characterized in that, The detection circuit includes a first judgment circuit and a second judgment circuit. The input terminal of the first judgment circuit, the input terminal of the second judgment circuit, and the pin of the input interface (1) are connected together. The output terminal of the first judgment circuit and the output terminal of the second judgment circuit are respectively connected to the timing circuit. The first judgment circuit outputs a first control signal, and the second judgment circuit outputs a second control signal.

6. The anti-over-trip protection device according to claim 5, characterized in that, The first judgment circuit includes a first operational amplifier, and the second judgment circuit includes a second operational amplifier. The input terminals of the first operational amplifier, the second operational amplifier, and the pins of the input interface (1) are connected together. The output terminals of the first operational amplifier and the second operational amplifier are respectively connected to the timing circuit.

7. The anti-over-trip protection device according to claim 6, characterized in that, The first judgment circuit also includes a delay circuit, and the output of the first operational amplifier is connected to the timing circuit through the delay circuit.

8. The anti-over-trip protection device according to claim 1, characterized in that, The adaptive control module also includes an isolation circuit, and the detection circuit is connected to the timing circuit through the isolation circuit.

9. The anti-overcurrent tripping protection device according to claim 8, characterized in that, The isolation circuit includes a transistor, an optocoupler, and a resistor. The base of the transistor is connected to the detection circuit, and the collector of the transistor is connected to the input terminal of the optocoupler and connected to the power supply through the resistor. The output terminal of the optocoupler is connected to the timing circuit.

10. The anti-over-trip protection device according to claim 1, characterized in that, The processor includes a main control chip, which is an STM32F103RET6.

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