Semiconductor device and system
By integrating a resistance temperature detector into a HEMT device and using the resistivity change of a metal field plate for temperature measurement, the problem of HEMT device performance degradation at high temperatures is solved, achieving simplified temperature sensor integration and accurate temperature measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2026-03-20
AI Technical Summary
Existing HEMT devices suffer from reduced performance and reliability at high temperatures. Existing integrated temperature sensor solutions are complex or cannot be closely integrated into the channel region, affecting device performance.
In HEMT devices, a resistance temperature detector is integrated. By laterally arranging a metal field plate next to the gate region, the temperature is measured by utilizing the change in resistivity of the metal field plate with temperature. This is combined with a control circuit system for voltage sensing.
This technology enables precise measurement of the channel temperature of HEMT devices at high temperatures, simplifying the manufacturing process and reducing the impact on device performance.
Smart Images
Figure CN224022140U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device, such as a high electron mobility transistor (HEMT) or a side-diffused metal-oxide-semiconductor (LDMOS) device, including a field plate region that can operate as a temperature sensor; to a system including the semiconductor device; and to a method of operating the semiconductor device as a temperature sensor. Background Technology
[0002] HEMT devices, also known as heterostructure field-effect transistors (HFETs), are gaining widespread adoption due to their potential to operate at high voltages and high breakdown voltages.
[0003] In each HEMT device, the semiconductor heterostructure allows for the electronically controlled generation of a so-called two-dimensional electron gas (2DEG), which forms the channel region of the HEMT device. Furthermore, each HEMT device includes a gate region; the HEMT device channel is modulated by a voltage across the gate region.
[0004] For example, Figure 1 The HEMT device 1 is shown, which includes a semiconductor body 2, which is formed herein by a first layer 4 and a second layer 6, also referred to below as a lower layer 4 and an upper layer 6.
[0005] The lower layer 4 is formed of a first semiconductor material (such as, for example, a first semiconductor alloy of elements from Group III and Group V of the periodic table); for example, the lower layer 4 may be formed of gallium nitride (GaN).
[0006] The upper layer 6 is located above and in direct contact with the lower layer 4, and is formed of a second semiconductor material (such as a second semiconductor alloy, different from the first semiconductor alloy, for example, elements of Group III-V of the periodic table). For example, the upper layer 6 may be formed of aluminum gallium nitride (AlGaN). The lower layer 4 and the upper layer 6 are, for example, N-type. Although not shown, the semiconductor body 2 also includes a substrate, typically silicon or silicon carbide, on which the lower layer 4 is formed.
[0007] HEMT device 1 also includes source metallization 20 and drain metallization 22 arranged at a distance from each other above upper layer 6.
[0008] A first insulating layer 8 (e.g., made of silicon nitride) extends over the upper layer 6 and a portion of the lower portions 20A, 22A of the source metallization 20 and the drain metallization 22. Furthermore, the first insulating layer 8 has an opening 11 disposed at an intermediate position between the lower portions 20A, 22A of the source metallization 20 and the drain metallization 22.
[0009] A gate region 10, made of a conductive material, extends partially within the opening 11 (having a lower gate portion 10A) and partially over the first insulating layer 8 (having an upper gate portion 10B). The gate region 10 is formed by a stack of materials such as nickel (Ni), gold (Au), platinum (Pt), and palladium (Pd), wherein the nickel layer is in direct contact with the upper layer 6 and forms a Schottky-type metal-semiconductor junction therewith, which is a rectifier junction. The stack of materials mentioned above may also include aluminum.
[0010] The second insulating layer 12 (e.g., made of silicon nitride) extends over the first insulating layer 8 and surrounds the upper gate portion 10A. In practice, the second insulating layer 12 and the first insulating layer 8 form an insulating structure 13 that seals the gate region 10.
[0011] The field plate region 14 extends over the second insulating layer 12, partially vertically covering the gate region 10 and partially laterally offset toward the drain metallization region 22. The field plate region 14 (e.g., made of aluminum) is designed to modify the existing electric field during operation of the HEMT device 1. The field plate region 14 is electrically coupled to the source metallization 20 in a manner not shown.
[0012] The passivation layer 16 (e.g., made of silicon oxide) surrounds the upper portions 20B and 22B of the source metallization 20 and the drain metallization 22, as well as the field plate region 14, and covers the entire structure.
[0013] Power devices made of GaN are allowed to operate normally at high temperatures (e.g., base temperatures ranging from -50°C to 150°C, and channel temperatures up to 250°C). However, at such high temperatures, the performance and reliability of HEMT devices degrade. Therefore, during the operation of GaN-based HEMTs, it is essential to be able to measure / estimate their channel temperature. Integrated temperature sensors can meet this requirement. Ideally, the sensor should be located within the same die (integrated sensor) and close to the active region (channel). Utility Model Content
[0014] Several solutions for implementing integrated sensors in GaN-based HEMTs have been proposed, including: 2DEG-based resistors, IC circuits utilizing the temperature-dependent characteristics of Schottky barrier diodes, enhancement / depletion-mode HEMTs, side-effect rectifiers; non-gated HEMTs; Schottky gate-diode HEMTs; resistance temperature sensors (using Pt or Ni materials); and resistance linear temperature sensors on interconnect metallization.
[0015] All the solutions mentioned above have drawbacks. For example, 2DEG-based resistors have non-linear temperature dependence and cannot be formed close to the transistor channel; IC circuits require particularly complex GaN HEMT technology, which demands very complex manufacturing processes; non-gated HEMTs require self-organized structures and cannot be formed close to the main transistor channel; Schottky gate-diode HEMTs are sensitive to trapping and biasing effects and require appropriate readout strategies to avoid interfering with transistor operation; resistance temperature sensors require appropriate metal layers and additional masks for fabrication; resistance linear temperature sensors on interconnect metallization require dedicated areas, which affects packaging and disrupts the periodicity of the structure.
[0016] The purpose of this disclosure is to provide a HEMT device with an integrated temperature sensor that overcomes the problems mentioned above.
[0017] According to this disclosure, a semiconductor device, a system including the semiconductor device, and a method of operating the semiconductor device are provided.
[0018] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a semiconductor body having a semiconductor heterostructure; a gate region made of a conductive material, located on and in contact with the semiconductor body; a first insulating layer extending over the semiconductor body laterally toward the conductive gate region, the first insulating layer including a first portion and a second portion, wherein the second portion is located below the first portion; a second insulating layer extending over the first insulating layer and the gate region; a first field plate made of a metallic material extending between the first and second insulating layers and laterally spaced from the gate region, the first field plate having a strip-like shape in a top plan view, its main extension along a first direction, the strip-like shape having a first end and a second end opposite to each other along the first direction; a first conductive pad electrically contacting the first field plate at a first end via a first connection region; a second conductive pad electrically contacting the first field plate at a second end via a second connection region; and a third conductive pad electrically contacting the first field plate at a second end via a third connection region.
[0019] In one example, the first field plate is made of pure metal.
[0020] In one example, the pure metal is one of platinum, nickel, copper, and aluminum.
[0021] In one example, the first connection region is closer to the first end than to the second end; and both the second and third connection regions are closer to the second end than to the first end.
[0022] In one example, a first connecting region is coupled to a first field plate at a first intersection point, a second connecting region is coupled to the first field plate at a second intersection point, and a third connecting region is coupled to the first field plate at a third intersection point. The length of the first field plate along a first direction from the first intersection point to at least one of the second and third intersection points is in the range of 25 μm to 1.5 mm.
[0023] In one example, the device is either a HEMT or an LDMOS transistor.
[0024] In one example, the semiconductor body includes at least a first semiconductor layer and a second semiconductor layer, the first semiconductor layer including aluminum gallium nitride, the second semiconductor layer including one of gallium nitride and gallium arsenide, and wherein the second semiconductor layer is adjacent to the first insulating layer.
[0025] In one example, a first field plate, a first conductive pad, a second conductive pad, and a third conductive pad, as well as a first connection region, a second connection region, and a third connection region, form a resistance temperature detector; the first conductive pad, the second conductive pad, and the third conductive pad are terminals of the resistance temperature detector; and the first field plate has a temperature-dependent resistivity.
[0026] In one example, the device also includes a second field plate made of a conductive material that extends over the second insulating layer and covers the first field plate.
[0027] In one example, the second field plate is located on the second portion of the first insulating layer.
[0028] In one example, the second field plate covers the gate region.
[0029] In one example, the first field plate has a first width along a second direction that is transverse to the first direction, and the second field plate has a second width along the second direction, wherein the second width is greater than or equal to the first width.
[0030] In one example, the device also includes a drain contact region and a source contact region made of conductive material, extending over and electrically contacting the semiconductor body, passing through a first insulating layer and a second insulating layer on opposite sides of the gate region, wherein a first field plate extends between the gate region and the drain contact region.
[0031] In one example, the first conductive pad is electrically coupled to the source contact region.
[0032] In one example, the device also includes a second field plate extending over the second insulating layer, which covers the first field plate in a top plan view and partially covers the first field plate in a cross-sectional view transverse to the top plan view.
[0033] In one example, the second field plate is electrically coupled to the source contact region.
[0034] According to another aspect of this disclosure, a system is provided, comprising: a device including: a gate region; a first insulating layer including a first portion and a second portion, wherein the second portion is located below the first portion; a second insulating layer extending over the first insulating layer and the gate region; a first field plate extending between the first insulating layer and the second insulating layer, the first field plate being positioned on the second portion of the first insulating layer and laterally spaced from the gate region; a first conductive pad contacting the first field plate; and a second conductive pad electrically connected to the first field plate. The system includes: a contact; and a third conductive pad, which is in electrical contact with the first field plate; a control circuit system having: a current generator coupled to the first conductive pad and to one of the second and third conductive pads, operable to allow current to flow through the first field plate between the first conductive pad and one of the second and third conductive pads; and a voltage sensor coupled to the first conductive pad and to the other of the second and third conductive pads, operable to sense a voltage drop across the first field plate when current flows through it.
[0035] In one example, the system also includes a processor configured to correlate the voltage drop value with a corresponding temperature value. Attached Figure Description
[0036] To better understand this disclosure, some embodiments of the disclosure will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:
[0037] Figure 1 A cross-section of a HEMT device known in the art is schematically shown;
[0038] Figure 2 A cross-section of an embodiment of the HEMT device according to an embodiment is schematically shown;
[0039] Figure 3 A cross-section of an embodiment of a HEMT device according to another embodiment is schematically shown;
[0040] Figures 4A-4C In the subsequent manufacturing steps according to the embodiment Figure 2 A top view of a portion of the HEMT device;
[0041] Figure 5A and Figure 5B According to embodiments of this disclosure Figure 2 A top view of a portion of a HEMT device; and
[0042] Figure 6 Includes embodiments according to this disclosure Figure 2 The system of HEMT devices. Detailed Implementation
[0043] Figure 2 An embodiment of a HEMT device is shown, generally identified by reference numeral 50. Figure 2 It is a schematic representation of the lateral cross-sectional view of a HEMT device in a Cartesian system with mutually orthogonal X, Y, and Z axes.
[0044] HEMT device 50 includes a semiconductor body 52, which is formed of a lower layer 56 (e.g., made of gallium nitride (GaN)) and an upper layer 54 (e.g., made of aluminum gallium nitride (AlGaN)). The upper layer 54 forms the surface 52a of the semiconductor body 52. The semiconductor body 52 may also include a silicon substrate, and / or the upper layer 54 may be multilayered, including AlGaN layers with different percentages of aluminum (e.g., one AlGaN layer has 20% aluminum and another AlGaN layer has 40% aluminum).
[0045] Source metallization 70 and drain metallization 72 extend above body 52 at a distance from each other. Source metallization 70 and drain metallization 72 include lower portions 70a, 72a and upper portions 70b, 72b, and are made of, for example, aluminum. Source metallization 70 and drain metallization 72 form source electrodes and drain electrodes, and are electrically coupled to corresponding source terminals S and drain terminals D.
[0046] A first insulating layer 58 (e.g., made of silicon nitride) extends over the upper layer 54 and over a portion of the lower portions 70a, 72a of the source metallization 70 and drain metallization 72. The first insulating layer 58 is a conformal layer extending along the top surface of the lower portions 70a, 72a. Recesses are formed in the lower portions 70a, 72a having the first insulating layer 58 on the top and side surfaces of the lower portions 70a, 72a, in which the gate portion 60b and the first field plate region 84 are positioned. The bottom surface of each of the gate portion 60b and the first field plate region 84 is located below the top surface of the lower portions 70a, 72a.
[0047] HEMT device 50 also includes a gate region 60 having a lower gate portion 60a and an upper gate portion 60b. The gate region 60 may be formed of one and only one conductive material, or it may be a stack of materials (e.g., nickel (Ni), aluminum (Al), and tungsten nitride (WN) or tantalum nitride (TaN)).
[0048] The first insulating layer 58 has an opening 61 that accommodates the lower gate portion 60a. The gate region 60 is electrically coupled to the gate terminal G.
[0049] HEMT device 50 has a first field plate region 84 and a second field plate region 85 made of a conductive material (such as a metal, for example, aluminum, platinum, nickel or copper).
[0050] The first field plate region 84 extends over the insulating layer 58 and is coated on the sides and top by a second insulating layer 62. The second insulating layer 62 (e.g., made of silicon nitride) extends over the first insulating layer 58 and surrounds the upper gate portion 60a and the first field plate region 84 on the top and sides. In practice, the second insulating layer 62, together with the first insulating layer 58, forms an insulating structure 63 that seals the gate region 60 and the first field plate region 84.
[0051] The passivation layer 66 (e.g., formed of silicon oxide or silicon nitride) surrounds the upper portions 70b, 72b of the source metallization 70 and the drain metallization 72 and covers the entire previously disclosed structure.
[0052] In the illustrated embodiment, the first field plate region 84 is arranged closer to the gate region 60 than to the drain metallization 72. For example, in the direction of the axis X adjacent to the source metallization 70, gate region 60, first field plate region 84, and drain metallization 72, the first field plate region 84 may have a width L1 selected according to the breakdown voltage, for example, between 0.1 and 3 μm, such as 1 μm, and may be arranged at a distance d from the gate region 60 at a distance of 0.1 to 3 μm, such as 1 μm (the distance d is approximately calculated from the edge of the upper gate portion 60b facing the first field plate region 84).
[0053] The first field plate region 84 can be made of the same conductive material as the upper gate portion 60b, in particular of the same metal layer, and manufactured using the same manufacturing steps.
[0054] The second field plate region 85 extends above the second insulating layer 62, thereby vertically covering (relative to the Z-axis) above the first field plate region 84 and being covered by the passivation layer 66. The second field plate region 85 has a width L2 that is at least equal to, but generally greater than, the width L1 of the first field plate region 84. For example, the width L2 of the second field plate region 85 may be between 0.1 and 5 μm.
[0055] Field plate regions 84 and 85 are electrically coupled to source metallization 70. In particular, the second field plate region 85 may be formed together with the upper portions 70b and 72b of source and drain regions 70 and 72 and use the same metal layer.
[0056] Field plate regions 84 and 85 have the effect of modifying the existing electric field, especially making it more uniform during the operation of HEMT device 50. Furthermore, the presence of the first field plate region 84 allows the gain of HEMT device 50 to increase relative to HEMT devices without a corresponding field plate. In fact, with an increased drain voltage, the first field plate region 84, acting as a shield between gate region 60 and drain metallization 72, has the effect of reducing the gate-drain capacitance, which is inversely proportional to the gain.
[0057] In one embodiment, the lower gate portion 60a and the upper gate portion 60b may be formed by a single deposited (e.g., "sputtered") metal layer or a single evaporated layer, or by a stack of individually deposited layers. In the latter case, the first field plate region 84 may be formed by one of the layers of the gate region 60.
[0058] It is clear that references are available. Figure 2 The HEMT device described and illustrated may be modified and varied. For example, the second field plate 85 and the first field plate 84 may be connected to the source metallization 70 in various ways; the first field plate 84 and the gate region 60 may be positioned relative to the insulating layer 58 in different ways; and the gate region 60 may be defined in different ways.
[0059] The second field plate 85 can be connected to the source metallization 70 through a connection region extending over the active region (where the two-dimensional electron gas - 2DEG - forms the channel region of the HEMT device and conducts current) or the non-active region surrounding the active region.
[0060] For example, Figure 3 An embodiment is shown, wherein Figure 2 The HEMT device 50 has a second field plate 85 connected to the source metallization 70 via a connection portion formed in a third metal layer. This third metal layer also forms the upper portion 70b of the source metallization 70, the upper portion 72b of the drain metallization 72, and the second field plate region 85, thus defined in the same etching step. Specifically, in Figure 3 In the middle, the bias metal portion 88 extends on the second insulating layer 62 between the upper portion 70b of the source metallization 70 and the second field plate region 85 and forms a single region with them.
[0061] According to different embodiments, the second field plate 85 is connected to the source metallization 70 through a connection region extending over the non-active region of the HEMT device 50.
[0062] The HEMT device 150 is intended to include a plurality of basic cells, each basic cell having at least one source metallization 70, at least one drain metallization 72, at least one first field plate 84 and at least one second field plate 85, which extend as fingers along the Y-axis.
[0063] Now for reference Figures 4A-4C .
[0064] The first field plate 84 can be connected to the source metallization 70 through a connection region extending over the non-active region 91 or through the second field plate 85.
[0065] The active region 90 accommodates the high-mobility conduction electrons of the 2-DEG transistor and is surrounded by the passive region 91, thus preventing it from participating in electrical conduction when the transistor is ON. The passive region 91 is typically doped to prevent current from flowing through when the HEMT device 50 is turned off. Line 93 indicates the boundary of the active region 90.
[0066] In one example, the first field plate 84 can be connected to the source metallization 70, such as Figures 4A-4C These figures, as shown in the text, illustrate... Figure 2 The basic cell structure of the HEMT device 50 in three intermediate manufacturing steps (connection on the non-active region 91).
[0067] HEMT device 50 may include a plurality of basic cells, each basic cell having at least one source metallization 70, at least one drain metallization 72, at least one first field plate 84 and at least one second field plate 85, which extend as fingers along the Y-axis.
[0068] Figure 4A This shows a portion of the intermediate structure of the HEMT device 50 after the formation of the lower portions 70a and 72a of the source metallization 70 and the drain metallization 72, and after the formation and definition of the insulating layer 58.
[0069] exist Figure 4A In the middle, the lower portions 70a and 72a of the source metallization 70 and the drain metallization 72 mainly extend on the active region 90 and have end portions 70a1 and 72a1 extending on the non-active region 91.
[0070] Figure 4B The same portion of the intermediate structure of the HEMT device 50 after the deposition and definition of the metal layers is shown, forming a gate region 60, a first field plate 84, and a first connection region 96. The first connection region 96 extends at a first end of the strip forming the first field plate 84. Specifically, the connection region 96 is integral with and a continuation of the first field plate 84. The connection region 96 extends from the first end of the first field plate 84 onto the non-active region 91 and electrically connects the first field plate 84 to the amplification portion 96a. The amplification portion 96a is made of a conductive material; in one embodiment, the amplification portion 96a is integral with and a continuation of the connection region 96.
[0071] Another embodiment envisions depositing and defining a second insulating layer 62 and depositing and defining a third metal layer 98 to form the upper portions 70b and 72b of the source metallization 70 and drain metallization 72, and the second field plate region 85. Thus, Figure 4C The deposition and definition of the second insulating layer 62 are shown. Figure 4C (not visible in the middle) and after the deposition and definition of the third metal layer 98 Figure 4A and Figure 4B The same parts are used to form the upper portions 70b and 72b of the source metallization 70 and the drain metallization 72, as well as the second field plate region 85.
[0072] exist Figure 4C In this context, the second insulating layer 62 is defined as forming a through opening 99 over the amplified portion 96a of the first connection region 96.
[0073] The third metal layer 98 extends over the non-active region 91, and particularly over the amplification portion 96a, filling the through opening 99 to form a connection via (indicated by the same reference numeral 99 as its shape is the same as the through opening). The connection via 99 electrically connects the upper portion 70b of the source metallization 70 to the amplification portion 96a of the first connection region 96 (at a lower level) and thereby to the first field plate 84.
[0074] Here, a third metal layer 98 is also defined to form a second field plate connection region 97 extending over the non-active region 91 between the upper portion 70b of the source metallization 70 and the second field plate region 85.
[0075] In all the previously discussed embodiments, the first field plate 84 can be arranged in different ways relative to the insulating layer 58. Specifically, as Figure 2 An alternative to the arrangement shown in which the first field plate 84 is formed entirely on the insulating layer 58 is that the first field plate 84 may be formed such that its lower portion is within the insulating layer 58.
[0076] In different embodiments, the first field plate 84 may be formed in contact with the semiconductor body 52. In this case, the insulating layer 58 may be partially removed.
[0077] The gate region 60 may extend directly onto and be in physical contact with the semiconductor body 52, or it may enter a groove in the semiconductor body 52.
[0078] The gate region 60 and the first field plate 84 can be defined by known masking and etching steps, in which case the insulating layer 58 is slightly recessed due to the etching process or the use of a stripping process. In this case, the insulating layer 58 has a flat upper surface instead of being recessed.
[0079] According to one aspect of this disclosure, as shown in FIG5, the first field plate 84 is used as a temperature or thermal sensor. Temperature measurement can be performed when the device is on (i.e., in an electrically conductive state) or when the device is off (i.e., not in an electrically conductive state).
[0080] In this regard, the first field board 84 can be connected to the first metal pad 100 and the second metal pad 102 to force current to flow to the first field board 84 and sense the voltage across the first field board 84. Figure 5A Is it used with Figures 4A-4C Representation of the HEMT device with the same top plan view. Metal pads 100, 102 are formed at the second end of the first field plate 84, which is opposite to the first end of the first field plate 84 to which the amplification portion 96a is coupled. Figure 5B yes Figure 5A A magnified view of the portion.
[0081] Metal pads 100 and 102 are electrically coupled to the second end of the first field plate 84 through their respective second connection regions 104 and third connection regions 106.
[0082] Connection regions 104 and 106 are integral with and extend from the first field plate 84 at its second end. Connection regions 104 and 106 extend from the second end of the first field plate 84 onto the non-active region 91 and electrically connect the first field plate 84 to metal pads 100 and 102. In one embodiment, metal pads 100 and 102 are integral with and extend from connection regions 104 and 106.
[0083] The connection region 96 is coupled to the first field plate 84 in a region closer to the first end of the first field plate 84 than to the second end of the first field plate 84.
[0084] The connection region 104 is coupled to the first field plate 84 in a region of the first field plate 84 that is closer to the second end of the first field plate 84 than to the first end of the first field plate 84.
[0085] The connection region 106 is coupled to the first field plate 84 in a region of the first field plate 84 that is closer to the second end of the first field plate 84 than to the first end of the first field plate 84.
[0086] In one embodiment, the portion of the first field plate extending along the Y-axis from the connection region 96 to the connection region 104 (or the connection region 106) is in the range of 25 μm to 1.5 mm.
[0087] Now for reference Figure 5A , Figure 5B and Figure 6 . Figure 6A system 150 including a device 50 according to any of the previously disclosed embodiments is schematically illustrated. To use the first field plate 84 as a temperature sensor, a current I is fed to the metal pad 100 by a current generator 110; the current flows from the metal pad 100 to the amplification section 96a, or vice versa (by appropriately biasing the metal pad 100 and the amplification section 96a). A voltage sensor 112 senses the voltage V across the first field plate 84 using the metal pad 102 and the amplification section 96a as sensing terminals. As is known, the sensing of the voltage V can provide an indirect measurement of the temperature of the first field plate 84 because the resistance (resistivity) R of the material (metal) of the first field plate 84 varies with its current temperature. This temperature can be assumed to be substantially equal to the temperature of the active region (channel). Therefore, the first field plate 84 operates as a resistance temperature detector (RTD).
[0088] Figure 6 The measurement method described in the text is also known as a two-wire (double-wire) measurement: a current source I (with high output impedance) excites the RTD, resulting in a voltage drop, which is measured through a circuit with high input impedance. The operating principle of the RTD relies on the fact that the resistivity (and therefore resistance) of a (pure) metal increases with increasing temperature. The physics behind this operating principle is that increased temperature causes higher thermal vibrations of atoms, thus reducing the average collision interval of electrons and increasing the resistivity of the metal. Platinum is the most commonly used metal for manufacturing RTDs. However, as already discussed, other metals are possible and envisioned in this disclosure for manufacturing the first field plate 84. Generally, platinum can withstand high temperatures and has good stability; furthermore, it is a noble metal with excellent resistance to chemical corrosion and contamination. Other usable metals are nickel and copper. Other usable metals may include aluminum.
[0089] The temperature input range for platinum-based RTDs is -200 to +850°C, while for nickel-based and copper-based RTDs, the ranges are -80 to +320°C and -200 to +260°C, respectively. Nickel-based RTDs offer almost twice the sensitivity of platinum-based RTDs, but with poorer linearity.
[0090] Other circuit implementations are conceivable for fabricating the integrated temperature sensor according to this disclosure. For example, a 4-wire (quad-wire) measurement, also known as a Kelvin resistance measurement, can be employed.
[0091] When used as a thermal sensor, the current injected from one side of the field plate 84 causes lateral depolarization of the field plate 84. However, this effect is negligible because the current required for the control circuit system to detect the voltage increase is very low. The injected current I is actually approximately 100μA-100mA.
[0092] like Figure 6 As shown, the HEMT device 50 also includes an external control circuit system to inject current into the field plate 84 and acquire / monitor the voltage drop across the field plate 84 when used as a thermal sensor. A surge suppressor can be implemented on the detection side of the control circuit system to prevent the control circuit system from injecting any possible current spikes into the field plate 84.
[0093] The thermal sensor disclosed above can also be applied to GaAs-based HEMT devices as an alternative to GaN.
[0094] The thermal sensor disclosed above can also be implemented in semiconductor devices different from HEMT, such as LDMOS transistors whose field plates are connected to the source.
[0095] The semiconductor device (50) is generally defined as including: a semiconductor body (52) having a semiconductor heterostructure (54, 56); a gate region (60) made of a conductive material disposed on and in contact with the semiconductor body (52); a first insulating layer (58) extending over the semiconductor body and laterally toward the conductive gate region (60); a second insulating layer (62) extending over the first insulating layer (58) and the gate region (60); and a first field plate (84) made of a metallic material extending between the first insulating layer and the second insulating layer (58, 62) and adjacent to the conductive gate region. The domains (60) are laterally spaced apart. The first field plate (84) has a strip shape in the top plan view, the main extension of which is along a first direction (Y). The strip shape has a first end and a second end opposite to each other along the first direction (Y). A first conductive pad (96a) is electrically contacted with the first field plate (84) at the first end through a first connection region. A second conductive pad (104) is electrically contacted with the first field plate (84) at the second end through a second connection region. A third conductive pad (106) is electrically contacted with the first field plate (84) at the second end through a third connection region.
[0096] The first plate area (84) is made of pure metal, particularly one of platinum, nickel, copper, or aluminum.
[0097] The first connecting region is closer to the first end than to the second end; and both the second and third connecting regions can be closer to the second end than to the first end.
[0098] The first connecting region is coupled to the first field plate (84) at the first intersection point, the second connecting region is coupled to the first field plate (84) at the second intersection point, and the third connecting region is coupled to the first field plate (84) at the third intersection point. The length of the first field plate (84) along the first direction (Y) from the first intersection point to at least one of the second and third intersection points is in the range of 25 μm to 1.5 mm.
[0099] The device is one of the following: HEMT, LDMOS transistor.
[0100] The semiconductor body (52) includes at least a first semiconductor layer (54) and a second semiconductor layer (56), the first semiconductor layer (54) including aluminum gallium nitride (AlGaN), the second semiconductor layer (56) including gallium nitride (GaN) and gallium arsenide (GaAs), and the second semiconductor layer (56) is adjacent to the first insulating layer (58).
[0101] The first field plate (84), the first conductive pad, the second conductive pad and the third conductive pad (96a, 104, 106) and the first connection area, the second connection area and the third connection area (96, 100, 102) form a resistance temperature detector (RTD); the first conductive pad, the second conductive pad and the third conductive pad (96a, 104, 106) are the terminals of the RTD; the first field plate (84) has a temperature-dependent resistivity.
[0102] The device also includes a second field plate (85) made of conductive material that extends over the second insulating layer (62), the second field plate region covering the first field plate (84).
[0103] The device also includes a drain contact region (72) and a source contact region (70) made of conductive material, extending over and electrically contacting the semiconductor body (52), through a first insulating layer and a second insulating layer (58, 62) on opposite sides of the gate region (60), wherein a first field plate region (84) extends between the gate region and the drain contact region (72).
[0104] The first conductive pad (96a) is electrically coupled to the source contact region (70).
[0105] The first field plate region (84) has a first width (L1) along a second direction (X) that is transverse to the first direction (Y), and the second field plate region (85) has a second width (L2) along the second direction (X), wherein the second width is greater than the first width.
[0106] A system includes devices; a control circuit system having: a current generator coupled to a first conductive pad (96a) and to one of a second conductive pad and a third conductive pad (104, 106), operable to cause a current (I) to flow through a first field plate (84) between the first conductive pad (96a) and the one of the second and third conductive pads (104, 106); and a voltage sensor coupled to the first conductive pad (96a) and to the other of the second and third conductive pads (104, 106), operable to sense a voltage drop (V) across the first field plate (84) when the current (I) flows through the first field plate (84).
[0107] The system also includes a processor configured to correlate the value of the voltage drop (V) with a corresponding value of the temperature.
[0108] A method of operating a device includes: allowing a current (I) to flow through a first field plate (84) between a first conductive pad (96a) and one of a second conductive pad and a third conductive pad (104, 106); sensing a voltage drop (V) across the first field plate (84) while the current (I) flows through the first field plate (84); and correlating the value of the voltage drop (V) with a corresponding value of temperature.
[0109] The various embodiments described above can be combined to provide other embodiments. If necessary, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.
[0110] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments together with the full scope of equivalents enjoyed by such claims. Therefore, the claims are not limited by the disclosure.
Claims
1. A semiconductor device, characterized in that, The device includes: A semiconductor body having a semiconductor heterostructure; A gate region, made of a conductive material, is located on and in contact with the semiconductor body; A first insulating layer extends over the semiconductor body and laterally toward the conductive gate region, the first insulating layer comprising a first portion and a second portion, wherein the second portion is located below the first portion; A second insulating layer extends over the first insulating layer and the gate region; A first field plate, made of a metallic material, extends between a first insulating layer and a second insulating layer and is laterally spaced from the gate region. The first field plate has a strip-like shape in the top plan view, with its main extension along a first direction. The strip-like shape has a first end and a second end opposite to each other along the first direction. A first conductive pad, which is electrically contacted with a first field plate at a first end via a first connection area; A second conductive pad, which is electrically contacted with the first field plate at a second end via a second connection region; and The third conductive pad is electrically connected to the first field plate at the second end via a third connection area.
2. The device according to claim 1, characterized in that, The first board was made of pure metal.
3. The device according to claim 2, characterized in that, Pure metals are one of platinum, nickel, copper, and aluminum.
4. The device according to claim 1, characterized in that, The first connecting region is closer to the first end than to the second end; and both the second and third connecting regions are closer to the second end than to the first end.
5. The device according to claim 1, characterized in that, The first connecting region couples to the first field plate at the first intersection point, the second connecting region couples to the first field plate at the second intersection point, and the third connecting region couples to the first field plate at the third intersection point. The length of the first plate along the first direction from the first intersection point to at least one of the second and third intersection points is in the range of 25 μm to 1.5 mm.
6. The device according to claim 1, characterized in that, This device is a type of HEMT or LDMOS transistor.
7. The device according to claim 1, characterized in that, The semiconductor body includes at least a first semiconductor layer and a second semiconductor layer, the first semiconductor layer including aluminum gallium nitride, the second semiconductor layer including one of gallium nitride and gallium arsenide, and wherein the second semiconductor layer is adjacent to the first insulating layer.
8. The device according to claim 1, Its characteristics are: The first board, the first conductive pad, the second conductive pad and the third conductive pad, as well as the first connection area, the second connection area and the third connection area form a resistance temperature detector; The first conductive pad, the second conductive pad, and the third conductive pad are the terminals of the resistance temperature detector; as well as The first plate has a temperature-dependent resistivity.
9. The device according to claim 1, characterized in that, The device also includes a second field plate made of conductive material extending over the second insulating layer, the second field plate covering the first field plate.
10. The device according to claim 9, characterized in that, The second field plate is located on the second part of the first insulating layer.
11. The device according to claim 9, characterized in that, The second field plate covers the gate region.
12. The device according to claim 9, characterized in that, The first field plate has a first width along a second direction that is transverse to the first direction, and the second field plate has a second width along the second direction, wherein the second width is greater than or equal to the first width.
13. The device according to claim 1, characterized in that, The device further includes a drain contact region and a source contact region made of conductive material, extending over and electrically contacting the semiconductor body, passing through a first insulating layer and a second insulating layer on opposite sides of the gate region, wherein a first field plate extends between the gate region and the drain contact region.
14. The device according to claim 13, characterized in that, The first conductive pad is electrically coupled to the source contact area.
15. The device according to claim 13, characterized in that, The device further includes a second field plate extending over the second insulating layer, wherein the second field plate covers the first field plate in a top plan view and in a cross-sectional view transverse to the top plan view, the second field plate partially covers the first field plate.
16. The device according to claim 13, characterized in that, The second field plate is electrically coupled to the source contact region.
17. A system, characterized in that, The system includes: The device includes: Gate region; A first insulating layer, the first insulating layer comprising a first portion and a second portion, wherein the second portion is located below the first portion; A second insulating layer extends over the first insulating layer and the gate region; A first field plate extends between a first insulating layer and a second insulating layer, and is positioned on a second portion of the first insulating layer, laterally spaced from the gate region. A first conductive pad, which is in contact with a first field plate; A second conductive pad, which is in electrical contact with the first field plate; and The third conductive pad is in electrical contact with the first field plate; The control circuit system has the following features: A current generator coupled to a first conductive pad and to one of a second and a third conductive pad, operable to allow current to flow through a first field plate between the first conductive pad and one of the second and third conductive pads; and A voltage sensor, coupled to a first conductive pad and to another of a second and a third conductive pad, is operable to sense the voltage drop across the first field plate when current flows through it.
18. The system according to claim 17, characterized in that, The system also includes a processor configured to correlate the voltage drop value with a corresponding temperature value.