Digital ring oscillator and integrated circuit die

Abstract

The utility model relates to a digital ring oscillator and an integrated circuit die. Digital ring oscillators (DROs) are distributed throughout the integrated circuit die to enable small form factor local temperature sensing. The DRO may include a cross-coupled inverter, header and foot transistors, and a delay element. Leakage current through the DRO causes a state of an internal node to switch at a frequency as a function of a temperature of the DRO, which may depend on a temperature of a nearby circuit, such as a processor. The integrated circuit die may include a controller coupled to the DRO. The controller may receive an oscillating digital signal generated by the DRO and control operation of the integrated circuit die based on a temperature indicated by the frequency of the oscillating digital signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to temperature monitoring systems. In particular, the present disclosure relates to in-situ temperature monitoring in integrated circuits. BACKGROUND

[0002] With the advent of energy saving techniques such as dynamic voltage and frequency scaling (DVFS) on multi-core CPUs and dense system-on-chip (SoC), on-die temperature measurement is becoming increasingly important. As the number of processing units on a single integrated circuit die increases, local hotspots become more common and those local hotspots become hotter faster. For example, advanced technology nodes using backside power delivery and gate-all-around FETs (GAAFETs) have very low heat dissipation capabilities. The latent heat from local hotspots in high performance silicon leads to increased leakage current in energy saving cores, which creates a positive feedback effect (i.e., thermal runaway). If left unmonitored, thermal runaway can lead to catastrophic failure.

[0003] Devices such as laptops or cell phones have processing cores that operate at different frequencies, which requires different workload balancing based on local thermal limits. To control the workload, a process management system measures the temperature on the chip and controls the workload based on those measured temperatures. Given the differences in core workloads (i.e., different cores can operate at different temperatures), local temperature can be important. Some temperature sensing solutions can require significantly more area on the chip. For example, an image processing chip that requires significant processing unit space can reserve a significant amount of space (e.g., half the chip) for a temperature sensing solution. Due to this large size, the temperature sensing solution measures the temperature across a larger area, which can not accurately represent the local hotspot temperature. Furthermore, some temperature sensing solutions produce an analog signal that requires shielding, has a very high area overhead, requires time consuming dedicated manual routing work, and requires conversion to a digital signal. This conversion requires a space consuming analog-to-digital converter for post processing. Some temperature sensing solutions can also require a dedicated power supply to operate. For example, one solution is a bandgap reference circuit, which adds power overhead to the chip. Thus, such temperature sensing solutions can have a large chip area, be inaccurate, and power inefficient. SUMMARY

[0004] In one aspect, a digital ring oscillator includes a pair of cross-coupled inverters, two head transistors coupled between a supply voltage and the inverters, two foot transistors coupled between the inverters and ground, and a delay element coupled to inputs of the head and foot transistors and an output of the inverters. An input of each of the inverters is coupled to an output of the other inverter at one of two complementary state nodes. The head transistors gate connections of the supply voltage to the inverters. The foot transistors gate connections of the inverters to ground. A delay element is coupled between the state nodes and gates of the head and foot transistors. The state nodes switch states due to leakage current gated by the head transistors from the supply voltage through the inverters to the state nodes and due to leakage current gated by the foot transistors from the state nodes through the inverters to ground. A frequency of the switching is a function of the leakage current and the leakage current is a function of a temperature of the digital ring oscillator.

[0005] In another aspect, a controller receives an oscillating digital signal (e.g., a clock-like digital signal) from a sensor block on an integrated circuit die. A frequency of the oscillating digital signal varies with temperature. The controller controls operation of circuitry on the integrated circuit die based on a temperature indicated by the frequency of the oscillating digital signal.

[0006] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer readable media, and other technologies related to any of the above. BRIEF DESCRIPTION OF DRAWINGS

[0007] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of an integrated circuit with a built-in temperature sensor block according to some embodiments of the disclosure.

[0009] Figure 2A is a schematic diagram of a unit cell of a temperature sensor block according to some embodiments of the disclosure.

[0010] Figure 2B is a diagram showing states of switches of a unit cell of Figure 2A according to some embodiments of the disclosure.

[0011] Figure 3A is a simplified representation of a unit cell of Figure 2A according to some embodiments of the disclosure.

[0012] Figure 3B is a diagram showing a simplified representation of a state of a switch according to some embodiments of the disclosure. Figure 3A

[0013] Figure 4 depicts a digital ring oscillator (DRO) according to some embodiments of the disclosure.

[0014] Figure 5 depicts a timing diagram of inputs, outputs, and transistor states of the DRO of Figure 4

[0015] Figure 6 is a flowchart of various processes used during design and fabrication of integrated circuits according to some embodiments of the disclosure.

[0016] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure relate to a leakage-based on-chip temperature analysis system. Temperature measurement is important for detecting overheating chips and preventing catastrophic failures. The digital ring oscillator (DRO) described herein can produce a digital oscillation signal as a function of temperature. The oscillation frequency is a function of the leakage current, and the leakage current is a function of temperature. Using a digital ring oscillator to measure temperature is advantageous for digital circuits because the output of the digital ring oscillator does not need to be interpreted by a processing or controller unit on the digital circuit with an analog-to-digital converter (ADC) and also avoids an expensive shielding path. In contrast, some temperature sensing designs can produce an analog output and thus require an ADC on the chip. Thus, utilizing a digital ring oscillator is space efficient, not only because the ADC does not take up space to convert the output of the digital ring oscillator, but also because the digital ring oscillator occupies substantially less area than some temperature sensing designs, such as bandgap reference circuits. Furthermore, by utilizing leakage current to determine temperature, the digital ring oscillator does not increase the power overhead of the chip.

[0018] The relatively small form factor of the DRO also provides improved accuracy in measuring local hotspot temperatures, which are not measurable by larger temperature sensors. Multiple DROs can be placed in close proximity to a single processing unit to measure temperatures at different locations on the single processing unit. This fine granularity can be extended by placing one or more DROs at various processing units in a single integrated circuit die to determine an on-die temperature profile with a finer measurement granularity than can be provided by one large temperature sensor.

[0019] ​​The digital ring oscillator described herein is also advantageous from a usability perspective. The utility digital ring oscillator is similar to more interchangeable switching elements as compared to some solutions that require special care during placement in a circuit layout (e.g., creating boundaries around temperature sensing circuits). Thus, commercial compilers can be able to automatically replace temperature sensor circuits with the utility digital ring oscillator.

[0020] The utility temperature sensing system also improves thread management efficiency by taking action based on the monitored temperature without the need for an additional step to convert the output of the temperature sensor block from analog to digital. The output of the digital ring oscillator is already digital. The benefits of not needing an ADC conversion for the utility temperature sensor include saving the space on the chip that would otherwise be needed for the ADC, not needing to wait for the time that would otherwise be needed to convert the analog output to a digital output, and reducing the power consumption that would otherwise be needed for the ADC. Rather than using an ADC that has a larger footprint than a frequency divider or time-to-digital converter, one or more frequency dividers or time-to-digital converters can be used in combination with the digital ring oscillator.

[0021] In more detail, Figure 1 is a block diagram of an integrated circuit 100 with built-in temperature sensor blocks 130 according to some embodiments of the disclosure. Each sensor block can include a DRO that generates a frequency that depends on the nearby temperature (e.g., a temperature detected within a threshold range) that affects the leakage current through the DRO. The built-in sensor blocks 130 allow for a fine-grained temperature sensing system. The sensor blocks 130 can have a relatively small form factor (e.g., less than a standard cell, such as a flip-flop or latch). Each sensor block 130 can be a standard library cell design, allowing unconstrained placement of the cell with multiple instantiations. The multiple instantiations of the sensor blocks 130 allow for faster detection of local hotspots on the integrated circuit 100. The sensor blocks 130 operate according to a leakage-based temperature sensing principle. The sensor blocks 130 are very sensitive to temperature changes and less sensitive to process and voltage variations.

[0022] In this particular example, the integrated circuit 100 contains different functional blocks 110. Examples can include processor cores, on-chip memory, input / output (I / O) interfaces, other types of logic and analog and mixed-signal circuits. Examples of processor cores include energy-efficient cores, performance cores, computer processing units (CPUs), or neural engines.

[0023] The integrated circuit 100 also includes temperature sensor blocks, shown as small black squares (some of which are labeled 130), and corresponding controllers 150. The sensor blocks 130 are distributed throughout the integrated circuit to monitor temperature at different points across the integrated circuit. The sensor blocks 130 are proximate to the functional blocks 110. Temperature can be monitored by a circuit, such as a digital ring oscillator, that utilizes a frequency that varies with temperature. For example, the transistor leakage current of a digital ring oscillator is amplified with modified digital gates and converted to an oscillating digital signal that is related to the temperature on the die. Figure 1 The distribution of sensor blocks 130 shown in FIG. 1 is not intended to be limiting. Different distributions of sensor blocks 130 would be apparent. The number of sensor blocks 130 on an integrated circuit die can be greater than the number of controllers 150 on the integrated circuit die.

[0024] In some embodiments, the post-processing unit 120 and the sensor controllers 150 are also integrated on-chip. In Figure 1 In FIG. 1, they are shown as two separate blocks and implemented in a distributed manner, but in some embodiments, the functions thereof can be performed by a single block (e.g., the controller 150 also performs the functions of the post-processing unit 120). The post-processing unit 120 and / or the controller 150 communicate with the sensor blocks 130. The post-processing unit 120 and / or the controller 150 can send control signals to configure the sensor blocks 130 (e.g., send input signals that cause the sensor blocks 130 to output data 156). The controller 150 can be a dynamic voltage and frequency scaling (DVFS) controller.

[0025] The post-processing unit 120 can receive data 156 from the sensor blocks 130. The data 156 can include oscillating digital signals ("oscillating digital signals" or "oscillating signals") having frequencies indicative of temperatures at local hot spots on the integrated circuit 100 (e.g., at a functional block or a local region of a functional block). Each sensor block 130 can provide such an oscillating signal in the data 156 to the post-processing unit 120. The post-processing unit 120 can determine the frequency of the oscillating signal using a frequency divider, a frequency counter, or a time-to-digital converter. The post-processing unit 120 can include one or more of such units for determining the frequency of a received oscillating signal. For example, the post-processing unit 120 can include 10 frequency dividers to determine 10 different oscillating signals from 10 different sensor blocks 130.

[0026] The post-processing unit 120 can perform comparisons and / or mappings to determine a temperature corresponding to the received oscillation signals. In one example of determining a temperature, the post-processing unit 120 accesses a register file that includes a mapping of frequency to temperature. In some embodiments, multiple register files can be accessible, where different register files correspond to different types of processing units (i.e., processing units of different operating frequencies). The post-processing unit 120 can look up a temperature that maps to the determined frequency of the oscillation signal. In another example of determining a temperature, the post-processing unit 120 uses a combination of comparisons and mappings. The post-processing unit 120 can compare the received frequencies to reference frequencies. The reference frequencies can be within a similar range (e.g., a range from a few kilohertz to a gigahertz) at which the sensor block 130 operates. The reference frequencies can be stored in a register file that is accessible by the post-processing unit 120. The post-processing unit 120 can be pre-calibrated to obtain an absolute temperature based on a difference between the received frequencies and the reference frequencies, where pre-calibration involves a lookup table in the register file that stores data (e.g., empirical or simulated) for temperature comparisons. For example, the post-processing unit 120 can access a register file that includes a mapping of frequency difference (i.e., relative to a reference frequency) and temperature. The post-processing unit 120 can then determine a temperature by lookup method. Additionally or alternatively, the post-processing unit 120 can compare the received frequencies to each other to determine a difference between the received frequencies. The post-processing unit 120 can provide the results of these comparisons to the controller 150.

[0027] In some cases, the controller 150 can provide some analysis of the received data 156. For example, the controller 150 can use the differences between the frequencies of the oscillation signals of the sensor block 130 to determine a temperature distribution profile on the die. The controller 150 can determine control signals 154 based on the data 156 output by the sensor block 130. The control signals 154 can include instructions for enabling or disabling throttling at a functional block. For example, the controller 150 can determine to enable voltage or clock throttling at a functional block in response to the data 156 indicating that there is a local hot spot at the functional block. In this example, the controller 150 can also determine to disable voltage or clock throttling in response to the data 156 indicating that there is not a local hot spot. The control signals 154 can include instructions to allocate processing threads among the processing units of the functional block 110 based on the data 156 (e.g., based on comparisons of frequencies determined by the post-processing unit 120). The controller 150 can send the control signals 154 to the functional block 110. In response to determining that a temperature of an identified local hot spot is below a threshold temperature, the controller 150 can disable voltage throttling at the integrated circuit die. In response to determining that a temperature of an identified local hot spot is above a threshold temperature, the controller 150 can enable voltage throttling at the integrated circuit die.

[0028] Temperature monitoring across different conditions (e.g., supply voltage and operating frequency) and over time can be used to predict future failures before they occur as part of overall lifecycle management of a device. The post-processing unit 120 or controller 150 can provide the monitored oscillation frequency, temperature profile across the die, and / or determined temperatures at local regions on the die to a monitoring system. The monitoring system can include multiple instantiations of the post-processing unit 120 and / or controller 150 across multiple integrated circuit dies. Collecting data from sensor blocks across various functional blocks on various integrated circuit dies allows the monitoring system to identify trends and correlations across the device (e.g., a smartphone) as a whole. The monitoring data can be analyzed on-chip (e.g., at the controller 150). Alternatively or additionally, the data can be analyzed off-chip. For example, more complex analysis can require computational resources not available on-chip, and storing monitoring data indicative of local temperatures captured over a long period of time can require more space than available on-chip. The analysis can also combine the monitoring data with other data not available on-chip, such as external measurements of power consumption. As another example, monitoring data from multiple chips can be analyzed together to provide a view of a board, rack-mounted device, or other environment that is larger than a single chip.

[0029] Figure 2A is a schematic diagram of a unit cell of a temperature sensor block according to some embodiments of the disclosure. Figure 2B is a diagram showing one embodiment of a state of switches of the unit cell of Figure 2A Figure 2B Further shows a preferred leakage path according to the shown embodiment. The leakage path causes the internal nodes of the unit cell to charge and discharge, creating an oscillation signal whose frequency is indicative of the temperature affecting the unit cell (e.g., the temperature of the functional block the unit cell is proximate to).

[0030] The unit cell 200 includes p-channel metal-oxide-semiconductor (PMOS) head transistors 210 and 230, n-channel metal-oxide-semiconductor (NMOS) foot transistors 220 and 240, and cross-coupled inverters (transistors 213 / 223 and 233 / 243). The PMOS head transistors 210 and 230 are cross-coupled. That is, the gate of transistor 212 is coupled to the drain of transistor 232, and the gate of transistor 232 is coupled to the drain of transistor 212. Similarly, the NMOS foot transistors 220 and 240 are cross-coupled. That is, the gate of transistor 222 is coupled to the drain of transistor 242, and the gate of transistor 242 is coupled to the drain of transistor 222. The PMOS head transistors can be referred to as PMOS heads, and the NMOS foot transistors can be referred to as NMOS feet. The total number of transistors of the unit cell 200 is 12 transistors.

[0031] ​The cross-coupled inverters include a first inverter configured with a PMOS transistor 213 and an NMOS transistor 223, and a second inverter configured with a PMOS transistor 233 and an NMOS transistor 243. The inverters are cross-coupled because the input of each inverter is coupled to the output of the other inverter. PMOS heads 210 and 230 gate the supply voltage to the connection of the cross-coupled inverters. NMOS feet 220 and 240 gate the connection of the cross-coupled inverters to ground.

[0032] The cross-coupled inverters form a bistable circuit with state nodes 260 and 261 in complementary states. The first state node 260 is the output of the first inverter and the input of the second inverter. The second state node 261 is the output of the second inverter and the input of the first inverter. The state nodes 260 and 261 are connected to nodes 250 and 251, respectively, through delay elements as described with respect to Figure 4 Further described.

[0033] The PMOS head 210 is made up of two PMOS transistors 211 and 212 connected in parallel. Similarly, the PMOS head 230 is made up of two PMOS transistors 231 and 232 connected in parallel. The NMOS foot 220 is made up of two NMOS transistors 221 and 222 connected in parallel. Similarly, the NMOS foot 240 is made up of two NMOS transistors 241 and 242 connected in parallel. The source of the PMOS transistor 213 is coupled to the drains of the PMOS transistors 211 and 212. The NMOS transistor 223 is coupled to the drain of the PMOS transistor 213 and the drains of the NMOS transistors 221 and 222. The source of the PMOS transistor 233 is coupled to the drains of the PMOS transistors 231 and 232. The gate of the PMOS transistor 232 is coupled to the drains of the PMOS transistors 211 and 212. The drains of the PMOS transistors 231 and 232 are coupled to the gate of the PMOS transistor 212. The NMOS transistor 243 is coupled to the drain of the PMOS transistor 233 and the drains of the NMOS transistors 241 and 242. The gate of the NMOS transistor 242 is coupled to the drains of the NMOS transistors 221 and 222. The drains of the NMOS transistors 241 and 242 are coupled to the gate of the NMOS transistor 222.

[0034] Transistors 212, 222, 232, and 242 are used to maintain voltage stability at the unit cell 200. Transistors 212, 222, 232, and 242 maintain full voltage swing and prevent floating nodes at the head and foot transistors (e.g., the drain terminal at the PMOS head or the drain terminal at the NMOS foot). Transistors 211, 221, 231, and 241, in combination with the cross-coupled inverters (composed of transistors 213, 223, 233, and 243), are used to provide temperature sensing characteristics of the unit cell 200.

[0035] Sensing the temperature experienced at the unit cell 200 depends on the leakage current through the inverter transistors 213, 223, 233, and 243. For example, as current leaks from VDD through the PMOS head 230 (in the on state) through transistor 233 (in the off state) to the state node 261, the state node 261 charges from '0' to '1'. In this same example, as current leaks through transistor 223 (in the off state) through the NMOS foot 220 (in the on state) to ground, the state node 260 discharges from '1' to '0'. This example of leakage current is depicted in Figure 2B .

[0036] In another example, as current leaks from VDD through the PMOS head 230 (in the on state) through transistor 233 (in the off state) to the state node 261, the state node 261 charges from '0' to '1'. In this same example, as current leaks through transistor 223 (in the off state) through the NMOS foot 220 (in the on state) to ground, the state node 260 discharges from '1' to '0'. The charging and discharging of any given state node constitutes a state switch at that internal node. As described above, this switch is a result of the leakage current from the supply voltage through the cross-coupled inverters, gated by the head transistors 210 and 230, to the state nodes 260 and 261, respectively. The switch is also a result of the leakage current from the state nodes 260 and 261 through the cross-coupled inverters, gated by the foot transistors 220 and 240, to ground, respectively. Leakage current is a function of temperature, so the frequency of the switch is a function of temperature.

[0037] Figure 2B is a diagram showing one embodiment of the state of the switch of the unit cell 200 of Figure 2A . Additionally, Figure 2BA leakage path based on the state of the switches is shown. In this example, the value at input 250 is '0' (a logic low state) and the value at input 251 is '1' (a logic high state). These inputs cause PMOS head transistor 210 to turn on, NMOS foot transistor 220 to turn off, PMOS transistor 213 to turn off, and NMOS transistor 223 to turn on. These on and off states are shown as closed and open switches, respectively, in Figure 2B . This configuration of transistor switch states facilitates leakage current 270 from the supply to state node 260, which is represented as a capacitor in Figure 2B . State node 260 is in the '0' state until leakage current charges state node 260 to the '1' state.

[0038] To the right of unit cell 200, the '0' at input 250 and the '1' at input 251 cause complementary switch states. That is, these inputs cause PMOS head 230 to turn off, NMOS foot 240 to turn on, PMOS transistor 233 to turn on, and NMOS transistor 243 to turn off. This configuration causes state node 261, which is in the '1' state, to begin discharging due to leakage current 271 through NMOS transistor 243 to ground. State node 261 is represented by a capacitor in Figure 2B , similar to state node 260.

[0039] State node 260 charging to a logic high and state node 261 discharging to a logic low causes the cross-coupled inverters of unit cell 200 to flip. The cross-coupled inverters provide high gain to toggle unit cell 200. This toggling can correspond to one of leakage currents 270 and 271 (e.g., proportional to the one) through unit cell 200. These leakage currents 270 and 271 are related to temperature in the vicinity of unit cell 200 (e.g., the temperature of a processing unit in which unit cell 200 is located in proximity to). The relationship between temperature and leakage current includes that leakage current is greater when temperature is higher and leakage current is less when temperature is lower.

[0040] Figure 3A is a method of operating a processing unit according to one embodiment Figure 2AA simplified representation of unit cell 200. PMOS transistor 213 and NMOS transistor 223 are represented by inverter 300. State node 261 is depicted as the input to inverter 300. PMOS transistor 233 and NMOS transistor 243 are represented by inverter 310. State node 260 is depicted as the input to inverter 310. Transistors 211, 221, 231, and 241 are depicted as they are used for temperature sensing. Although transistors 212, 222, 232, and 242 are not depicted and can be excluded without necessarily sacrificing the temperature sensing capabilities of unit cell 200, transistors 212, 222, 232, and 242 maintain voltage stability. That is, transistors 212, 222, 232, and 242 are included in unit cell 200 to prevent floating nodes and encourage full voltage swings at those nodes.

[0041] Ignoring the delay elements for the moment, the states of inputs 250 and 251 at unit cell 200 are coupled to the states of internal nodes 260 and 261 of cross-coupled inverters 300 and 310, respectively. For example, a '0' state at input 250 is the result of a '0' state stored at state node 260. Similarly, a '1' state at input 251 is the result of a '1' state stored at state node 261. The switching frequency of any of these nodes 250, 251, 260, 261, i.e., the oscillating signal output by the DRO, is a function of the leakage current through unit cell 200.

[0042] In addition, the states of inputs 250 and 251 at unit cell 200 are complementary to the states of internal nodes 260 and 261. For example, a '0' state at input 250 is complementary to a '1' state stored at internal node 261. Similarly, a '1' state at input 251 is complementary to a '0' state stored at internal node 260. This complementary logic creates the least preferred resistive path from power supply VDD to an internal node or from an internal node to ground. In one example of the creation of the least preferred resistive path, internal node 261 discharges from '1' to '0' through NMOS transistor 243, and leakage current from PMOS head 230 does not shift this discharge. In this example, the intermediate node between PMOS head 230 and PMOS transistor 233 is at VDD, and since the initial state of internal node 261 is '1', it is also at VDD. Thus, both the source-to-drain voltage of PMOS head 230 and transistor 233 are 0V, creating a high resistance path that current will not naturally follow. Thus, the natural current leakage path is through NMOS transistor 243, causing internal node 261 to discharge.

[0043] Figure 3B is shown to be in a state of '0' and '1' at inputs 250 and 251, respectively. In this state, the state of internal node 261 is '1' and the state of internal node 260 is '0'. Inverter 300 is in a state of '0' and inverter 310 is in a state of '1'. Thus, the state of input 250 is '0' and the state of input 251 is '1'. Figure 3Aa '0' input at the gate of the PMOS transistor 211. The NMOS transistor 221 is depicted as an open switch in response to a '0' input at the gate of the NMOS transistor 221. The state node 260, which is in state '0', can charge to '1' due to a leakage current from the supply voltage through the inverter 300 to the state node 260, which is gated by the head transistor 211. The PMOS transistor 231 is depicted as an open switch in response to a '1' input at the gate of the PMOS transistor 231. The NMOS transistor 241 is depicted as a closed switch in response to a '1' input at the gate of the NMOS transistor 241. The state node 261, which is in state '1', can discharge to '0' due to a leakage current through the inverter 310 to ground, which is gated by the foot transistor 241.

[0044] Figure 4 A digital ring oscillator 400 is depicted in accordance with one embodiment. Figure 4 The circuit of Figure 3A and 3B The same as in the unit cell 200, delay elements 410, 411 are added between the state nodes 260, 261 and the corresponding inputs 250, 251. The DRO 400 is composed of the head transistors 211 and 231, the cross-coupled inverters 300 and 310, the foot transistors 221 and 241, and the delay elements 410 and 411. Although not depicted, the transistors 212, 222, 232, and 242 can be included in the DRO 400 to improve the voltage stability of the DRO 400. Figure 2A The unit cell 200 can be transformed into a digital ring oscillator by inserting delay elements 410 and 411 at the gates of the transistors 211, 221, 231, and 241, as depicted in Figure 4 The delay elements 410 and 411 stabilize the DRO 400 (e.g., the delay elements maintain the Barkhausen criterion). The delay elements 410 and 411 create a delay between the state nodes 260 and 261 and the gates of the PMOS head transistors 210 and 230 and the NMOS foot transistors 220 and 240. In particular, the delay element 410 is positioned between the state node 260 and the input 250, and the delay element 411 is positioned between the state node 261 and the input 251. The sensor block 130 can include the DRO 400. The switching state of one or more of the internal nodes 260 and 261 of the DRO 400 can contribute to an oscillating digital signal output by the DRO 400 (e.g., an output as measured at either of the internal nodes 260 or 261). This oscillating digital signal can be included in the data 156 output by the sensor block 130.

[0045] Figure 5A timing diagram depicting the input, output, and transistor states of DRO 400, according to at least one embodiment. In timing diagram 500, Figure 5 The state node 260 labeled "output" begins at logic low. In this state, PMOS inverter transistor 213 is off and NMOS inverter transistor 223 is on. This connects state node 260 to ground. After a delay Δ enabled by delay element 410, the value of state node 260 is reflected at input 250. A '0' at input 250 causes PMOS head 210 to turn on and NMOS foot 220 to turn off. This establishes a leakage path from VDD through PMOS head 210. Leakage current from VDD through PMOS head 210 and off PMOS 213 begins to charge node 260, as indicated by the "charge" label in Figure 5 The "charge" label in indicates when state node 260 reaches the threshold point. The bistability of the cross-coupled inverters causes the same node 260 to switch from '0' to '1', as indicated by the "switch" label in Figure 5 This process then repeats, but discharges state node 260.

[0046] Complementary state node 261 operates similarly, but in the complementary state. Node 261 charges when node 260 discharges, and vice versa.

[0047] Figure 6 An example process set 600 for transforming and verifying design data and instructions representing an integrated circuit during design, verification, and fabrication of an article of manufacture, such as an integrated circuit, is illustrated. Each of these processes can be structured and implemented as a number of modules or operations. The term 'EDA' denotes the term 'electronic design automation.' These processes begin with creating a product idea 610 using information supplied by a designer, which is transformed to create an article of manufacture using a set of EDA processes 612. When the design is complete, the design is flowed 634, at which point the artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to make a set of masks, which are then used to manufacture the integrated circuit. After flow, semiconductor dies are fabricated 636, and packaging and assembly processes 638 are performed to produce finished integrated circuits 640.

[0048] The specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description language. Higher levels of representation can be used to design circuits and systems using a hardware description language ('HDL'), such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more detailed description adds more useful detail to the design description, e.g., more detail about the modules included in the description. Lower levels of representation as more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of language than HDL is SPICE, which is used to describe a circuit in great detail with many analog components. The description at each level of representation is enabled to be used by the corresponding tools at that layer, e.g., formal verification tools. The design process can use Figure 6 The processes described in the middle are enabled by EDA products (or tools).

[0049] During system design 614, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics, such as power consumption, performance, area (physical and / or lines of code), and cost reduction, among others. The division of the design into different types of modules or components can occur at this stage.

[0050] During logic design and functional verification 616, the modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specification is checked. For example, the components of the circuit can be verified to generate outputs that match the requirements of the specification for the circuit or system being designed. Functional verification can use simulators and other programs, such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a special component system, called a'simulator' or 'prototype system', is used to speed up functional verification.

[0051] During synthesis and test design 618, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent the components of the circuit and where the nodes of the graph structure represent the way the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit, when manufactured, operates according to the specified design. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0052] During netlist checking 620, the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning 622, the overall floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0053] During placement or physical implementation 624, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components through a plurality of conductors) occurs, and selection of cells from a library to implement a particular logic function can be performed. As used herein, the term "cell" can designate a set of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a memory function (e.g., a flip-flop or latch). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled as two physical structures and in simulation. Parameters such as size are selected for the selected cells (based on'standard cells') and made accessible in a database for use by EDA products.

[0054] During analysis and extraction 626, the circuit function is checked at the layout level, which permits improvement of the layout design. During physical checking 628, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, lithography constraints, are correct and that the circuit system function matches the HDL design specification. During resolution enhancement 630, the geometry of the layout is transformed to improve the manufacturing way of the circuit design.

[0055] During tapeout, data is created for production of photolithographic masks (after lithography enhancement is applied, where appropriate). During mask data preparation 632, the 'tapeout' data is used to produce photolithographic masks for production of finished integrated circuits.

[0056] The storage subsystem(s) of a computer system (e.g., the computer system 700 of Figure 7 The storage subsystem(s) of a computer system (e.g., the computer system 700 of

[0057] Figure 7 An example machine of a computer system 700 is illustrated, wherein the machine is capable of executing a set of instructions that are stored in the computer system's memory (e.g., the memory 704) that instructs the machine to perform any one or more of the methodologies discussed herein. In alternative embodiments, the machine operates as a standalone device or can be connected (e.g., networked) to other machines. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0058] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while referring to a single machine, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0059] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM) and the like), and a data storage device 718.

[0060] Processing device 702 represents a processor, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps described herein.

[0061] The computer system 700 may further include a network interface device 708 for communication via a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generation device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0062] The data storage device 718 may include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable medium) thereon storing one or more sets of instructions 726 or software embodying any or more of the methodologies or functions described herein. The instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media.

[0063] In some embodiments, the instructions 726 include instructions to implement functionality corresponding to the methods of the present disclosure. Although the machine- readable storage medium 724 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processor 702 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0064] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, is considered to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0065] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

[0066] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure described herein.

[0068] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium, etc.

[0069] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to particular example implementations. It will be understood that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. In some instances, reference has been made to particular examples of the disclosure in order to provide a thorough understanding of the application. These examples should not be understood to limit the scope of the present disclosure, as the present disclosure has broad applicability claimed all encompassed therein. Accordingly, the present disclosure and figures should not be viewed as limiting the present disclosure but rather as illustrating the present disclosure.

Claims

1. A digital ring oscillator, wherein the digital ring oscillator is characterized by comprising: A pair of cross-coupled inverters, wherein the input of each of the inverters is coupled to the output of the other inverter at one of two complementary state nodes; Two head transistors are coupled between a supply voltage and the inverter, wherein the head transistors gate the connection of the supply voltage to the inverter; Two pin transistors are coupled between the inverter and ground, wherein the pin transistors gate the connection of the inverter to ground; A delay element, coupled between the state node and the gate of the head and foot transistors; and The state node switches states due to leakage current gated by the head transistor flowing from the supply voltage through the inverter to the state node and due to leakage current gated by the foot transistor flowing from the state node through the inverter to ground; the switching frequency is a function of the leakage current and the leakage current is a function of the temperature of the digital ring oscillator.

2. The digital ring oscillator according to claim 1, wherein the digital ring oscillator is characterized in that the two complementary state nodes are configured to: In response to the output of one of the delay elements being in a logic low state, it is charged to a logic high state; and The output of the other delayed element is discharged to a logic low state in response to the output being in a logic high state.

3. The digital ring oscillator of claim 1, wherein the digital ring oscillator is characterized in that the cross-coupled inverter, the head transistor, and the foot transistor comprise: A first PMOS head transistor has a source coupled to the supply voltage; The first PMOS inverter transistor has a source coupled to the drain of the first PMOS head transistor. The first NMOS inverter transistor has a drain that is coupled to the drain of the first PMOS inverter transistor. The first NMOS pin transistor has a drain coupled to the source of the first NMOS inverter transistor; The second PMOS head transistor has a source coupled to the supply voltage; The second PMOS inverter transistor has a source coupled to the drain of the second PMOS head transistor; The second NMOS inverter transistor has a drain that is coupled to the drain of the second PMOS inverter transistor; and The second NMOS pin transistor has a drain that is coupled to the source of the second NMOS inverter transistor.

4. The digital ring oscillator according to claim 3, wherein the digital ring oscillator is characterized in that: The two state nodes include a first state node and a second state node; The first state node is coupled to the drain of the first PMOS and NMOS inverter transistors and the gate of the second PMOS and NMOS inverter transistors. The second state node is coupled to the drain of the second PMOS and NMOS inverter transistors and the gate of the first PMOS and NMOS inverter transistors. The delay element includes a first delay element and a second delay element; The first delay element is coupled between the first state node and the gates of the first PMOS head transistor and the first NMOS foot transistor; and The second delay element is coupled between the second state node and the gates of the second PMOS head transistor and the second NMOS foot transistor.

5. The digital ring oscillator according to claim 3, wherein the digital ring oscillator is characterized in that the digital ring oscillator further comprises: The third PMOS head transistor is coupled in parallel to the first PMOS head transistor. A fourth PMOS head transistor is coupled in parallel to the second PMOS head transistor, wherein the drain of the third PMOS head transistor is coupled to the gate of the fourth PMOS head transistor, and the drain of the fourth PMOS head transistor is coupled to the gate of the third PMOS head transistor. The third NMOS transistor is coupled in parallel to the first NMOS transistor. and A fourth NMOS transistor is coupled in parallel to the second NMOS transistor, wherein the drain of the third NMOS transistor is coupled to the gate of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is coupled to the gate of the third NMOS transistor.

6. The digital ring oscillator according to claim 1, wherein the digital ring oscillator is characterized in that the digital ring oscillator has an area smaller than that of the trigger on the same integrated circuit die as the digital ring oscillator.

7. The digital ring oscillator according to claim 1, wherein the digital ring oscillator is characterized in that the digital ring oscillator comprises up to 12 transistors and the delay element.

8. An integrated circuit die, wherein the integrated circuit die is characterized in that it comprises: Multiple sensor blocks are distributed at different locations on the die, wherein the sensor blocks include digital ring oscillators that generate oscillating digital signals at a frequency that varies with temperature; and A controller coupled to the sensor block, wherein the controller receives the oscillating digital signal and controls the operation of the integrated circuit die based on the temperature indicated by the frequency of the oscillating digital signal.

9. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the controller is further configured to compare the oscillating digital signal with a reference frequency.

10. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the controller is a Dynamic Voltage and Frequency Scaling (DVFS) controller.

11. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the number of sensor blocks on the integrated circuit die is greater than the number of controllers on the integrated circuit die.

12. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the controller is further configured to disable voltage throttling based on the temperature.

13. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the controller is further configured to determine the difference between the frequencies of the digital oscillation signals of the digital ring oscillator, and the difference indicates the temperature.

14. The integrated circuit die of claim 8, wherein the integrated circuit die is characterized in that the temperature indication is insensitive to changes in supply voltage and process technology.

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