High-speed signal acquisition equipment and automatic test system

Abstract

The utility model provides a high-speed signal acquisition device and an automatic test system in order to solve the problem of insufficient signal-to-noise ratio of signals in the prior art. The equipment comprises an analog front-end module, an analog-to-digital conversion module, a multi-stage storage module, an interface module, a clock synchronization module, a digital correction module and a distributed data processing module. The analog front-end module adopts three-stage processing of a signal conditioning circuit, a differential amplifier and an anti-aliasing filter, low-noise amplification and single-end-to-differential output are realized through the signal conditioning circuit, the bandwidth is accurately limited by combining the anti-aliasing filter, the signal-to-noise ratio of a signal is increased to more than 100dB, common-mode interference and aliasing distortion are effectively inhibited, and the signal-to-noise ratio of the signal is increased to more than 100dB. And the nanosecond baseline error is ensured. The analog-to-digital conversion module adopts a multi-ADC time interleaving architecture and is matched with a phase locking circuit to generate a synchronous clock with the phase difference of 180 degrees / n, so that the equivalent sampling rate is improved to n times of that of a single channel, and meanwhile, the time sequence offset between the channels is eliminated.

Description

TECHNICAL FIELD

[0001] The utility model belongs to signal processing technical field especially relates to a high -speed signal acquisition equipment and automatic test system. BACKGROUND

[0002] With the rapid development of radar detection, 5G communication, medical imaging and other fields, higher requirements are put forward to the sampling rate, dynamic range and anti -interference ability of signal acquisition equipment.

[0003] The existing high -speed signal acquisition equipment is easy to introduce noise in the weak signal conditioning process, and the signal signal -to -noise ratio is insufficient. UTILITY MODEL CONTENTS

[0004] The utility model discloses a high -speed signal acquisition equipment and automatic test system to solve the problem of insufficient signal signal -to -noise ratio in prior art.

[0005] The utility model discloses the technical scheme is:

[0006] A high -speed signal acquisition equipment, including analog front end module, ad conversion module, multistage storage module and interface module, the input of analog front end module is connected external signal source, and the output is connected ad conversion module, the output of ad conversion module is connected multistage storage module, and multistage storage module communicates with external equipment through interface module, still includes:

[0007] Clock synchronization module, digital correction module and distributed data processing module;

[0008] The output of analog front end module is connected to digital correction module in sequence through ad conversion module, and the output of digital correction module is connected distributed data processing module, and the output of distributed data processing module is connected multistage storage module;

[0009] Clock synchronization module is connected with analog front end module, ad conversion module and digital correction module respectively, and is used to provide global synchronous clock signal.

[0010] Further, the analog front end module includes signal conditioning circuit and anti-aliasing filter, wherein the input of the signal conditioning circuit serves as the input of the analog front end module, the output of the signal conditioning circuit is connected with the input of the anti-aliasing filter through a differential amplifier, and the output of the anti-aliasing filter serves as the output of the analog front end module.

[0011] The cutoff frequency of the anti-aliasing filter is 1.2 times the highest frequency of the signal.

[0012] The signal conditioning circuit is used for pre-processing the input raw analog signal, ensuring that the signal has sufficient signal-to-noise ratio and stability before entering the anti-aliasing filter and the analog-to-digital converter;

[0013] The differential amplifier is used for converting a single-ended input signal into a differential signal and amplifying the differential voltage, suppressing common-mode noise.

[0014] The anti-aliasing filter is used to prevent high-frequency noise from aliasing into low-frequency signals, ensuring that the sampled digital signal truly restores the original analog signal.

[0015] Further, the clock synchronization module includes a clock source and a phase-locked loop circuit.

[0016] The output end of the clock source is connected to the reference clock input end of the phase-locked loop circuit, and the synchronous clock output end of the phase-locked loop circuit is connected to the clock input end of the analog-to-digital conversion module, the timing control end of the analog front-end module, and the synchronization signal end of the digital correction module through a coaxial cable, respectively.

[0017] Further, the analog-to-digital conversion module adopts a multi-channel alternate sampling architecture and includes at least two ADC chips connected in parallel.

[0018] The analog input end of each ADC chip is connected in parallel to the output end of the analog front-end module, and the clock input end of each ADC chip receives a sampling clock signal with a phase difference of 180° / n from the clock synchronization module, where n is the number of ADC chips.

[0019] The output end of each ADC chip is connected in parallel to the input end of the digital correction module.

[0020] Further, the digital correction module includes a real-time error compensation circuit and a time delay calibration logic.

[0021] The input end of the real-time error compensation circuit is connected to the output end of the analog-to-digital conversion module, the output end of the real-time error compensation circuit is connected to the input end of the time delay calibration logic, and the output end of the time delay calibration logic is connected to the input end of the distributed data processing module.

[0022] The real-time error compensation circuit is implemented based on FPGA, and the output data of the analog-to-digital conversion module is dynamically adjusted by pre-storing correction coefficients.

[0023] Further, the distributed data processing module is composed of multiple parallel DSP cores.

[0024] The data input end of each DSP core is connected with the output end of the digital correction module through a cross switch matrix, and the data output end of each DSP core shares the data bus of the multi-stage storage module through the cross switch matrix.

[0025] Further, the multi-stage storage module comprises a cache unit and a solid state storage array.

[0026] The input end of the cache unit is connected with the output end of the distributed data processing module, the overflow signal output end of the cache unit is connected with the input end of the solid state storage array, and the output end of the solid state storage array is connected with the interface module through a PCIe interface.

[0027] The cache unit adopts a DDR4 SDRAM.

[0028] Further, the interface module integrates a fiber transceiver and a gigabit Ethernet controller.

[0029] The data input end of the fiber transceiver is directly connected with the real-time data output end of the multi-stage storage module, so as to realize real-time data uploading through an optical module.

[0030] The data input end of the gigabit Ethernet controller is connected with the offline data output end of the solid state storage array, and supports a TCP / IP protocol stack for batch data transmission.

[0031] Based on the same inventive concept, the utility model also provides a kind of automatic test system, and the system includes the high-speed signal acquisition equipment of preceding description.

[0032] The utility model has the beneficial effects that:

[0033] High-precision signal fidelity: the analog front-end module adopts signal conditioning circuit, differential amplifier and anti-aliasing filter three-stage processing, realizes low-noise amplification (1.8nV / √Hz) and single-ended to differential output through signal conditioning circuit, accurately limits bandwidth (cut-off frequency is 1.2 times of signal highest frequency) in combination with anti-aliasing filter, improves signal signal-to-noise ratio to 100dB or more, effectively suppresses common-mode interference and aliasing distortion, and ensures nanosecond-level baseline error.Super high-speed sampling and synchronization: the analog-digital conversion module adopts multi-ADC time interleaving architecture, generates synchronous clock with phase difference 180° / n in cooperation with phase-locked loop, makes equivalent sampling rate increase to n times of single channel, and eliminates inter-channel time offset.Real-time dynamic correction: the error compensation circuit based on FPGA pre-stores non-linear correction coefficient, aligns multi-channel data stream in combination with time delay calibration logic, and eliminates ADC non-linear distortion and sampling time delay error.High-efficiency parallel processing: the distributed data processing module realizes multi-task parallel computation through cross switch matrix, and the processing bandwidth reaches 40GB / s, which significantly improves real-time performance. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0035] Figure 1 It is a high-speed signal acquisition device general block diagram;

[0036] Figure 2 It is an analog front-end module block diagram;

[0037] Figure 3 It is a clock synchronization module block diagram;

[0038] Figure 4 It is an analog-to-digital conversion module block diagram;

[0039] Figure 5 It is a digital correction module block diagram;

[0040] Figure 6 It is a distributed data processing module block diagram;

[0041] Figure 7 It is a multi-level storage module block diagram;

[0042] Figure 8 It is an interface module block diagram. DETAILED DESCRIPTION

[0043] In the description of the present application, it is understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation of the present application.

[0044] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of a specific example are described in the following. Of course, they are only examples, and the purpose is not to limit the present application.

[0045] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0046] The high-speed signal acquisition device disclosed in the embodiment comprises the following components: an analog front-end module 1, a clock synchronization module 2, an analog-to-digital conversion module 3, a digital correction module 4, a distributed data processing module 5, a multi-level storage module 6, and an interface module 7. On the basis of the complete structure of the high-speed signal acquisition device, the embodiment further provides external components: an external signal source and an external device. The high-speed signal acquisition device acquires the signal at the output end of the external signal source, and the external device receives the signal at the output end of the high-speed signal acquisition device. As shown in the accompanying Figure 1 .

[0047] The connection relationship between the components is described in detail below:

[0048] The input end of the analog front-end module 1 is connected to the external signal source, and the output end is connected to the analog-to-digital conversion module 3. The output end of the analog-to-digital conversion module 3 is connected to the multi-level storage module 6, and the multi-level storage module 6 communicates with the external device through the interface module 7. The output end of the analog front-end module 1 is connected to the digital correction module 4 in sequence through the analog-to-digital conversion module 3, the output end of the digital correction module 4 is connected to the distributed data processing module 5, and the output end of the distributed data processing module 5 is connected to the multi-level storage module 6. The clock synchronization module 2 is connected to the analog front-end module 1, the analog-to-digital conversion module 3, and the digital correction module 4, respectively, for providing a global synchronous clock signal.

[0049] The analog front-end module 1 comprises a signal conditioning circuit 101 and an anti-aliasing filter 102. The input end of the signal conditioning circuit 101 serves as the input end of the analog front-end module 1, the output end of the signal conditioning circuit 101 is connected to the input end of the anti-aliasing filter 102 through a differential amplifier 103, and the output end of the anti-aliasing filter 102 serves as the output end of the analog front-end module 1. The cutoff frequency of the anti-aliasing filter is 1.2 times the highest frequency of the signal, which is used to suppress aliasing while preserving the effective components of the signal, and to balance the filter order and hardware complexity. As shown in the accompanying Figure 2 .

[0050] The function of the signal conditioning circuit 101 is to preprocess the input raw analog signal, to ensure that the signal has sufficient signal-to-noise ratio and stability before entering the anti-aliasing filter and the analog-to-digital conversion. The preprocessing includes amplification (to raise the amplitude of the weak signal to meet the input dynamic range of the analog-to-digital conversion module 3), filtering (to preliminarily filter out high-frequency noise or low-frequency interference, to reduce the processing burden of the subsequent module), and impedance matching (to adjust the output impedance of the signal source to match the input impedance of the subsequent circuit, to reduce signal reflection and attenuation). In this embodiment, the signal conditioning circuit 101 selects the AD8421 chip, because the chip has the advantages of low noise (1.8nV / √Hz), high common-mode rejection ratio (CMRR≥100dB@1kHz), adjustable gain (1-1000 times), and support for single-ended to differential output, which is suitable for weak signal amplification.

[0051] The function of the differential amplifier 103 is differential signal amplification (to convert a single-ended input signal into a differential signal and amplify the differential voltage, to suppress common-mode noise (such as electromagnetic interference) and isolation protection (to isolate the front-end sensor from the back-end circuit through the differential input structure, to prevent ground loop interference or high-voltage impact from damaging the equipment)), in high-speed and high-precision systems, differential amplification is a key means to improve the anti-interference ability, especially suitable for long-distance transmission or noisy environments. In this embodiment, the differential amplifier 103 selects the AD8138 chip.

[0052] The function of the anti-aliasing filter 102 is bandwidth limitation (to filter out high-frequency components higher than 1 / 2 of the sampling frequency in the signal according to the Nyquist sampling theorem) and steep roll-off (to use a high-order filter to quickly attenuate near the cutoff frequency, to ensure a narrow transition band and high stopband rejection), to prevent high-frequency noise from aliasing into low-frequency signals, to ensure that the digital signal after sampling truly restores the original analog signal. In this embodiment, the anti-aliasing filter 102 selects the LTC1562 filter.

[0053] The synergistic effect of the signal conditioning circuit 101, the differential amplifier 103, and the anti-aliasing filter 102 is to solve the problem of nanosecond-level error, because the signal conditioning circuit 101 and the differential amplifier 103 reduce the input noise and improve the signal quality, to reduce the baseline error during analog-to-digital conversion, and the anti-aliasing filter 102 accurately limits the signal bandwidth, to avoid high-frequency interference from introducing timing jitter or harmonic distortion in the sampling process.

[0054] The clock synchronization module 2 includes a clock source 201 and a phase-locked loop 202. The output end of the clock source 201 is connected to the reference clock input end of the phase-locked loop 202, and the synchronous clock output end of the phase-locked loop 202 is connected to the clock input end of the analog-to-digital conversion module 3, the timing control end of the analog front-end module 1, and the synchronization signal end of the digital correction module 4 through a coaxial cable, respectively. As shown in the accompanying Figure 3 ​

[0055] The clock source 201 is a core component of the high-speed signal acquisition device for providing a reference clock signal. In this embodiment, the clock source 201 is an AKERS75005-12.000-X-15 patch clock oscillator. The phase-locked circuit 202 is used for phase synchronization and frequency locking: by comparing the phase difference of the reference clock and the feedback clock, the output clock frequency is dynamically adjusted to ensure that the clock signals of multiple modules such as ADC and digital correction unit are strictly synchronized, and the timing deviation is eliminated. In this embodiment, the phase-locked circuit 202 is selected as the Hangzhou Ruimeng MS5351 phase-locked loop chip.

[0056] The analog-to-digital conversion module 3 adopts a multi-channel alternate sampling architecture and includes three ADC chips 301 connected in parallel. The analog input ends of the ADC chips 301 are connected in parallel to the output end of the analog front-end module 1, and the clock input ends of the ADC chips 301 respectively receive the sampling clock signals with a phase difference of 180° / n from the clock synchronization module 2, which are used to realize time-interleaved sampling and reduce the pressure of a single channel, where n is the number of ADC chips 301. The output ends of the ADC chips 301 are connected in parallel to the input end of the digital correction module 4. In this embodiment, the ADC chip 301 is selected as the ADC12_DJ3200. As shown in the accompanying Figure 4

[0057] The digital correction module 4 includes a real-time error compensation circuit 401 and a time delay calibration logic 402. The input end of the real-time error compensation circuit 401 is connected to the output end of the analog-to-digital conversion module 3, the output end of the real-time error compensation circuit 401 is connected to the input end of the time delay calibration logic 402, and the output end of the time delay calibration logic 402 is connected to the input end of the distributed data processing module 5. The real-time error compensation circuit 401 is realized based on FPGA, and dynamically adjusts the output data of the analog-to-digital conversion module 3 by pre-stored correction coefficients. As shown in the accompanying Figure 5

[0058] The real-time error compensation circuit 401 is used for nonlinear error correction: the ADC chip 301 may cause output data distortion due to device nonlinearity during high-speed sampling. The error compensation circuit corrects the nonlinear error of the output data of the ADC chip 301 in real time by using pre-stored correction coefficients (such as a lookup table LUT or polynomial fitting parameters).

[0059] The time delay calibration logic 402 is used for timing alignment: in the multi-ADC alternate sampling architecture, the phase difference of the sampling clock of each ADC chip 301 will cause the time offset of the data output, and the time delay calibration logic aligns the multiple data streams to ensure the timing consistency of the subsequent processing. In this embodiment, the time delay calibration logic 402 is selected as the AD9508 chip.

[0060] ​​The distributed data processing module 5 is composed of multiple parallel DSP cores 501. The data input end of each DSP core 501 is connected with the output end of the digital correction module 4 through a crossbar switch matrix 502, and the data output end of each DSP core 501 shares the data bus of the multi-level storage module 6 through the crossbar switch matrix 502. As shown in the accompanying Figure 6

[0061] The distributed data processing module 5 is the core computing unit of the high-speed signal acquisition device, responsible for parallel processing of the data after digital correction, such as FFT transformation, digital filtering, data compression, etc., and improving the overall processing efficiency through multi-core collaborative work.

[0062] In this embodiment, the DSP core 501 selects a multi-core floating-point DSP (such as TMS320C6678 chip), which is suitable for complex algorithms such as FFT and filtering.

[0063] In this embodiment, the crossbar switch matrix 502 is implemented by an FPGA chip. The crossbar switch matrix 502 is used for conflict management of multi-core shared storage bus. When multiple DSP cores 501 access the multi-level storage module 6 at the same time, the arbitration logic (such as time slice rotation and priority preemption) is used to avoid data blocking caused by bus competition. Technical implementation: a non-blocking architecture is adopted to ensure that the internal bandwidth of the crossbar switch matrix 502 is higher than the peak output sum of all DSP cores.

[0064] The multi-level storage module 6 includes a cache unit 601 and a solid-state storage array 602. The input end of the cache unit 601 is connected with the output end of the distributed data processing module 5, the overflow signal output end of the cache unit 601 is connected with the input end of the solid-state storage array 602, and the output end of the solid-state storage array 602 is connected with the interface module 7 through a PCIe interface. The cache unit 601 adopts DDR4 SDRAM. As shown in the accompanying Figure 7

[0065] The overall role of the multi-level storage module 6 is as follows:

[0066] Data temporary storage and traffic shaping: as a buffer between high-speed data processing and external transmission, it solves the problem of difference between data processing rate and interface transmission rate.

[0067] Data reliability guarantee: through the hierarchical storage strategy, data loss due to sudden load or transmission interruption is avoided. Batch transmission optimization: after accumulating data, the data is transmitted to the external device in batches, reducing the overhead of frequent interface operations.

[0068] ​​The cache unit 601 is used for high-speed data buffering: as a primary storage, a DDR4 SDRAM double data rate synchronous dynamic random access memory is adopted to provide nanosecond-level access delay and tens of GB / s bandwidth, and data streams from the distributed processing module 5 are received in real time.

[0069] The solid-state storage array 602 is used for large-capacity persistent storage: as a secondary storage, a TB-level capacity is provided, and data is stored for a long time for subsequent offline analysis (such as historical backtracking of communication signals). In this embodiment, the solid-state storage array 602 adopts a RAID5 array composed of four Samsung PM1733s, is managed through a Broadcom MegaRAID 9560-16i controller, and provides 24 TB of effective capacity and single-disk fault tolerance.

[0070] The interface module 7 integrates a fiber transceiver 701 and a gigabit Ethernet controller 702. The data input end of the fiber transceiver 701 is directly connected to the real-time data output end of the multi-level storage module 6, and is used to realize real-time data uploading through an optical module. The data input end of the gigabit Ethernet controller 702 is connected to the offline data output end of the solid-state storage array 602, and supports a TCP / IP protocol stack for batch data transmission. As shown in the accompanying drawings. Figure 8

[0071] The fiber transceiver 701 is used for real-time data transmission: real-time data (such as radar signals and high-speed sensor data) output by the multi-level storage module 6 is converted from an electrical signal to an optical signal, and is transmitted at a high speed and low delay through an optical fiber. In this embodiment, the fiber transceiver 701 selects an XW-GD1EQ from Xunwei.

[0072] The gigabit Ethernet controller 702 is used for batch transmission of offline data: offline data (such as historical records and batch analysis results) accumulated in the solid-state storage array 602 is packaged and transmitted to an external device through a TCP / IP protocol stack. In this embodiment, the gigabit Ethernet controller 702 selects a LAN7800 from Microchip.

[0073] Based on the same inventive concept, the embodiment also provides an automatic test system, which comprises the aforementioned high-speed signal acquisition device.

[0074] The high-speed signal acquisition device disclosed in this embodiment realizes high-performance signal acquisition and processing through multi-module collaborative design, and has the following significant advantages:

[0075] High-precision signal fidelity: the analog front-end module 1 adopts an AD8421 chip and an LTC1562 anti-aliasing filter, and combines a differential amplifier AD8138 to improve the signal-to-noise ratio of the input signal to more than 100 dB, effectively suppresses common-mode noise and aliasing interference, and ensures that the baseline error of the signal is less than nanoseconds after amplification, filtering and impedance matching.​

[0076] Ultra-high-speed sampling capability: The analog-to-digital conversion module 3 realizes time-interleaved sampling through a 3-channel ADC 12_DJ3200 chip, and cooperates with a phase-locked clock synchronization technology (MS5351), so that the equivalent sampling rate is increased to 3 times of that of a single channel, and the multi-channel timing deviation is eliminated.

[0077] Real-time correction and parallel processing: The real-time error compensation circuit 401 based on FPGA and the AD9508 time delay calibration logic 402 dynamically correct non-linear distortion and inter-channel time delay; the distributed DSP architecture (TMS320C6678) is combined with a cross switch matrix to realize multi-core parallel FFT / filtering operation, and the processing bandwidth reaches 40 GB / s.

[0078] Hierarchical storage and efficient transmission: The DDR4 cache (nanosecond-level delay) and the PM1733 solid-state array (RAID5) realize data hierarchical buffering and persistent storage, cooperate with the optical fiber (XW-GD1EQ) for real-time transmission and the gigabit Ethernet (LAN7800) for batch return, and meet the low-delay interaction requirements of high-speed and large-capacity data.

Claims

1. A high-speed signal acquisition device, comprising an analog front-end module (1), an analog-to-digital converter (3), a multi-level storage module (6), and an interface module (7), wherein the input end of the analog front-end module (1) is connected to an external signal source, and the output end is connected to the analog-to-digital converter (3), the output end of the analog-to-digital converter (3) is connected to the multi-level storage module (6), and the multi-level storage module (6) communicates with an external device through the interface module (7), characterized in that, Also includes: Clock synchronization module (2), digital correction module (4) and distributed data processing module (5); The output of the analog front-end module (1) is connected to the digital correction module (4) via the analog-to-digital conversion module (3), the output of the digital correction module (4) is connected to the distributed data processing module (5), and the output of the distributed data processing module (5) is connected to the multi-level storage module (6). The clock synchronization module (2) is connected to the analog front-end module (1), the analog-to-digital conversion module (3) and the digital correction module (4) respectively, and is used to provide a global synchronization clock signal.

2. The high-speed signal acquisition device according to claim 1, characterized in that, The analog front-end module (1) includes a signal conditioning circuit (101) and an anti-aliasing filter (102). The input terminal of the signal conditioning circuit (101) serves as the input terminal of the analog front-end module (1). The output terminal of the signal conditioning circuit (101) is connected to the input terminal of the anti-aliasing filter (102) through a differential amplifier (103). The output terminal of the anti-aliasing filter (102) serves as the output terminal of the analog front-end module (1). The cutoff frequency of the anti-aliasing filter is 1.2 times the highest frequency of the signal; The signal conditioning circuit (101) is used to preprocess the input raw analog signal to ensure that the signal has sufficient signal-to-noise ratio and stability before entering the anti-aliasing filter and analog-to-digital conversion; The differential amplifier (103) is used to convert the single-ended input signal into a differential signal, amplify the differential voltage, and suppress common-mode noise; The anti-aliasing filter (102) is used to prevent high-frequency noise from aliasing into low-frequency signals, ensuring that the sampled digital signal truly restores the original analog signal.

3. The high-speed signal acquisition device according to claim 1, characterized in that, The clock synchronization module (2) includes a clock source (201) and a phase-locked circuit (202). The output terminal of the clock source (201) is connected to the reference clock input terminal of the phase-locked circuit (202), and the synchronous clock output terminal of the phase-locked circuit (202) is connected to the clock input terminal of the analog-to-digital conversion module (3), the timing control terminal of the analog front-end module (1), and the synchronous signal terminal of the digital correction module (4) via coaxial cables.

4. The high-speed signal acquisition device according to claim 1, characterized in that, The analog-to-digital conversion module (3) adopts a multi-channel alternating sampling architecture and includes at least two parallel-connected ADC chips (301). The analog input terminals of each ADC chip (301) are connected in parallel to the output terminal of the analog front-end module (1), and the clock input terminals of each ADC chip (301) receive sampling clock signals with a phase difference of 180° / n from the clock synchronization module (2), where n is the number of ADC chips (301). The output terminals of each of the ADC chips (301) are connected in parallel to the input terminal of the digital correction module (4).

5. The high-speed signal acquisition device according to claim 1, characterized in that, The digital correction module (4) includes a real-time error compensation circuit (401) and a time delay calibration logic (402). The input terminal of the real-time error compensation circuit (401) is connected to the output terminal of the analog-to-digital conversion module (3), the output terminal of the real-time error compensation circuit (401) is connected to the input terminal of the time delay calibration logic (402), and the output terminal of the time delay calibration logic (402) is connected to the input terminal of the distributed data processing module (5). The real-time error compensation circuit (401) is implemented based on FPGA and dynamically adjusts the output data of the analog-to-digital conversion module (3) by pre-storing correction coefficients.

6. The high-speed signal acquisition device according to claim 1, characterized in that, The distributed data processing module (5) is composed of multiple parallel DSP cores (501); The data input terminals of each DSP core (501) are connected to the output terminal of the digital correction module (4) through a cross switch matrix (502), and the data output terminals of each DSP core (501) share the data bus of the multi-level storage module (6) through the cross switch matrix (502).

7. The high-speed signal acquisition device according to any one of claims 1-6, characterized in that, The multi-level storage module (6) includes a cache unit (601) and a solid-state storage array (602). The input end of the cache unit (601) is connected to the output end of the distributed data processing module (5), the overflow signal output end of the cache unit (601) is connected to the input end of the solid-state storage array (602), and the output end of the solid-state storage array (602) is connected to the interface module (7) through the PCIe interface. The cache unit (601) uses DDR4 SDRAM.

8. The high-speed signal acquisition device according to claim 7, characterized in that, The interface module (7) integrates a fiber optic transceiver (701) and a gigabit Ethernet controller (702). The data input end of the fiber optic transceiver (701) is directly connected to the real-time data output end of the multi-level storage module (6) for real-time data upload via the optical module. The data input terminal of the Gigabit Ethernet controller (702) is connected to the offline data output terminal of the solid-state storage array (602), supporting batch data transmission via the TCP / IP protocol stack.

9. An automatic testing system, characterized in that, It includes the high-speed signal acquisition device according to any one of claims 1-8.

Images