Inverter circuit of solar energy storage power supply

Abstract

The utility model provides an inverter circuit of a solar energy storage power supply. The inverter circuit comprises a filter circuit electrically connected with the solar energy storage power supply; the metal-oxide-semiconductor MOS tube power driving circuit is electrically connected with the filter circuit; a pulse width modulation (PWM) control circuit; the processing amplification circuit is electrically connected with the PWM control circuit and the MOS tube power driving circuit; and the isolating circuit is electrically connected with the PWM control circuit and the MOS tube power driving circuit. According to the utility model, through accurate control and driving amplification of PWM signals, the MOS tube power driving circuit efficiently completes conversion from direct current to alternating current, and the requirement of a load for alternating current is met.

Description

TECHNICAL FIELD

[0001] The utility model relates to solar current conversion technical field especially relates to a kind of solar energy storage power supply's inverter circuit. BACKGROUND

[0002] Inverter circuit is a kind of power electronic circuit, core function is to convert DC into AC, is widely used in solar power generation, UPS (uninterruptible power supply), electric vehicle, household appliance etc. Its core working principle is to control the fast on-off of electronic switch, and DC is "chopped" and reorganized into AC waveform, inverter efficiency of the inverter circuit in current solar photovoltaic panel energy storage power supply still needs to be improved. SUMMARY

[0003] The utility model discloses a kind of solar energy storage power supply's inverter circuit, the accurate control and driving amplification of PWM signal, make MOS pipe power drive circuit efficiently complete the conversion of DC to AC, meet the demand of load to AC.

[0004] To solve the above technical problems, the technical scheme of the present application is as follows:

[0005] A kind of solar energy storage power supply's inverter circuit, comprising:

[0006] Filter circuit electrically connected with solar energy storage power supply;

[0007] Metal-oxide-semiconductor MOS pipe power drive circuit electrically connected with the filter circuit;

[0008] Pulse width modulation PWM control circuit;

[0009] Processing amplification circuit electrically connected with the PWM control circuit and MOS pipe power drive circuit;

[0010] Isolation circuit electrically connected with the PWM control circuit and MOS pipe power drive circuit;

[0011] Wherein, the input of the filter circuit is solar energy storage power supply DC, and output is smooth DC;

[0012] The input of the MOS pipe power drive circuit is smooth DC, and inverter output is AC;

[0013] The PWM control circuit generates first PWM signal and second PWM signal;

[0014] The processing amplification circuit processes and amplifies first PWM signal, and outputs first PWM signal to drive control the switching sequence of the MOS pipe of MOS pipe power drive circuit;

[0015] The isolation circuit electrically isolates the second PWM signal, outputs the second PWM signal in a phase complementary to the first PWM signal, and controls the switching sequence of the MOS tube of the MOS tube power drive circuit in a split-phase manner.

[0016] Optionally, the filter circuit comprises:

[0017] The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7 are connected in parallel with the solar energy storage power supply.

[0018] Optionally, the MOS tube power drive circuit comprises:

[0019] The upper bridge arm of the full-bridge is electrically connected to the filter circuit and the isolation circuit.

[0020] The lower bridge arm of the full-bridge is electrically connected to the processing and amplifying circuit and the ground terminal.

[0021] The upper bridge arm and the lower bridge arm of the full-bridge inversely output alternating current under the alternating driving of the first PWM signal and the second PWM signal.

[0022] Optionally, the PWM control circuit comprises:

[0023] The control chip;

[0024] The first PWM signal generated by the control chip comprises a first signal PWM-1 and a third signal PWM-3, and the second PWM signal generated by the control chip comprises a second signal PWM-2 and a fourth signal PWM-4; the phases of the first signal PWM-1, the second signal PWM-2, the third signal PWM-3, and the fourth signal PWM-4 are sequentially different by 90 degrees.

[0025] Optionally, the isolation circuit comprises:

[0026] The first optocoupler circuit is electrically connected to the first signal PWM-1.

[0027] The second optocoupler circuit is electrically connected to the third signal PWM-3.

[0028] The first optocoupler circuit optically couples and isolates the input first signal PWM-1 and transmits the isolated fifth signal PWM-A; the second optocoupler circuit optically couples and isolates the input third signal PWM-3 and transmits the isolated seventh signal PWM-C.

[0029] Optionally, the processing and amplifying circuit comprises:

[0030] The comparison circuit is electrically connected to the second signal PWM-2 and the fourth signal PWM-4.

[0031] amplification circuit electrically connected with the comparison circuit;

[0032] The comparison circuit compares the second signal PWM-2 and the fourth signal PWM-4 with a set comparison threshold respectively, and the amplification circuit amplifies the comparison signal output by the comparison circuit to form the sixth signal PWM-B and the eighth signal PWM-D.

[0033] Optionally, the comparison circuit comprises:

[0034] a first comparison circuit electrically connected with the second signal PWM-2;

[0035] a second comparison circuit electrically connected with the fourth signal PWM-4;

[0036] The first comparison circuit compares the second signal PWM-2 with a set comparison threshold and outputs a first comparison signal, and the second comparison circuit compares the fourth signal PWM-4 with a set comparison threshold and outputs a second comparison signal.

[0037] Optionally, a clamping protection diode is arranged between the first comparison circuit and the second comparison circuit.

[0038] Optionally, the amplification circuit comprises:

[0039] a first amplification circuit electrically connected with the first comparison circuit;

[0040] a second amplification circuit electrically connected with the second comparison circuit;

[0041] The first amplification circuit amplifies the first comparison signal to form the sixth signal PWM-B, and the second comparison circuit amplifies the second comparison signal to form the eighth signal PWM-D.

[0042] Optionally, the upper bridge arm of the full-bridge comprises:

[0043] a first full-bridge upper bridge matrix electrically connected with the filter circuit and the fifth signal PWM-A;

[0044] a second full-bridge upper bridge matrix electrically connected with the filter circuit and the seventh signal PWM-C;

[0045] a first full-bridge lower bridge matrix electrically connected with the ground terminal and the sixth signal PWM-B;

[0046] a second full-bridge lower bridge matrix electrically connected with the ground terminal and the eighth signal PWM-D;

[0047] The first full-bridge upper bridge matrix, the second full-bridge upper bridge matrix, the first full-bridge lower bridge matrix and the second full-bridge lower bridge matrix are connected in a bridge mode.

[0048] The utility model discloses beneficial effect is:

[0049] The filter circuit in the scheme carries out the smooth processing to solar energy energy storage power supply direct current, filters the ripple and clutter in input current, provides stable direct current power supply for subsequent MOS pipe power drive circuit, guarantees the quality of inverter output AC, reduces the influence of voltage fluctuation to load.

[0050] The isolation circuit carries out electrical isolation to the second PWM signal, avoids strong and weak electric interference on one hand, guarantees control circuit safety, and the signal of complementary phase of first PWM signal is output on the other hand, makes MOS pipe power drive circuit MOS pipe realize complementary conduction, avoids straight-through short circuit, guarantees the precision of current direction switching in inverter process, improves inverter efficiency.

[0051] From power input filtering, signal generation processing to power drive, form complete inverter link, through the accurate control and drive amplification of PWM signal, make MOS pipe power drive circuit complete the conversion of direct current to alternating current efficiently, satisfy the demand of load to AC. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 It is the schematic diagram of the inverter of the solar energy energy storage power supply of the utility model;

[0053] Figure 2 It is the circuit diagram of filter circuit and full bridge upper bridge arm of the inverter circuit of the solar energy energy storage power supply of the utility model.

[0054] Figure 3 It is the circuit diagram of full bridge lower bridge arm of the inverter circuit of the solar energy energy storage power supply of the utility model.

[0055] Figure 4 It is the circuit diagram of PWM control circuit of the inverter circuit of the solar energy energy storage power supply of the utility model.

[0056] Figure 5 It is the circuit diagram of first opto-coupler circuit of the inverter circuit of the solar energy energy storage power supply of the utility model.

[0057] Figure 6 It is the circuit diagram of second opto-coupler circuit of the inverter circuit of the solar energy energy storage power supply of the utility model.

[0058] Figure 7 It is the circuit diagram of processing amplification circuit of the inverter circuit of the solar energy energy storage power supply of the utility model. DETAILED DESCRIPTION

[0059] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0060] like Figures 1-7 As shown, an embodiment of this utility model proposes an inverter circuit for a solar energy storage power supply, comprising:

[0061] A filter circuit electrically connected to the solar energy storage power supply;

[0062] The metal-oxide-semiconductor MOSFET power drive circuit is electrically connected to the filter circuit.

[0063] Pulse Width Modulation (PWM) control circuit;

[0064] A processing amplifier circuit electrically connected to the PWM control circuit and the MOS transistor power drive circuit;

[0065] An isolation circuit electrically connected to the PWM control circuit and the MOS transistor power drive circuit;

[0066] The input of the filter circuit is DC power from the solar energy storage power supply, and the output is smoothed DC power.

[0067] The input of the MOS transistor power drive circuit is smooth DC power, and the inverter output is AC power.

[0068] The PWM control circuit generates a first PWM signal and a second PWM signal;

[0069] The processing and amplification circuit processes and amplifies the first PWM signal, and outputs the first PWM signal to drive and control the switching sequence of the MOSFETs in the MOSFET power drive circuit.

[0070] The isolation circuit electrically isolates the second PWM signal and outputs the second PWM signal with a phase complementary to the first PWM signal, thereby controlling the switching sequence of the MOSFETs in the MOSFET power drive circuit.

[0071] In this embodiment, the filtering circuit smooths the DC power from the solar energy storage power supply, filtering out ripple and noise in the input current to provide a stable DC power supply for the subsequent MOSFET power drive circuit, ensuring the quality of the AC power output from the inverter and reducing the impact of voltage fluctuations on the load. The processing amplification circuit processes and amplifies the first PWM signal, enhancing the signal driving capability, ensuring the accuracy of the MOSFET switching action, optimizing the switching timing control, and improving the circuit response speed.

[0072] The isolation circuit electrically isolates the second PWM signal, avoids strong and weak electrical interference on one hand, and guarantees the safety of the control circuit; on the other hand, the signal in the complementary phase of the first PWM signal is outputted, so that the MOS tube of the MOS tube power drive circuit realizes complementary conduction, avoids direct short circuit, ensures the accurate switching of the current direction in the inverting process, and improves the inverting efficiency.

[0073] From the power input filtering, signal generation processing to power drive, a complete inverting link is formed. Through the accurate control and drive amplification of the PWM signal, the MOS tube power drive circuit efficiently completes the conversion from direct current to alternating current, and meets the demand of the load for alternating current.

[0074] As shown in Figure 4 The PWM control circuit comprises:

[0075] a control chip;

[0076] The first PWM signal generated by the control chip comprises a first signal PWM-1 and a third signal PWM-3, and the second PWM signal generated by the control chip comprises a second signal PWM-2 and a fourth signal PWM-4; the phases of the first signal PWM-1, the second signal PWM-2, the third signal PWM-3 and the fourth signal PWM-4 are sequentially different by 90 degrees.

[0077] Specifically, the control chip is U1, and the control chip is built-in with a timing clock to generate a PWM signal.

[0078] In the inverting circuit of the solar energy storage power supply in this embodiment, the PWM signals with the specific phase difference can be used to control the switching sequence of the MOS tube, so that the output alternating current waveform is closer to a sine wave. Compared with the traditional square wave output, the sine wave output can reduce the harmonic content and reduce the interference on the load device.

[0079] The four PWM signals with the phase difference of 90 degrees can make the current and voltage distribution in the circuit more uniform, reduce electromagnetic radiation and interference. The control chip is built-in with a timing clock to generate a PWM signal, which reduces the dependence on external clock sources and reduces the risk of system crash caused by external clock failure. Even in a harsh working environment, the built-in timing clock can guarantee the stable output of the PWM signal, so that the system has stronger fault tolerance.

[0080] As shown in Figures 5-6 The isolation circuit comprises:

[0081] a first optocoupler circuit electrically connected with the first signal PWM-1;

[0082] The second optocoupler circuit is electrically connected with the third signal PWM-3;

[0083] The first optocoupler circuit optically couples the input first signal PWM-1 and transmits the fifth signal PWM-A after isolation; and the second optocoupler circuit optically couples the input third signal PWM-3 and transmits the seventh signal PWM-C after isolation.

[0084] Specifically, the first optocoupler circuit comprises an optocoupler chip U5, a resistor R41 and a resistor R62. The input first signal PWM-1 is connected to the pin 2 of the U5 through the R41, and the R62 is grounded to realize pull-down voltage stabilization and stabilize the input signal level. The first signal PWM-1 is converted into an optical signal by the internal light-emitting diode of the U5, and the fifth signal PWM-A after isolation is output by the internal photosensitive transistor after transmission through the internal optical path, so that the electrical isolation of the first signal is completed.

[0085] In the embodiment, the optocoupler chip U5 cuts off the electrical connection between the input and the output, prevents the high voltage of the later-stage MOS tube power drive circuit from being transmitted to the front-stage control circuit, avoids the low-voltage elements such as the control chip from being damaged, improves the circuit safety, and is suitable for the inverter system with strong electricity and weak electricity mixed.

[0086] The second optocoupler circuit comprises an optocoupler chip U6, a resistor R39 and a resistor R61. The third signal PWM-3 is connected to the pin 2 of the U6 through the resistor R39 (current limiting), and the R61 is grounded to stabilize the input signal level. The PWM-3 is converted into an optical signal by the internal light-emitting diode of the U6, and the seventh signal PWM-C after isolation is output by the internal photosensitive transistor after transmission through the optical path, so that the optical coupling isolation of the third signal PWM-3 is realized.

[0087] In the embodiment, the optocoupler chips U5 and U6 cut off the direct electrical connection between the input and the output through the conversion of "electricity-optical-electricity". The high voltage of the later-stage MOS tube power drive circuit cannot be transmitted to the front-stage control circuit, so that the low-voltage elements such as the control chip are prevented from being damaged due to the high voltage impact. The photoelectric conversion mechanism in the optocoupler can effectively isolate the external electromagnetic interference. Even if there is high-frequency noise or voltage mutation in the circuit, the PWM-A and PWM-C signals after isolation can still remain pure, so that the accuracy of signal transmission is ensured and the probability of misoperation is reduced.

[0088] As shown in Figure 7 In an optional embodiment of the utility model, the processing amplification circuit comprises:

[0089] The comparison circuit is electrically connected with the second signal PWM-2 and the fourth signal PWM-4.

[0090] An amplification circuit electrically connected with the comparison circuit;

[0091] The comparison circuit compares the second signal PWM-2 and the fourth signal PWM-4 with a set comparison threshold respectively, and the amplification circuit amplifies the comparison signal output by the comparison circuit to form the sixth signal PWM-B and the eighth signal PWM-D.

[0092] The comparison circuit comprises:

[0093] A first comparison circuit electrically connected with the second signal PWM-2;

[0094] A second comparison circuit electrically connected with the fourth signal PWM-4;

[0095] The first comparison circuit compares the second signal PWM-2 with a set comparison threshold and outputs a first comparison signal, and the second comparison circuit compares the fourth signal PWM-4 with a set comparison threshold and outputs a second comparison signal.

[0096] A clamping protection diode is arranged between the first comparison circuit and the second comparison circuit.

[0097] The amplification circuit comprises:

[0098] A first amplification circuit electrically connected with the first comparison circuit;

[0099] A second amplification circuit electrically connected with the second comparison circuit;

[0100] The first amplification circuit amplifies the first comparison signal to form the sixth signal PWM-B, and the second amplification circuit amplifies the second comparison signal to form the eighth signal PWM-D.

[0101] Specifically, the first comparison circuit comprises a voltage comparator U8A, a resistor R27, a resistor R25, a resistor R51, a resistor R52 and a diode D10. The second signal PWM-2 is connected to the 6th pin (inverted input end) of the U8A through the R27. The R51 and the R52 provide a set comparison threshold for the 7th pin (same phase input end) of the U8A. The U8A compares the input second signal PWM-2 with the threshold value and outputs the first comparison signal to the 1st pin. The diode D10 is connected across the 7th pin of the U8A and the ground, which plays a clamping protection role and prevents the input voltage from being damaged by abnormality.

[0102] The second comparison circuit comprises a voltage comparator U8B, a resistor R20, a resistor R26 and a diode D12. The fourth signal PWM-4 is connected to the 4th pin (inverted input end) of U8B through R20, and R26 provides a comparison threshold for the 5th pin (non-inverted input end) of U8B. U8B compares the fourth signal PWM-4 with the threshold, and outputs a second comparison signal to the 2nd pin. The diode D12 is connected between the signal paths of U8A and U8B, and further clamps protection is provided to avoid the influence of voltage mutation on the circuit.

[0103] The first amplification circuit comprises a transistor Q4, a transistor Q5 and a resistor R48. The first comparison signal output by U8A is connected to the base of Q4, and is amplified through the push-pull structure composed of Q4 and Q5. A +12V power supply is provided for Q4, and Q5 is grounded, so that the sixth signal PWM-B is finally amplified to drive the subsequent circuit.

[0104] The second amplification circuit comprises a transistor Q6, a transistor Q7 and a resistor R47. The second comparison signal output by U8B is input to the base of Q6, and is amplified through the push-pull structure composed of Q6 and Q7. A +12V power supply is provided for Q6, and Q7 is grounded, so that the eighth signal PWM-D is formed after amplification and is used to drive the subsequent power device.

[0105] In this embodiment, the processing amplification circuit realizes signal threshold comparison through a comparator, and combines a transistor push-pull amplification, so that the PWM-B and PWM-D signals output have sufficient driving capability, and the clamping diode improves the impact resistance of the circuit.

[0106] As shown in Figure 2 In an optional embodiment of the utility model, the filter circuit comprises:

[0107] A first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7 are connected in parallel with the direct current of the solar energy storage power supply.

[0108] Specifically, the filter circuit further comprises: the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are connected in parallel with the direct current of the solar energy storage power supply, and the first current limiting resistor R9 and the second current limiting resistor R19 are connected to the gate of the MOS tube of the MOS tube power drive circuit.

[0109] In the embodiment, the first capacitor C1 to the seventh capacitor C7 are connected in parallel, and the ripple and fluctuation in the input solar energy storage power supply direct current are filtered out by using the "passing alternating current and blocking direct current" characteristic of the capacitor. The multiple capacitors work together to increase the equivalent capacitance value, so that the output direct current is smoother, and a stable direct current power supply is provided for the subsequent MOS power drive circuit, so that the voltage fluctuation does not affect the inverter effect. The first current-limiting resistor R9 and the second current-limiting resistor R19 limit the impact current at the starting moment of the circuit. For example, when the capacitor is charged, the current-limiting resistor can avoid damaging the capacitor or the subsequent components due to the large current, prolong the service life of the circuit, and improve the system reliability. The stable direct current power supply after filtering can make the MOS power drive circuit work more stably. The stable voltage input reduces the switching loss and performance fluctuation of the MOS tube caused by voltage fluctuation, and indirectly improves the conversion efficiency and working stability of the inverter circuit of the solar energy storage power supply.

[0110] As shown in Figures 2-3 , in an optional embodiment of the utility model, the MOS power drive circuit comprises:

[0111] The full-bridge upper bridge arm is electrically connected with the filter circuit and the isolation circuit respectively.

[0112] The full-bridge lower bridge arm is electrically connected with the processing amplification circuit and the ground terminal.

[0113] The full-bridge upper bridge arm and the full-bridge lower bridge arm are inversely driven to output alternating current under the alternating driving of the first PWM signal and the second PWM signal.

[0114] The full-bridge upper bridge arm comprises:

[0115] The first full-bridge upper bridge matrix is electrically connected with the filter circuit and the fifth signal PWM-A.

[0116] The second full-bridge upper bridge matrix is electrically connected with the filter circuit and the seventh signal PWM-C.

[0117] The first full-bridge lower bridge matrix is electrically connected with the ground terminal and the sixth signal PWM-B.

[0118] The second full-bridge lower bridge matrix is electrically connected with the ground terminal and the eighth signal PWM-D.

[0119] The first full-bridge upper bridge matrix, the second full-bridge upper bridge matrix, the first full-bridge lower bridge matrix and the second full-bridge lower bridge matrix are connected in bridge mode.

[0120] Specifically, the first full-bridge upper bridge matrix includes MOS tubes Q1, Q2, Q3, Q4, Q5, Q6 and Q7, which are connected in series through resistors (such as R2, R3 and R4). The first full-bridge upper bridge matrix is electrically connected with an output end of a filter circuit to receive a stable direct current power supply; and receives a fifth signal PWM-A (input through D1 and R5) output by an isolation circuit as a driving control signal.

[0121] The second full-bridge upper bridge matrix includes MOS tubes Q21, Q22, Q23, Q24, Q25, Q26 and Q27, which are connected in series through resistors (such as R25, R26 and R27). The second full-bridge upper bridge matrix is also connected with the output end of the filter circuit to obtain the direct current power supply; and receives a seventh signal PWM-C (input through D3 and R11) output by the isolation circuit for driving control.

[0122] The first full-bridge lower bridge matrix includes MOS tubes Q11, Q12, Q13, Q14, Q15, Q16 and Q17, which are connected in series through resistors (such as R13, R14 and R15). One end of the first full-bridge lower bridge matrix is grounded, and the other end receives a sixth signal PWM-B (input through D2 and R15) output by a processing amplification circuit for driving control.

[0123] The second full-bridge lower bridge matrix includes MOS tubes Q31, Q32, Q33, Q34, Q35, Q36 and Q37, which are connected in series through resistors (such as R37, R38 and R39). One end of the second full-bridge lower bridge matrix is grounded, and the other end receives an eighth signal PWM-D (input through D4 and R41) output by the processing amplification circuit for driving control.

[0124] The first full-bridge upper bridge matrix, the second full-bridge upper bridge matrix, the first full-bridge lower bridge matrix and the second full-bridge lower bridge matrix are connected in a bridge mode to form a complete full-bridge topology. The first full-bridge upper bridge matrix (Q1-Q7) and the first full-bridge lower bridge matrix (Q11-Q17), and the second full-bridge upper bridge matrix (Q21-Q27) and the second full-bridge lower bridge matrix (Q31-Q37) respectively form a bridge arm. Under the alternating driving of a first PWM signal (PWM-A, PWM-C) and a second PWM signal (PWM-B, PWM-D), the MOS tubes of the full-bridge upper bridge arm and the full-bridge lower bridge arm are turned on / off in a specific time sequence. For example, when the PWM-A drives the MOS tubes of the upper bridge arm to be turned on and the PWM-B drives the MOS tubes of the lower bridge arm to be turned off, a current forms a path through the upper bridge arm, the load and the lower bridge arm; after the signals are reversed, the direction of the current is changed, and finally an alternating current is output to realize the energy conversion from direct current to alternating current.

[0125] The filter circuit of the inverter circuit of the solar energy storage power supply utilizes a combination of multiple capacitors in parallel and current limiting resistors to filter out the ripple and noise of the input solar energy storage power supply DC, smooth the DC voltage, and provide a stable power supply for the MOS power drive circuit, reduce the impact of voltage fluctuations on the load, and improve the quality of the inverter output AC. The control chip generates PWM signals with a phase difference of 90°, making the MOS switch sequence more accurate, and the output AC waveform close to a sine wave, reducing harmonic content and reducing interference with the load device. The threshold comparison of the PWM signal is compared by the comparison circuit, combined with the push-pull amplification of the triode, to enhance the signal driving ability, ensure the accuracy of the MOS switch action, optimize the switch timing, and improve the circuit response speed. The optocoupler isolation circuit cuts off the electrical connection between strong and weak electricity, prevents the high voltage from damaging the control chip, and at the same time, through the "electricity-optical-electricity" conversion, it isolates electromagnetic interference, ensures the purity of the PWM signal transmission, reduces the misoperation, and is suitable for complex inverter systems with strong and weak electricity mixed. The MOS power drive circuit adopts full-bridge topology, and the upper and lower bridge arms are driven by complementary phase PWM signals, realizing the complementary conduction of MOS tubes and avoiding short circuit. Through specific timing control of current direction switching, it efficiently completes the conversion from DC to AC, meeting the demand of the load for AC.

[0126] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, these improvements and refinements should also be considered within the scope of the present application.

Claims

1. An inverter circuit for a solar energy storage power supply, characterized by, include: A filter circuit electrically connected to the solar energy storage power supply; The metal-oxide-semiconductor MOSFET power drive circuit is electrically connected to the filter circuit. Pulse Width Modulation (PWM) control circuit; A processing amplifier circuit electrically connected to the PWM control circuit and the MOS transistor power drive circuit; An isolation circuit electrically connected to the PWM control circuit and the MOS transistor power drive circuit; The input of the filter circuit is DC power from the solar energy storage power supply, and the output is smoothed DC power. The input of the MOS transistor power drive circuit is smooth DC power, and the inverter output is AC power. The PWM control circuit generates a first PWM signal and a second PWM signal; The processing and amplification circuit processes and amplifies the first PWM signal, and outputs the first PWM signal to drive and control the switching sequence of the MOSFETs in the MOSFET power drive circuit. The isolation circuit electrically isolates the second PWM signal and outputs the second PWM signal with a phase complementary to the first PWM signal, thereby controlling the switching sequence of the MOSFETs in the MOSFET power drive circuit.

2. The inverter circuit of a solar energy power storage source according to claim 1, characterized by: The filtering circuit includes: The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7 are connected in parallel with the DC power supply of the solar energy storage power source, respectively.

3. The inverter circuit of a solar energy power storage source according to claim 1, characterized by: The MOSFET power drive circuit includes: The upper bridge arm of the full bridge is electrically connected to the filter circuit and the isolation circuit, respectively; The lower bridge arm of the full-bridge circuit is electrically connected to the processing amplifier circuit and the ground terminal; The upper and lower arms of the full-bridge inverter output AC power under the alternating drive of the first and second PWM signals.

4. The inverter circuit of a solar energy power storage source according to claim 3, characterized by: The PWM control circuit includes: Control chip; The first PWM signal generated by the control chip includes a first signal PWM-1 and a third signal PWM-3, and the second PWM signal generated includes a second signal PWM-2 and a fourth signal PWM-4; the phases of the first signal PWM-1, the second signal PWM-2, the third signal PWM-3 and the fourth signal PWM-4 are respectively 90 degrees apart.

5. The inverter circuit of a solar energy power storage source according to claim 4, characterized by: The isolation circuit includes: The first optocoupler circuit is electrically connected to the first signal PWM-1; The second optocoupler circuit is electrically connected to the third signal PWM-3; Specifically, the first optocoupler circuit performs optocoupler isolation on the input first signal PWM-1 and outputs the isolated fifth signal PWM-A; the second optocoupler circuit performs optocoupler isolation on the input third signal PWM-3 and outputs the isolated seventh signal PWM-C.

6. The inverter circuit of a solar energy power storage source according to claim 5, characterized by: The processing amplification circuit includes: A comparator circuit electrically connected to the second signal PWM-2 and the fourth signal PWM-4; An amplifier circuit electrically connected to the comparison circuit; The comparison circuit compares the second signal PWM-2 and the fourth signal PWM-4 with a set comparison threshold, and the amplifier circuit amplifies the comparison signal output by the comparison circuit to form the sixth signal PWM-B and the eighth signal PWM-D.

7. The inverter circuit of a solar energy power storage source according to claim 6, characterized by: The comparison circuit includes: A first comparator circuit electrically connected to the second signal PWM-2; A second comparison circuit electrically connected with the fourth signal PWM-4; The first comparison circuit compares the second signal PWM-2 with a set comparison threshold, and outputs a first comparison signal; and the second comparison circuit compares the fourth signal PWM-4 with the set comparison threshold, and outputs a second comparison signal.

8. The inverter circuit of a solar energy power storage source according to claim 7, characterized by: A clamping protection diode is arranged between the first comparison circuit and the second comparison circuit.

9. The inverter circuit of a solar energy power storage source according to claim 7, characterized by: The amplification circuit comprises: A first amplification circuit electrically connected with the first comparison circuit; A second amplification circuit electrically connected with the second comparison circuit; The first amplification circuit amplifies the first comparison signal to form a sixth signal PWM-B; and the second amplification circuit amplifies the second comparison signal to form an eighth signal PWM-D.

10. The inverter circuit of a solar energy power storage source according to claim 6, characterized by: The upper bridge arm of the full-bridge comprises: A first full-bridge upper bridge matrix electrically connected with the filter circuit and the fifth signal PWM-A; A second full-bridge upper bridge matrix electrically connected with the filter circuit and the seventh signal PWM-C; A first full-bridge lower bridge matrix electrically connected with the ground terminal and the sixth signal PWM-B; A second full-bridge lower bridge matrix electrically connected with the ground terminal and the eighth signal PWM-D; The first full-bridge upper bridge matrix, the second full-bridge upper bridge matrix, the first full-bridge lower bridge matrix, and the second full-bridge lower bridge matrix are connected in a bridge mode.

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