High surge MOS device

Abstract

The utility model relates to a high surge MOS device comprising at least two gate structures, a second conductive type body region, a first conductive type first source region and a first conductive type second source region, the number of the gate structures is at least two, and the second conductive type body region is arranged between the two gate structures. The first conduction type first source regions are arranged in the first direction, the first conduction type second source regions are arranged in the first direction, and the first conduction type first source regions and the first conduction type second source regions are located at different positions in the second direction. The first conduction type first source regions and the second conduction type second source regions are sequentially arranged in a staggered mode in the first direction, and the first conduction type first source regions are connected with the adjacent first conduction type second source regions. And the anti-surge capability of the MOS device is effectively enhanced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor device, in particular to a kind of high surge MOS device. BACKGROUND

[0002] MOS (Metal Oxide Semiconductor) device is an important power semiconductor device, widely used in power electronic equipment, industrial control system and consumer electronics, and it is widely concerned because of high switching efficiency, low power consumption and excellent current control performance. In practical application, MOS device usually needs to work in high-voltage, high-surge current environment, so its surge resistance directly affects the reliability and service life of the device.

[0003] The existing MOS device, as shown in Figure 1 Usually adopts strip cell structure, sets up strip source region structure 14 in body region structure 15, and improves the performance of the device by optimizing the doping parameters and layout of body region structure 15 and source region structure 14.

[0004] However, in this design, the junction area of the body region structure is relatively small, so the P / N junction area is relatively small. When it needs to be used in high-surge current and high-voltage impact environment, the carrier capacity of P / N junction is limited, which cannot effectively disperse surge charge, so as to easily cause local overheating or even device breakdown, which significantly affects the surge resistance of MOS device, so it is necessary to provide a MOS device that can significantly improve the surge resistance of the device to adapt to the application environment of high-surge current and high-voltage impact. SUMMARY

[0005] Therefore, the purpose of the utility model is to provide a high surge MOS device to solve the technical problems of the prior art that the junction area of the body region is relatively small, the P / N junction area is relatively small, and the surge resistance is poor.

[0006] The utility model provides a kind of high surge MOS device, comprising:

[0007] Gate structure is at least provided with two;

[0008] Second conductive type body region is set between two gate structures;

[0009] First conductive type first source region is set in second conductive type body region and is provided with multiple;

[0010] First conductive type second source region is set in second conductive type body region and is provided with multiple;

[0011] The first conductive type first source regions are arranged along a first direction, the first conductive type second source regions are arranged along the first direction, the first conductive type first source regions and the first conductive type second source regions are located at different positions along a second direction, the first conductive type first source regions and the second conductive type second source regions are arranged in sequence along the first direction, and the first conductive type first source regions and adjacent first conductive type second source regions are connected.

[0012] Optionally, a width of an overlapping part of the first conductive type first source regions and the first conductive type second source regions along the second direction is less than half of a width of the first conductive type first source regions or / and the first conductive type second source regions along the second direction.

[0013] Optionally, the first conductive type first source regions and the first conductive type second source regions are arranged in an S shape along the first direction.

[0014] Optionally, the first conductive type first source regions are arranged in two rows, the first conductive type second source regions are located between the two rows of first conductive type first source regions, and each row of first conductive type first source regions is arranged in sequence with the first conductive type second source regions along the first direction.

[0015] Optionally, the first conductive type first source regions and the first conductive type second source regions have the same size.

[0016] Optionally, the device further comprises:

[0017] a first conductive type substrate;

[0018] a first conductive type epitaxial layer arranged on a front surface of the first conductive type substrate, the gate structure is arranged on a front surface of the first conductive type epitaxial layer, the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and in the first conductive type epitaxial layer, and the first conductive type first source regions and the first conductive type second source regions are located in the second conductive type body region.

[0019] Optionally, a back surface of the second conductive type body region is provided with a first conductive type high resistance region, and a resistivity of the first conductive type high resistance region is higher than a resistivity of the first conductive type epitaxial layer.

[0020] Optionally, the device further comprises a second conductive type extension column, the second conductive type extension column is arranged in the first conductive type high resistance region, and the second conductive type extension column is connected with the second conductive type body region and the first conductive type epitaxial layer respectively.

[0021] Optionally, at least two of the second-conductivity-type extension columns corresponding to each of the second-conductivity-type body regions are arranged in the first-conductivity-type high-resistance region in a first direction.

[0022] Optionally, a front surface of the first-conductivity-type epitaxial layer is provided with an insulating medium layer covering the gate structure, a front surface of the insulating medium layer is provided with a front surface metal layer, a back surface of the first-conductivity-type substrate is provided with a back surface metal layer, and the front surface metal layer extends to the second-conductivity-type body region and is connected to the second-conductivity-type body region.

[0023] The technical scheme of the utility model has the advantages of:

[0024] The high-surge MOS device has the following advantages: the first-conductivity-type first source region and the first-conductivity-type second source region are arranged in an interlaced manner, so that the junction area of the second-conductivity-type body region in the MOS device can be significantly increased, the junction area of the P / N junction can be effectively increased, the anti-surge capability of the MOS device can be effectively enhanced, the MOS device can be applied to a higher-surge-current and high-voltage-impact application environment, and the adaptability is wider. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the drawings needed in the embodiments will be briefly introduced below, and it should be understood that the following drawings only show some embodiments of the utility model, and should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of the drawings.

[0026] Figure 1 It is a schematic diagram of prior art in the background technology of the utility model;

[0027] Figure 2 It is a structural schematic diagram of the high-surge MOS device in the utility model;

[0028] Figure 3 It is a sectional structure schematic diagram of the high-surge MOS device in the utility model;

[0029] Figure 4 It is a step diagram of the preparation method of the high-surge MOS device in the utility model.

[0030] EXPLANATION OF REFERENCE NUMERALS:

[0031] 1, gate structure; 2, second conductive type body region; 3, first conductive type first source region; 4, first conductive type second source region; 5, first conductive type substrate; 6, first conductive type epitaxial layer; 7, first conductive type high resistance region; 8, second conductive type extension column; 9, gate oxide layer; 10, insulating medium layer; 11, front metal layer; 12, back metal layer; 13, metal contact via; 14, source region structure; 15, body region structure. DETAILED DESCRIPTION

[0032] The specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the description of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0033] Unless otherwise explicitly specified and limited, the terms "arranged", "mounted", "connected" and the like should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0034] The terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, and are only for the convenience of description and simplification of description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0035] The terms "first", "second", "third" and the like are only for distinguishing similar attributes of elements, and do not indicate or imply relative importance or a particular order.

[0036] The terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, in addition to including the listed elements, other elements not explicitly listed can also be included.

[0037] Example 1

[0038] The high surge MOS device includes an N-type MOS device and a P-type MOS device, for the N-type MOS device, the first conductive type is N-type, and the second conductive type is P-type; for the P-type MOS device, the first conductive type is P-type, and the second conductive type is N-type, in this embodiment, taking the N-type MOS device as an example.

[0039] Referring to Figure 2 and Figure 3 The utility model provides a kind of high surge MOS device, including gate structure 1, second conductive type body area 2, first conductive type first source area 3 and first conductive type second source area 4, wherein at least two are provided for gate structure 1, and gap is left between adjacent two gate structure 1 to set second conductive type body area 2, first conductive type first source area 3 and first conductive type second source area 4, second conductive type body area 2 is arranged between adjacent two gate structure 1, and second conductive type body area 2 is arranged between adjacent two gate structure 1;

[0040] First conductive type first source area 3 and first conductive type second source area 4 are all arranged in second conductive type body area 2 and are all provided with multiple, multiple first conductive type first source area 3 is arranged along first direction, multiple first conductive type second source area 4 is arranged along first direction, first conductive type first source area 3 and first conductive type second source area 4 are in different positions in second direction, i.e. two rows of first conductive type first source area 3 and first conductive type second source area 4 are parallel but not coincident arrangement, first conductive type first source area 3 and second conductive type second source area 4 are sequentially staggered along first direction, so that there is a second conductive type second source area 4 between adjacent two first conductive type first source area 3, there is a second conductive type first source area 3 between adjacent two first conductive type second source area 4, first conductive type first source area 3 and adjacent two first conductive type second source area 4 are connected, first conductive type second source area 4 and adjacent two first conductive type first source area 3 are connected, so that multiple first conductive type first source area 3 and multiple first conductive type second source area 4 are arranged along first direction S type.

[0041] By setting first conductive type first source area 3 and first conductive type second source area 4, and first conductive type first source area 3 and first conductive type second source area 4 are staggered arrangement, so that the junction area of second conductive type body area 2 in MOS device can be significantly increased, and the junction area of P / N junction is effectively increased, the surge resistance of MOS device is effectively enhanced, so that it can adapt to higher surge current and high pressure impact application environment, and the adaptability is wider.

[0042] As a specific embodiment, referring to Figure 2As shown, the first conductive type first source region 3 and the first conductive type second source region 4 have the same size, and the first conductive type first source region 3 and the first conductive type second source region 4 have repeated parts in the second direction, and the width of the overlapping part is less than half of the width of the first conductive type first source region 3 or / and the first conductive type second source region 4 in the second direction. Through such arrangement, the first conductive type first source region 3 and the first conductive type second source region 4 can be connected, and the junction area of the P / N junction can be maximized to ensure the strongest surge resistance of the MOS device.

[0043] As another embodiment, the first conductive type first source region 3 is arranged in two rows, and the two rows of first conductive type first source regions 3 are arranged in the first direction, and the first conductive type second source region 4 is located between the two rows of first conductive type first source regions 3. Each row of first conductive type first source regions 3 is arranged in the first direction with a plurality of first conductive type second source regions 4, so that each first conductive type second source region 4 can be inserted between two adjacent first conductive type first source regions 3 in each row of first conductive type first source regions 3, and the overlapping part of the first conductive type second source region 4 and the two rows of first conductive type first source regions 3 in the second direction is less than half of the width of the first conductive type first source region 3 in the second direction. Further increase the junction area of the P / N junction, effectively enhance the surge resistance of the MOS device.

[0044] As a specific embodiment, the high surge MOS device further comprises a first conductive type substrate 5 and a first conductive type epitaxial layer 6, wherein the first conductive type substrate 5 selects N-type silicon as the substrate, the first conductive type epitaxial layer 6 is arranged on the front surface of the first conductive type substrate 5, the gate structure 1 is arranged on the front surface of the first conductive type epitaxial layer 6, and a plurality of gate structures 1 are arranged on the front surface of the first conductive type epitaxial layer 6,

[0045] The second conductive type body region 2 is arranged on the front surface of the first conductive type epitaxial layer 6 and arranged in the first conductive type epitaxial layer 6, and the second conductive type body region 2 is arranged between two adjacent gate structures 1. The first conductive type first source region 3 and the first conductive type second source region 4 are located in the second conductive type body region 2;

[0046] The front surface of the first conductive type epitaxial layer 6 is provided with an insulating medium layer 10, and the insulating medium layer 10 covers the gate structure 1. The front surface of the insulating medium layer 10 is provided with a front metal layer 11, and the back surface of the first conductive type substrate 5 is provided with a back metal layer 12. The front metal layer 11 extends to the second conductive type body region 2 and is connected to the second conductive type body region 2

[0047] Further, the back surface of the second-conductivity-type body region 2 is provided with a first-conductivity-type high-resistance region 7, the first-conductivity-type high-resistance region 7 is located in the first-conductivity-type epitaxial layer 6, the first-conductivity-type high-resistance region 7 has a higher resistivity than the first-conductivity-type epitaxial layer 6, and the first-conductivity-type high-resistance region 7 is provided with a second-conductivity-type extension column 8, the second-conductivity-type extension column 8 extends towards the second-conductivity-type body region 2 until connecting with the second-conductivity-type body region 2, and the second-conductivity-type extension column 8 also extends towards the first-conductivity-type substrate 5 until extending into the first-conductivity-type epitaxial layer 6 and connecting with the first-conductivity-type epitaxial layer 6;

[0048] By providing the first-conductivity-type high-resistance region 7, under a large current condition, a considerable part of the electron current will flow through the first-conductivity-type high-resistance region 7, and a parasitic resistance exists in the first-conductivity-type high-resistance region 7, so that a transverse voltage drop will be generated in the first-conductivity-type high-resistance region 7, which can significantly reduce the potential below the center of the second-conductivity-type body region 2, and the P / N junction in the device can be more effectively opened to achieve a higher current capacity, so that the device has a higher surge current resistance, and the surge resistance is further enhanced.

[0049] Embodiment 2

[0050] Referring to Figures 2-4 The embodiment provides a preparation method of a high-surge MOS device, which comprises the following steps:

[0051] S1, selecting a first-conductivity-type substrate 5 and growing a first-conductivity-type epitaxial layer 6 on the first-conductivity-type substrate 5, wherein the first-conductivity-type substrate 5 is selected as an N-type silicon substrate, and the first-conductivity-type epitaxial layer 6 is grown by an epitaxial process;

[0052] S2, growing a gate oxide layer 9 on the front surface of the first-conductivity-type epitaxial layer 6, etching away part of the gate oxide layer 9 by photolithography shielding, and depositing polysilicon on the front surface of the gate oxide layer 9, i.e. part of the first-conductivity-type epitaxial layer 6, to form a plurality of gate structures 1 by photolithography shielding again;

[0053] S3, implanting a first-conductivity-type ion with a high resistivity on the front surface of the first-conductivity-type epitaxial layer 6 without the gate structure 1 and performing high-temperature promotion to form a first-conductivity-type high-resistance region 7;

[0054] S4, implanting a second-conductivity-type ion at the first-conductivity-type high-resistance region 7 and performing high-temperature promotion to form a second-conductivity-type extension column 8 and a second-conductivity-type body region 2;

[0055] S5, forming the first conductive type first source region 3 and the first conductive type second source region 4 by placing a plurality of S-shaped staggered photoetching shielding plates along the first direction on the front surface of the second conductive type body region 2, and injecting ions of the first conductive type into the area on the front surface of the second conductive type body region 2 without the photoetching shielding plates;

[0056] S6, depositing an insulating medium layer 10 on the front surface of the first conductive type epitaxial layer 6, so that the insulating medium layer 10 wraps the gate structure 1, and then etching the insulating medium layer 10 to form a plurality of through holes on the insulating medium layer 10, thereby forming a metal contact through hole 13 located above the second conductive type body region 2, and during etching, 0.3-0.4mm of the first conductive type epitaxial layer 6 will be etched, thereby ensuring that the insulating medium layer 10 can be completely removed to expose the metal contact, ensuring the stability and reliability of the electrical connection, depositing metal on the front surface of the insulating medium layer 10 and filling the metal contact through hole 13 to form a front metal layer 11, and depositing metal on the back surface of the first conductive type substrate 5 to form a back metal layer 12.

[0057] By setting the first conductive type first source region 3 and the first conductive type second source region 4, and arranging the first conductive type first source region 3 and the first conductive type second source region 4 in a staggered manner, the junction area of the second conductive type body region 2 in the MOS device can be significantly increased, thereby effectively increasing the junction area of the P / N junction and effectively enhancing the surge resistance of the MOS device, so that it can adapt to higher surge current and high-voltage impact application environment, and has wider adaptability.

[0058] It should be noted that each embodiment in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0059] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A high surge MOS device, characterized by, include: The gate structure must have at least two gates; The second conductivity type body region is disposed between the two gate structures; A first source region of a first conductivity type is provided within a body region of a second conductivity type, and multiple such regions are provided. The second source region of the first conductivity type is set within the body region of the second conductivity type and there are multiple such regions. Multiple first source regions of the first conductivity type are arranged along a first direction, and multiple second source regions of the first conductivity type are arranged along a first direction. The first source regions of the first conductivity type and the second source regions of the first conductivity type are located at different positions in a second direction. The first source regions of the first conductivity type and the second source regions of the second conductivity type are arranged alternately along the first direction. The first source regions of the first conductivity type are connected to adjacent second source regions of the first conductivity type.

2. The high surge MOS device of claim 1, wherein, The width of the overlapping portion of the first source region of the first conductivity type and the second source region of the first conductivity type in the second direction is less than half the width of the first source region of the first conductivity type and / or the second source region of the first conductivity type along the second direction.

3. The high surge MOS device of claim 1, wherein, Multiple first source regions of the first conductivity type and multiple second source regions of the first conductivity type are arranged in an S-shape along a first direction.

4. The high surge MOS device of claim 1, wherein, The first source region of the first conductivity type is provided in two rows, and the two rows of the first source regions of the first conductivity type are arranged along the first direction. The second source region of the first conductivity type is located between the two rows of the first source regions of the first conductivity type. Each row of the first source regions of the first conductivity type and multiple second source regions of the first conductivity type are arranged alternately along the first direction.

5. The high surge MOS device of claim 1, wherein, The first source region of the first conductivity type and the second source region of the first conductivity type have the same size.

6. The high surge MOS device of claim 1, wherein, Also includes: First conductivity type substrate; A first conductivity type epitaxial layer is disposed on the front side of the first conductivity type substrate. The gate structure is disposed on the front side of the first conductivity type epitaxial layer. The second conductivity type body region is disposed on the front side of the first conductivity type epitaxial layer and within the first conductivity type epitaxial layer. The first conductivity type first source region and the first conductivity type second source region are located within the second conductivity type body region.

7. The high surge MOS device of claim 6, wherein, A first conductivity type high resistance region is provided on the back side of the second conductivity type body region, and the resistivity of the first conductivity type high resistance region is higher than the resistivity of the first conductivity type epitaxial layer.

8. The high surge MOS device of claim 7, wherein, It also includes a second conductivity type extension post, which is disposed within the first conductivity type high resistance region, and is connected to the second conductivity type body region and the first conductivity type epitaxial layer, respectively.

9. The high surge MOS device of claim 8, wherein, At least two second conductive type extension posts are provided at each second conductive type body region, and multiple second conductive type extension posts are spaced apart along the first direction within the first conductive type high resistance region.

10. The high surge MOS device of claim 8, wherein, An insulating dielectric layer is disposed on the front side of the first conductivity type epitaxial layer, the insulating dielectric layer covers the gate structure, a front metal layer is disposed on the front side of the insulating dielectric layer, a back metal layer is disposed on the back side of the first conductivity type substrate, and the front metal layer extends toward the second conductivity type body region until it is connected to the second conductivity type body region.

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