Semiconductor device packaging structure and electronic equipment
By integrating a transistor and a resistor inside an insulated gate bipolar transistor to form an active clamping circuit, the device failure problem caused by the Miller effect is solved, enabling direct application on existing printed circuit boards and avoiding the increase in space and cost of external clamping circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-03-27
AI Technical Summary
When traditional insulated-gate bipolar transistors are used in hard-switching circuits, the Miller effect causes inductive conduction, leading to device failure. Furthermore, existing active clamping circuits increase the wiring space and cost of printed circuit boards, making them unsuitable for use in circuits that have already been fabricated.
By encapsulating active clamping circuits such as transistors and resistors inside an insulated gate bipolar transistor, an internally integrated gate active clamping circuit is formed, avoiding the need to build external clamping circuits.
It mitigates gate oscillations caused by the Miller effect, reduces the risk of device failure, and enables direct application on existing printed circuit boards without changing the package size.
Smart Images
Figure CN224054694U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power semiconductor devices, in particular to a semiconductor device packaging structure and an electronic device. BACKGROUND
[0002] When a conventional Insulated Gate Bipolar Transistor (IGBT) is applied in a hard switching circuit, such as a bridge circuit of a switching power supply and a motor drive inverter, the fast switching of the IGBT often causes an induced conduction phenomenon due to the Miller effect, which is particularly obvious in a bridge circuit. When the low-side IGBT is turned off, the high-side IGBT is turned on after the dead time ends. When this happens, the middle node will quickly transition from zero volts to the bus voltage. This transient voltage will cause a current pulse to pass through the reverse transfer capacitor of the IGBT, the Miller capacitor, and be coupled to the gate, causing a voltage spike at the gate. If the voltage spike exceeds the threshold of the IGBT and the high-side IGBT is in the on state, the low-side IGBT and the high-side IGBT will be short-circuited, causing the loop current to exceed the safe operating area limit of the IGBT and causing the device to fail. To address the above phenomenon, an active clamping circuit can be added externally to discharge the voltage spike, but this method increases the Printed Circuit Board (PCB) layout space and the cost of the device. If the actual circuit has already been completed and there is no layout and wiring space for the active clamping device, the active clamping circuit cannot be used. CONTENT OF THE INVENTION
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a semiconductor device packaging structure and an electronic device, wherein the semiconductor device packaging structure comprises:
[0004] a bottom plate having electrical conductivity;
[0005] a power device disposed on one side of the bottom plate;
[0006] a first protection device; an emitter of the first protection device is connected to a gate of the power device through a conductive wire, and a collector of the first protection device is connected to an emitter of the power device through a conductive wire; an insulating layer is included between the first protection device and the bottom plate, and the orthographic projection of the first protection device on the bottom plate does not exceed the orthographic projection of the insulating layer on the bottom plate; the first protection device is used to protect the power device from voltage breakdown;
[0007] a gate pin connected to a gate of the power device through a conductive wire for transmitting a switching signal to the power device, the power device being controllably switched on and off based on the switching signal;
[0008] a collector pin connected to a collector of the power device;
[0009] an emitter pin connected to an emitter of the power device through a conductive wire;
[0010] a packaging material wrapping the power device and the first protection device.
[0011] In a possible implementation, the power device comprises an insulated gate bipolar transistor.
[0012] In a possible implementation, the power device has a collector close to one side of the base plate and an emitter close to the other side of the base plate, and the gate of the power device is surrounded by the emitter of the power device.
[0013] In a possible implementation, the insulating layer further comprises a conductive layer away from the side of the base plate, the collector of the first protection device is disposed on the conductive layer, the base of the first protection device is surrounded by the collector of the first protection device, and the emitter of the first protection device is surrounded by the collector of the first protection device; wherein the orthogonal projection of the conductive layer on the base plate does not exceed the orthogonal projection of the insulating layer on the base plate, and the orthogonal projections of the base of the first protection device and the emitter of the first protection device on the base plate do not coincide and do not exceed the orthogonal projection of the conductive layer on the base plate.
[0014] In a possible implementation, the semiconductor device package structure further comprises a second protection device, the second protection device has a cathode close to one side of the base plate and an anode close to the other side of the base plate;
[0015] the emitter of the power device is connected to the emitter pin through the second protection device via a conductive wire;
[0016] the packaging material wraps the power device, the first protection device, and the second protection device.
[0017] In a possible implementation, the first protection device comprises a triode chip and a polycrystalline resistor integrated inside the triode chip; wherein the polycrystalline resistor is a variable resistor.
[0018] In a possible implementation, the poly-resistor includes a first variable resistor located at the base of the first protection device; a second variable resistor located between the first variable resistor and the emitter of the first protection device; and a third variable resistor located between the first variable resistor and the collector of the first protection device.
[0019] In a possible implementation, the base plate material includes copper.
[0020] In a possible implementation, the insulating layer material includes direct copper clad ceramic material.
[0021] Based on the same concept, the application further provides an electronic device including the semiconductor device packaging structure according to any one of the preceding embodiments.
[0022] Compared with the prior art, the application has the following beneficial effects:
[0023] The scheme integrates the transistor, resistor and the like in the active clamping circuit into the inside of the plastic package of the insulated gate bipolar transistor, integrates the gate active clamping circuit inside without changing the original package size of the insulated gate bipolar transistor, can slow down the oscillation of the gate caused by the Miller effect in the bridge topology circuit, and avoids building an external clamping circuit or performing other external circuit operations. The insulated gate bipolar transistor device can be directly applied to the original printed circuit board layout. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings required to be invoked in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0025] Figure 1 Circuit diagram of the active clamping circuit in the prior art to cope with the Miller effect;
[0026] Figure 2 Circuit diagram of the semiconductor device packaging module provided in the embodiment;
[0027] Figure 3 Circuit diagram of the first protection device provided in the embodiment;
[0028] Figure 4 Circuit diagram of the equivalent circuit of the first protection device provided in the embodiment.
[0029] Icon: Insulating layer-12; Base plate-11; First protection device-200; Second protection device-300; Power device-100; Conductive line-R; Semiconductor device package structure-10; Emitter of first protection device-E2; Collector of first protection device-C2; Base of first protection device-B2; Gate pin-G; Collector pin-C; Emitter pin-E; Collector of power device-C1; Emitter of power device-E1; Gate of power device-G1; Insulated gate bipolar transistor-Q; First variable resistor-R1; Second variable resistor-R2; Third variable resistor-R3; Bipolar junction transistor-Q'; Miller capacitor-C'. DETAILED DESCRIPTION
[0030] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.
[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art without creative work based on the embodiments in the present application are within the scope of protection of the present application.
[0032] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.
[0033] In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present application is usually placed, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.
[0034] In addition, the terms "horizontal", "vertical", "overhanging", and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.
[0035] In the description of the present application, it also needs to be explained that, unless otherwise explicitly specified and limited, the terms "set", "install", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0036] The inventor found that, please refer to Figure 1 When the conventional Insulated Gate Bipolar Transistor (IGBT) is applied in a hard switching circuit, such as a bridge circuit of a switching power supply and a motor drive inverter, the fast switching transistor Q will often appear the induced conduction phenomenon caused by the Miller effect, which is particularly evident in the bridge circuit. When the low-side IGBT is off, the high-side IGBT is turned on after the dead time ends. When this happens, the intermediate node will quickly transition from zero volts to the bus voltage. This transient voltage will cause a current pulse to pass through the reverse transfer capacitor of the IGBT, the Miller capacitor C', and be coupled to the gate, causing a voltage spike at the gate. If the voltage spike exceeds the threshold of the IGBT, and the high-side IGBT is in the on state, the high and low side IGBTs will be shorted, causing the bridge arm to be short-circuited, resulting in the loop current exceeding the safe operating area limit of the IGBT, causing the device to fail.
[0037] In view of the above phenomenon, an active clamping circuit can be added externally to the IGBT to discharge the voltage spike, and the specific circuit is shown in Figure 1 . Specifically, a triode Q' can be added between the gate and the emitter, and when the voltage reaches a certain value, the short-circuit switch between the gate and the emitter, i.e. the triode Q', will be triggered. In this way, the current flowing through the Miller capacitor C' will be blocked by the added triode Q' and will not flow to the output. This technology is called active Miller clamping technology. However, this method increases the Printed Circuit Board (PCB) layout space and the cost of devices. If the actual circuit has already been completed and there is no layout and wiring for active clamping devices, the active clamping circuit cannot be used.
[0038] Therefore, the present application provides a semiconductor device packaging structure 10, please refer to Figure 2 , comprising:
[0039] A bottom plate 11, which is conductive and suitable for the application of high-current power semiconductor devices.
[0040] A power device 100 is arranged on one side of the bottom plate 11.
[0041] The first protection device 200; please refer to Figure 2 And Figure 3 The emitter E2 of the first protection device is connected with the gate G1 of the power device through the conductive wire R, and the collector C2 of the first protection device is connected with the emitter E1 of the power device through the conductive wire R; the first protection device 200 and the bottom plate 11 include an insulating layer 12, and the orthogonal projection of the first protection device 200 on the bottom plate 11 does not exceed the orthogonal projection of the insulating layer 12 on the bottom plate 11; the first protection device 200 is used for protecting the power device 100 from being voltage breakdown.
[0042] The gate pin G is connected with the gate G1 of the power device through the conductive wire R, and is used for transmitting a switching signal to the power device 100, and the power device 100 is controllable on and off based on the switching signal; the base B2 of the first protection device is connected to the gate pin G through the conductive wire R.
[0043] The collector pin C is connected with the collector C1 of the power device.
[0044] The emitter pin E is connected with the emitter E1 of the power device through the conductive wire R.
[0045] The packaging material wraps the power device 100 and the first protection device 200.
[0046] In the embodiment, by packaging the first protection device 200 into the power device 100 plastic package body, the first protection device 200 is integrated inside without changing the original power device 100 packaging size, which can improve the reliability of the power device 100. In addition, since the first protection device 200 and the power device 100 are directly packaged together in the embodiment to form a single-tube power device, the semiconductor device packaging structure 10 can be directly applied to the original PCB without reserving space on the PCB.
[0047] Specifically, the power device 100 can be an insulated gate bipolar transistor Q, and the first protection device 200 can be equivalent to an active clamping circuit. In this way, the oscillation of the gate caused by the Miller effect of the insulated gate bipolar transistor Q in the bridge topology circuit can be slowed down, and the external clamping circuit or other external circuit operation can be avoided.
[0048] In a possible implementation, the power device 100 includes an insulated gate bipolar transistor Q (Insulated Gate Bipolar Transistor, IGBT).
[0049] In the embodiment, the power device 100 can be an IGBT, which is a composite full-controlled power semiconductor device combining the high input impedance of a metal-oxide-semiconductor field-effect transistor (MOSFET) and the low on-state voltage drop advantage of a bipolar junction transistor Q' (BJT). The working principle thereof is to form a conductive channel through gate voltage control, and to reduce the on-state voltage drop by minority carrier injection in the on state, and to achieve fast switching by carrier extraction in the off state.
[0050] In a possible implementation, referring to Figure 2 , one side of the power device 100 close to the bottom plate 11 is the collector C1 of the power device, and the other side is the emitter E1 of the power device, and the gate G1 of the power device is surrounded by the emitter E1 of the power device.
[0051] In a possible implementation, referring to Figure 2 , the semiconductor device packaging structure 10 further comprises a second protection device 300, one side of the second protection device 300 close to the bottom plate 11 is the cathode, and the other side is the anode; the emitter E1 of the power device is connected with the emitter pin E through the second protection device 300 by a conductive wire R; and the packaging material wraps the power device 100, the first protection device 200 and the second protection device 300.
[0052] In the embodiment, the second protection device 300 is used to protect the power device 100.
[0053] Specifically, the power device 100 in the embodiment can be an IGBT, and the second protection device 300 can be a fast recovery diode (FRD). By co-sealing the IGBT and the FRD in the semiconductor device packaging structure 10, the following beneficial effects can be achieved. When the IGBT is used, at the moment of its off, the FRD can provide a low impedance freewheeling path for inductive loads, avoiding the generation of high voltage spikes to damage the IGBT. The reverse recovery time of the FRD can reduce the IGBT on-loss. The optimally designed FRD can also suppress the voltage overshoot when the IGBT is off; matching the switching speed of the FRD and the IGBT can reduce electromagnetic interference. The soft recovery characteristic of the FRD can reduce the switching stress of the IGBT, and in the short-circuit working condition, the FRD can shunt part of the fault current to protect the IGBT. In addition, the co-sealing structure makes the FRD and the IGBT share the heat dissipation path, and balances the temperature distribution in the semiconductor device packaging structure 10 of the embodiment.
[0054] In a possible implementation, referring to Figure 3 , the insulating layer 12 further comprises a conductive layer away from one side of the bottom plate 11, the collector C2 of the first protection device is arranged on the conductive layer, the base B2 of the first protection device is surrounded by the collector C2 of the first protection device; the emitter E2 of the first protection device is surrounded by the collector C2 of the first protection device; wherein the orthographic projection of the conductive layer on the bottom plate 11 does not exceed the orthographic projection of the insulating layer 12 on the bottom plate 11, the orthographic projection of the base B2 of the first protection device and the orthographic projection of the emitter E2 of the first protection device on the bottom plate 11 do not coincide and do not exceed the orthographic projection of the conductive layer on the bottom plate 11.
[0055] In a possible implementation, referring to Figure 4 , Figure 4 is an equivalent circuit of the first protection device 200, the first protection device 200 comprises a triode chip and a polycrystalline resistance integrated inside; wherein the polycrystalline resistance is a variable resistance.
[0056] In the embodiment, the first protection device 200 comprises a triode chip and a polycrystalline resistance integrated inside, and the equivalent circuit is an active clamping circuit.
[0057] Specifically, the power device 100 in the embodiment can be an IGBT, and the triode chip can be a bipolar junction transistor Q' (BJT). The low on-state voltage drop characteristic of the BJT enables it to quickly discharge the charge of the Miller capacitor, shortens the IGBT gate voltage platform time, and its collector current processing capability can effectively absorb the gate displacement current caused by the Miller effect, reducing the parasitic conduction risk of the IGBT. The polycrystalline resistance integrated inside is a variable resistance, which can change the on-state voltage of the BJT, thereby discharging the charge of the Miller capacitor. Therefore, the first protection device 200 can use the BJT as the core device when dealing with the Miller effect of the IGBT.
[0058] In a possible implementation, referring to Figure 4 , Figure 4 is an equivalent circuit of the first protection device 200, the polycrystalline resistance comprises a first variable resistance R1 located at the base B2 of the first protection device; a second variable resistance R2 located between the first variable resistance R1 and the emitter E2 of the first protection device; a third variable resistance R3 located between the first variable resistance R1 and the collector C2 of the first protection device.
[0059] In the embodiment, the first variable resistor R1, the second variable resistor R2 and the third variable resistor R3 are used to adjust the on-voltage of the first protection device 200.
[0060] Specifically, the triode chip can be a BJT. By connecting the first variable resistor R1 to the base of the BJT triode, the second variable resistor R2 between the base and the emitter of the BJT triode, and the third variable resistor R3 between the base and the collector of the BJT triode, an adjustable resistance network is formed, which can change the on-voltage of the BJT. This structure utilizes the variability of the polycrystalline resistance, and by cooperatively adjusting the resistance value ratio of the first variable resistor R1, the second variable resistor R2 and the third variable resistor R3, the on-voltage of the BJT can be accurately controlled, thereby adapting to different driving scenarios.
[0061] In a possible implementation, the material of the bottom plate 11 includes copper.
[0062] In the embodiment, the semiconductor device packaging structure 10 adopts a copper bottom plate 11. Copper has good electrical conductivity and is suitable for high-current power semiconductor module applications; at the same time, copper has good heat conduction performance and can quickly conduct heat, thereby improving the heat dissipation performance of the semiconductor device packaging structure 10 of the application. In addition, the copper bottom plate 11 has high process compatibility and low cost. Therefore, the material of the bottom plate 11 can be copper.
[0063] It should be noted that, in addition to copper, in other implementations of the embodiment, the bottom plate 11 can also include other materials, which are not limited here.
[0064] In a possible implementation, the material of the insulating layer 12 includes a direct bonded copper (DBC ceramic) material.
[0065] DBC ceramic has good dielectric strength and can better block the current between the first protection device 200 and the bottom plate 11; DBC ceramic has good heat conduction capacity and can form an efficient heat dissipation channel with the bottom plate 11, thereby alleviating the heating problem of the first protection device 200 in use. In the embodiment, the insulating layer 12 is used to form electrical isolation with the bottom plate 11, and DBC ceramic is selected as the material of the insulating layer 12 to improve the electrical isolation effect.
[0066] It should be noted that, in addition to DBC ceramic, in other implementations of the embodiment, the insulating layer 12 can also include other materials, as long as electrical isolation between the insulating layer 12 and the bottom plate 11 is achieved, which is not limited here.
[0067] Based on the same concept, the application also provides an electronic device comprising the semiconductor device packaging structure 10 of any one of the preceding embodiments.
[0068] In summary, the application provides a semiconductor device packaging structure 10 and an electronic device, by packaging the triode, resistor, etc. in the active clamping circuit into the IGBT plastic package, the internal integrated gate active clamping circuit is realized without changing the original IGBT package size, which can slow down the oscillation of the gate caused by the Miller effect in the bridge topology circuit, and at the same time, the external clamping circuit or other external circuit operation is avoided. The IGBT device can be directly applied on the original PCB layout.
[0069] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... " does not, without more limitations, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.
[0070] The above only describes the preferred embodiments of the application and is not intended to limit the application. The application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.
Claims
1. A semiconductor device package structure, comprising: The semiconductor device package structure comprises: a bottom plate, the bottom plate having electrical conductivity; a power device arranged on one side of the bottom plate; a first protection device; an emitter of the first protection device is connected to a gate of the power device through a conductive wire, and a collector of the first protection device is connected to an emitter of the power device through a conductive wire; an insulating layer is arranged between the first protection device and the bottom plate, and a footprint of the first protection device on the bottom plate does not exceed a footprint of the insulating layer on the bottom plate; the first protection device is used for protecting the power device from voltage breakdown; a gate pin is connected to the gate of the power device through a conductive wire, and is used for transmitting a switching signal to the power device, and the power device is controllably turned on and off based on the switching signal; a base of the first protection device is connected to the gate pin through a conductive wire; a collector pin is connected to a collector of the power device; an emitter pin is connected to an emitter of the power device through a conductive wire; a packaging material is arranged to wrap the power device and the first protection device.
2. The semiconductor device package structure of claim 1, wherein, The power device comprises an insulated gate bipolar transistor.
3. The semiconductor device package structure of claim 1, wherein, The power device has a collector on one side close to the bottom plate and an emitter on the other side, and a gate of the power device is surrounded by the emitter of the power device.
4. The semiconductor device package structure of claim 1, wherein, The insulating layer further comprises a conductive layer on a side away from the bottom plate, the collector of the first protection device is arranged on the conductive layer, the base of the first protection device is surrounded by the collector of the first protection device, and the emitter of the first protection device is surrounded by the collector of the first protection device; a footprint of the conductive layer on the bottom plate does not exceed a footprint of the insulating layer on the bottom plate, and footprints of the base of the first protection device and the emitter of the first protection device on the bottom plate do not coincide and do not exceed a footprint of the conductive layer on the bottom plate.
5. The semiconductor device package structure of claim 1, wherein, The semiconductor device package structure further comprises a second protection device, the second protection device has a cathode on one side close to the bottom plate and an anode on the other side; the emitter of the power device is connected to the emitter pin through the second protection device through a conductive wire; the packaging material wraps the power device, the first protection device and the second protection device.
6. The semiconductor device package structure of claim 1, wherein, The first protection device comprises a triode chip and a polycrystalline resistor integrated in the triode chip; the polycrystalline resistor is a variable resistor.
7. The semiconductor device package structure of claim 6, wherein, The polycrystalline resistor comprises a first variable resistor at the base of the first protection device, a second variable resistor between the first variable resistor and the emitter of the first protection device, and a third variable resistor between the first variable resistor and the collector of the first protection device.
8. The semiconductor device package structure of claim 1, wherein, The bottom plate material comprises copper.
9. The semiconductor device package structure of claim 1, wherein, The insulating layer material comprises direct copper clad ceramic material.
10. An electronic device, comprising: The semiconductor device package structure comprises any one of claims 1-9.