Electronic component

Abstract

The utility model provides an electronic component which comprises a first interconnection, a second interconnection and an insulating layer. The lower portion of the first interconnect is laterally spaced from the lower portion of the second interconnect by an air gap. The insulating layer is laterally between an upper portion of the first interconnect and an upper portion of the second interconnect. In the structure of the electronic component, the electronic component can have better performance and / or quality through the configuration position and / or mode of the air gap. For example, the air gap may reduce signal interference or coupling capacitance between two adjacent interconnects, such as a first interconnect and a second interconnect. In addition, the thermal conductivity of the insulating layer may be higher than the thermal conductivity of the first interconnect and the second interconnect. Therefore, when the electronic component operates, the generated heat can be easily and quickly transferred to one interconnection (such as a first interconnection) and then quickly or effectively transferred to another interconnection (such as a second interconnection) through the insulating layer, so that the heat scattering efficiency can be improved, and the electronic component can have better performance and / or quality.

Description

TECHNICAL FIELD

[0001] The utility model relates to an electronic component, especially an electronic component with air gap. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. A steady increase in demand has created pressure to reduce the costs of ICs. In response to this demand, there has been a corresponding increase in IC density (the number of interconnected devices per chip) and a decrease in feature sizes (the size of transistors, resistors, capacitors, etc.). SUMMARY

[0003] Embodiments of the utility model provide an electronic component, which includes a first interconnect, a second interconnect, and an insulating layer. A lower portion of the first interconnect is laterally spaced apart from a lower portion of the second interconnect by an air gap. The insulating layer is laterally between an upper portion of the first interconnect and an upper portion of the second interconnect.

[0004] Embodiments of the utility model provide an electronic component, which includes a substrate, an interconnect, a first insulating layer, and a second insulating layer. The interconnect is on the substrate. The first insulating layer is on the substrate. The second insulating layer is above the first insulating layer and surrounds the interconnect. A portion of the first insulating layer is vertically spaced apart from a portion of the second insulating layer by an air gap.

[0005] Based on the above, in the structure of the electronic component, via the configuration mode of the air gap, the signal interference or coupling capacitance between two adjacent interconnects (such as the first interconnect and the second interconnect) can be reduced. Therefore, the electronic component can have better performance and / or quality.

[0006] In order to make the above features and advantages of the utility model more obvious and easy to understand, the following examples are taken, and the detailed description is made as follows with the help of the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1K Various cross-sectional views of some embodiments of a method of forming an electronic component are illustrated.

[0008] Figure 1L A top view of an electronic component in some embodiments is illustrated.

[0009] Figures 2A-2E Various cross-sectional views of some embodiments of a method of forming an electronic component are illustrated.

[0010] Figures 3A-3C Various cross-sectional views of some embodiments of a method of forming an electronic component are illustrated.

[0011] Figure 4 A schematic cross-sectional view of an electronic component is illustrated.

[0012] Figure 5 A flowchart illustrating some embodiments of a method of forming an electronic component is shown.

[0013] Reference sign explanation:

[0014] 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 200A, 200B, 200C, 200D, 200E, 300A, 300B, 300C: structure;

[0015] 110: substrate;

[0016] 111: conductor;

[0017] 112: insulating region;

[0018] 111, V0: conductive via;

[0019] 120, 121, 122, 140, 141, 142: conductive layer;

[0020] 131, 132, 160, 169, 170, 179, 180, 189, 270, 279, 380, 389: insulating layer;

[0021] 139, 149, 49: cap layer;

[0022] 140a, 160a, 170a, 179a, 180a, 199a, 270a, 380a: top surface;

[0023] 140d, 180d: thickness;

[0024] 180s: sidewall;

[0025] 189b: bottommost surface;

[0026] 151, 152, 153, 51, 52, 53: interconnect;

[0027] 1511, 1521, 1531: upper portion;

[0028] 1512, 1522, 1532: lower portion;

[0029] 199, 299: sacrificial layer;

[0030] H0: hole;

[0031] S1: air gap;

[0032] T1: trench;

[0033] W1: top width;

[0034] W2: bottom width;

[0035] R1: area;

[0036] PL: plane;

[0037] 400: die;

[0038] 41: active device;

[0039] S: source;

[0040] D: drain;

[0041] G: gate;

[0042] 42: interconnect structure;

[0043] 48: die pad;

[0044] X, Y, Z: direction;

[0045] 501, 502, 503, 504, 505, 506, 507: act. DETAILED DESCRIPTION

[0046] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Some examples are provided in enough detail to facilitate practice of at least some embodiments of the present application and others are provided in

[0047] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The

[0048] Figures 1A-1K Various cross-sectional views of some embodiments of methods of forming electronic elements are illustrated.

[0049] As Figure 1AAs shown in the cross-sectional view, a structure 100A including a substrate 110 and a plurality of layers (e.g., layer 120, layer 131, layer 132, layer 139) or regions configured on or embedded in the substrate 110 is provided. The plurality of layers or regions can be formed by suitable processes, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density chemical plasma vapor deposition (HDPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or high density plasma chemical vapor deposition (HDPCVD), vapor transport deposition (VTD), ion implantation process, diffusion process, oxidation process, etc. The plurality of layers or regions configured on or embedded in the substrate 110 can be considered as part of the substrate 110. For example, the substrate 110 includes an insulating region 112 and a conductor 111 embedded in the insulating region 112. The conductor 111 can be an electrically conductive via electrically connected to a transistor. For example, the conductor 111 is electrically connected to an electrode (e.g., gate, source, or drain) of a transistor.

[0050] The substrate 110 can include a semiconductor substrate (e.g., a silicon (Si) substrate or a semiconductor wafer), a printed circuit board (e.g., an FR-4 printed circuit board), or a glass substrate, but the disclosure is not limited thereto. A structure including a semiconductor substrate can be referred to as a semiconductor structure. For example, a semiconductor wafer, the substrate includes a crystalline silicon wafer. The substrate 110 can include various doped regions (e.g., a p-type substrate or an n-type substrate) according to design requirements. In some embodiments, the doped regions can be doped with p-type dopants or n-type dopants. The doped regions can be doped with p-type dopants, such as boron or BF2, n-type dopants, such as phosphorus or arsenic, and / or combinations thereof. The doped regions can be configured as n-type Fin-type Field Effect Transistors (FinFETs) and / or p-type FinFETs. In some alternative embodiments, the substrate 110 is made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon carbon germanium, gallium arsenide phosphide, or gallium indium arsenide phosphide. The substrate 110 can further include interconnect structures formed on and electrically connected to the various doped regions. The interconnect structures can include circuits manufactured by front end of line (FEOL) or middle end of line (MEOL). For example, conductive vias can penetrate insulating regions and be electrically connected to gates, source regions, or drain regions.

[0051] Layers located on the substrate 110 include a conductive layer 120, an insulating layer 131, an insulating layer 132, and a cap layer 139. For example, the conductive layer 120 can include a conductive layer 121 and a conductive layer 122 having the same or similar patterns, and can be referred to as an M0 layer. The M0 layer can include interconnects. The conductive layer 121 can be referred to as a seed layer, a conductive glue layer, or a diffusion barrier layer. The conductive layer 122 can be referred to as a plated layer. The insulating layer 131 can include an etching-stop layer (ESL). The insulating layer 132 can include a low-k dielectric layer. The cap layer 139 can include a hard-mask (HM) layer. The material of the hard-mask layer can include a conductive material (e.g., titanium nitride (TiN), tantalum nitride (TaN), or amorphous carbon), an insulating material (e.g., an oxide or a nitride), or a semiconductor material (e.g., amorphous silicon (a-Si)).

[0052] AsFigure 1B As shown in the cross-sectional view, a structure 100B with at least one hole H0 is formed. The hole H0 is formed to penetrate layers 131, 132, and 139 to expose a portion of layer 120 MO. The hole H0 can be formed by a suitable semiconductor process (e.g., photolithography followed by etching).

[0053] like Figure 1C As shown in the cross-sectional view, a structure 100C is formed including at least one conductive through-hole V0. The conductive through-hole V0 can be filled with conductive material (e.g., through-hole H0) by appropriate semiconductor processes (e.g., physical vapor deposition (PVD) and / or plating processes). Figure 1B As shown in the diagram, the top surface of the conductive via V0 and the top surface of the insulating layer 132 can be substantially coplanar, and the top surface of the conductive via V0 and the top surface of the insulating layer 132 can be processed by a planarization process (such as chemical mechanical planarization (CMP)). In the aforementioned planarization process, such as... Figure 1B The capping layer 139 shown is removed. In the aforementioned planarization process, as... Figure 1B A portion of the insulating layer 132 shown may be further removed.

[0054] like Figure 1D As shown in the cross-sectional view, a structure 100D is formed, including at least one conductive layer. Figure 1D The diagram illustrates two conductive layers 141, conductive layer 142, and a capping layer 149, but this disclosure is not limited thereto. Conductive layer 141 may be referred to as a seed layer, conductive adhesive layer, or diffusion barrier layer. Conductive layer 142 may be referred to as a plating layer. Capping layer 149 may include a hard mask (HM) layer.

[0055] like Figure 1E As shown in the cross-sectional view, a structure 100E including at least one trench T1 is formed. Two trenches T1 that appear unconnected in the cross-sectional view may be substantially connected in other cross-sectional views. The trench T1 is formed to penetrate conductive layers 141, 142, and a capping layer 149 disposed thereon. The trench T1 can be formed by appropriate semiconductor processes (e.g., photolithography followed by etching).

[0056] Multiple conductive layers 141 and 142 are referred to as conductive layer 140. That is, conductive layer 140 may include conductive layers 141 and 142 with similar patterns and may be referred to as layer M1. After forming trenches T1, interconnects 151, 152, and 153 are formed in the patterned conductive layer 140, and interconnects 151, 152, and 153 are electrically insulated from each other by the multiple trenches T1. In a cross-sectional view, the top dimension (e.g., top width) of trench T1 may be larger than the bottom dimension (e.g., bottom width) of trench T1, and the top dimensions (e.g., top width) of interconnects 151, 152, and 153 may be smaller than the bottom dimensions (e.g., bottom width) of interconnects 151, 152, and 153. For example, the top width W1 of interconnect 151 is smaller than the bottom width W2 of interconnect 151. In other words, in the cross-sectional view, the shape of trench T1 may be an inverted trapezoid, and the shapes of interconnects 151, 152, and 153 may be trapezoidal. In subsequent processes, the inverted trapezoidal shape of trench T1 may enhance the step coverage of the film layer formed on trench T1 and / or the film layer embedded in trench T1.

[0057] like Figure 1F As shown in the cross-sectional view, a structure 100F is formed including an insulating layer 169. The insulating layer 169 may include a dielectric capping layer. The insulating layer 169 can be formed by a suitable process and conformally covers the surface. Figure 1E The insulating layer 169 is formed on the structure 100E shown. For example, the insulating layer 169 can be formed by a deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor transport deposition (VTD), or similar). For example, the insulating layer 169 can be formed by an exfoliation process (such as acoustic, mechanical, hydrothermal, electrochemical, laser-assisted, and microwave-assisted exfoliation). Further processes, such as thermal processes (such as heating, annealing, or similar), can be performed to form the insulating layer 169.

[0058] The insulating layer 169 may be made of silicon oxide (SiO), silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiNO), silicon carbon nitride (SiCN), nitrogen-doped silicon oxide (SiCON), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), or a 2D material. In one embodiment, the thickness of the insulating layer 169 is less than or substantially equal to 5 nanometers (nm). In another embodiment, the thickness of the insulating layer 169 is approximately 2 angstroms (Å). ) to 50 angstroms

[0059] like Figure 1G As shown in the cross-sectional view, a structure 100G including a sacrificial layer 199 is formed. The sacrificial layer 199 can be formed by a deposition process and a recess process (e.g., a partially removal process). The sacrificial layer 199 is configured and / or filled at the bottom of the trench T1, and the top surface 199a of the sacrificial layer 199 is lower than the top surface 140a of the conductive layer 140. In one embodiment, the thickness of the sacrificial layer 199 is less than or substantially equal to the thickness of the conductive layer 140. In another embodiment, the thickness of the sacrificial layer 199 is approximately to In subsequent processes, the sacrificial layer 199 will be removed to form an air gap.

[0060] like Figure 1H As shown in the cross-sectional view, a structure 100H is formed, including an insulating layer 179. The insulating layer 179 may include a support layer. The insulating layer 179 can be formed by a deposition process and conformally covers the substrate. Figure 1G This is a part of the structure 100G shown. Insulating layer 179 covers the top surface 199a of sacrificial layer 199. Insulating layer 179 further covers a portion of insulating layer 169 that is not in contact with sacrificial layer 199. Insulating layer 179 is separated from capping layer 149 and interconnects 151, 152, and 153 by insulating layer 169. The sidewalls of trench T1 not covered by sacrificial layer 199 are covered by insulating layer 179. The bottommost top surface 179a of insulating layer 179 is lower than the top surface 140a of conductive layer 140.

[0061] The insulating layer 179 may be made of silicon oxide (SiO), silicon carbide (SiCO), silicon oxynitride (SiNO), silicon carbide (SiCN), or nitrogen-doped silicon oxide (SiCON). In one embodiment, the thickness of the insulating layer 179 is less than or substantially equal to... In another embodiment, the thickness of the insulating layer 179 is approximately to

[0062] like Figures 1H-1I The cross-sectional view shows the removal process being performed. This removal process may be... Figure 1H The process is performed on the structure 100H shown. After the above removal process, at least a portion of the sacrificial layer 199 is removed. Therefore, as Figure 1I As shown in the cross-sectional view, a structure 100I is formed, including an air gap S1 located between two adjacent interconnects (e.g., between two interconnects 151 and 152 and between two interconnects 151 and 153).

[0063] Sacrificial layer 199 (e.g.) Figure 1HThe material of the sacrificial layer 199 (as shown) may exhibit etch selectivity with respect to insulating layers 169 and 179. The material of the sacrificial layer 199 may be or include oxides, nitrides, metal oxides, metal nitrides, or organic materials. For example, insulating layers 169 and / or 179 may be made of oxides, while the material of the sacrificial layer 199 may include metal nitrides or nitrides. For example, insulating layers 169 and / or 179 may be made of nitrides, while the material of the sacrificial layer 199 may include oxides or metal nitrides. For example, the material of the sacrificial layer 199 may include silicon oxides, silicon nitrides, titanium nitride (TiN), lanthanum oxide (LaO), or aluminum oxide (Al2O3). In embodiments where the sacrificial layer 199 is made of titanium nitride, a removal process using an ammonium hydroxide-hydrogen peroxide-water mixture (APM) solution can be performed. In embodiments where the sacrificial layer 199 is made of lanthanum oxide, a removal process using a solvent containing hydrochloric acid (HCl) can be performed. In embodiments where the sacrificial layer 199 is made of alumina, a removal process using a solvent containing tetramethylammonium hydroxide (TMAH) can be performed. In embodiments where the sacrificial layer 199 is made of an organic material, a removal process using an ashing process (e.g., UV ashing process) or a heating process (e.g., thermal baking process) can be performed.

[0064] It is worth noting that this disclosure reserves the possibility that the sacrificial layer 199 may not be completely removed. For example, a small amount of residual sacrificial layer 199 may be located on a portion of the insulating layer 169 embedded in the trench T1. For example, a small amount of residual sacrificial layer 199 may be located on a portion of the bottommost surface of the insulating layer 179 embedded in the trench T1. In embodiments where the sacrificial layer 199 is made of an insulating material, it has substantially no significant impact on the conductivity of interconnects 151, 152, and 153. In one embodiment, the removal rate of the sacrificial layer 199 is greater than 80%. In another embodiment, the removal rate of the sacrificial layer 199 is greater than 95%.

[0065] like Figure 1J As shown in the cross-sectional view, a structure 100J including an insulating layer 189 is formed. The insulating layer 189 is formed to cover the insulating layer 179 and fill the trench T1 (as shown in the figure). Figure 1IThe upper part of the insulating layer 189 (as shown). The bottom surface 189b of the insulating layer 189 is lower than the top surface 140a of the conductive layer 140. The insulating layer 189 and the insulating layer 169 are separated by the insulating layer 179. The material of the insulating layer 189 may include silicon oxycarbide (SiCOH) or a material that has good adhesion to other insulating layers 179.

[0066] It is worth noting that, in cases such as Figures 1H-1J In the illustrated embodiment, the sacrificial layer 199 (e.g. Figure 1H The sacrificial layer 199 (as shown) is removed before the formation of insulating layer 189, but this disclosure is not limited thereto. In another embodiment, sacrificial layer 199 may be removed after the formation of insulating layer 189.

[0067] like Figure 1K As shown in the cross-sectional view, a structure 100K is formed, comprising insulating layer 160, insulating layer 170, and insulating layer 180. (As shown in the cross-sectional view...) Figures 1J-1K As shown, portions of insulating layers 169, 179, and 189 can be removed by performing an appropriate removal process (e.g., planarization) to form insulating layers 160, 170, and 180. Furthermore, in the aforementioned removal process, capping layer 149 (e.g., Figure 1J The interconnects 151, 152, and 153 (shown in the diagram) are removed. After performing the aforementioned removal process, the top surfaces (i.e., top surfaces 140a) of interconnects 151, 152, and 153 are exposed. The top surfaces 140a of interconnects 151, 152, and 153, the top surfaces 160a of insulating layer 160, 170a of insulating layer 170, and 180a of insulating layer 180 may be substantially coplanar. A portion of insulating layers 170 and 180 is perpendicularly spaced from a portion of insulating layers 160 and 132 by an air gap S1. Insulating layer 170 extends from the sidewall of the upper portion 1511 of interconnect 151 to the sidewall of the upper portion 1521 of interconnect 152 and the sidewall of the upper portion 1531 of interconnect 153. Insulating layer 160 extends from the sidewall of interconnect 151 to the sidewall of interconnect 152 and the sidewall of interconnect 153, and air gap S1 is closed by a portion of insulating layer 160 and a portion of insulating layer 170.

[0068] It is worth noting that, in cases such as Figures 1H-1K In the embodiment shown, the sacrificial layer 199 (e.g. Figure 1H The sacrificial layer 199 (as shown) is removed before the formation of insulating layer 180, but this disclosure is not limited thereto. In another embodiment, the sacrificial layer 199 may be removed after the formation of insulating layer 180.

[0069] like Figure 1K The structure shown is 100K or Figure 1L The structure 100L shown may be part of an electronic component. That is to say,Figure 1K partially cross-sectional view of certain embodiments of an electronic component, and / or Figure 1L partially top view of certain embodiments of an electronic component. For example, Figure 1K may be considered as corresponding to Figure 1L partially cross-sectional view along the K-K' cross-sectional line shown in FIG. 1; and / or, Figure 1L may be considered as corresponding to Figure 1K top view along the plane PL shown in FIG. 1. As Figure 1K and / or Figure 1L illustrated, the electronic component can include a substrate 110, a plurality of interconnects 151, 152, 153 on the substrate 110, and an insulating layer 180 between two adjacent interconnects (e.g., the two interconnects 151 and 152 and the two interconnects 151 and 153). An air gap S1 is formed between the insulating layer 180 and the substrate 110. The lower portion 1512 of the interconnect 151 is laterally spaced apart from the lower portion 1522 of the interconnect 152 and the lower portion 1532 of the interconnect 153 by the air gap S1. The insulating layer 180 is laterally disposed between the upper portion 1511 of the interconnect 151 and the upper portion 1521 of the interconnect 152 and the upper portion 1531 of the interconnect 153. In an embodiment, the annular air gap S1 encircles at least one interconnect (e.g., the interconnect 151) as viewed from the top view.

[0070] The air gap S1 can be considered as a space that can not have solid material. The air pressure in the air gap S1 can be extremely low or close to vacuum. In an embodiment, the air gap S1 can reduce signal interference or coupling capacitance between two adjacent interconnects (e.g., the two interconnects 151 and 152 and the two interconnects 151 and 153). Thus, the electronic component can have better performance and / or quality.

[0071] The interconnect 151 is electrically connected to a component (e.g., a transistor) through one or more conductors (e.g., conductive vias 111). That is, when the component is in operation, the generated heat can be easily and quickly transferred to the interconnect 151. One or more interconnects 152, 153 adjacent to the interconnect 151 can be electrically insulated from the interconnect 151. The interconnects 152, 153 can be referred to as dummy patterns. It is noted that "dummy" here can refer to dummy on signal, but can have other uses. For example, during the process of forming the interconnects (e.g., the interconnect 151, the interconnect 152, the interconnect 153), the dummy patterns can generate corresponding stress on the corresponding parts of the structure, which can improve the process quality. For example, the interconnects 152, 153 can be electrically grounded, which can reduce electromagnetic interference. For example, the interconnects 152, 153 can be thermally coupled to a heat dissipating member, which can improve the heat dissipation efficiency.

[0072] The insulating layer 160 can be referred to as a thermal boundary resistance (TBR) layer, and the insulating layer 160 has a better thermal conductivity. The TBR layer has a high thermal conductivity and good electrical insulation, and can be formed of SiN, AlN, SiO2, silicon carbide (SiC), diamond, or a suitable insulating 2D material (e.g., hexagonal boron nitride (h-BN, graphitic BN) that is electrically insulated from the interconnects 151 and allows heat to pass from the interconnects 151 through the TBR layer). In an embodiment, the material of the insulating layer 160 has a higher thermal conductivity than the materials of the interconnects 151, 152, 153 of the conductive layer 140 (e.g., the Ml layer). In an embodiment, the insulating layer 160 has a thickness of less than or substantially equal to 5 nanometers. In another embodiment, the insulating layer 160 has a thickness of about 2 angstroms to 50 angstroms.

[0073] The material of the insulating layer 180 can have a higher thermal conductivity than the materials of the interconnects 151, 152, 153 of the conductive layer 140, and can be referred to as a TBR layer or a high thermal conductivity low k dielectric layer. The thermal conductivity of the insulating layer 180 can be two to ten times higher than the thermal conductivities of the interconnects 151, 152, 153. In an embodiment, the material of the insulating layer 180 can include AlN, h-BN, graphene oxide, diamond, SiC, or SiCN, and the materials of the interconnects 151, 152, 153 can include copper. Heat (e.g., thermal energy) in one interconnect (e.g., the interconnect 151) can be quickly or efficiently transferred to another interconnect (e.g., at least one of the interconnects 152, 153) through the insulating layer 180.

[0074] Considering the interconnect 151 and the sidewall 180s of the insulating layer 180 corresponding or adjacent to the interconnect 151, the product of the sidewall surface area and the thermal conductivity of the insulating layer 180 can be greater than or substantially equal to the product of the sidewall surface area and the thermal conductivity of the interconnect 151 in the same unit and order of magnitude. In an embodiment, an equivalent thermal conductivity of a volume (which corresponds to the area Rl shown in FIG. 1A and has a thickness equal to the thickness 140d of the interconnect 151) is substantially equal to or greater than the equivalent thermal conductivity of a block having the same size as the volume and the same material as the interconnect 151, and thus the heat dissipation efficiency can be better. Figure 1L ​​

[0075] Further considering the measurement method, the sidewall surface area of the insulating layer 180 can be estimated by the product of the thickness 180d of the insulating layer 180 and the inner profile length of the interconnect 151, and the sidewall surface area of the interconnect 151 can be estimated by the product of the thickness 140d and the outer profile length of the interconnect 151. Moreover, considering that the total thickness of the layers between the interconnect 151 and the insulating layer 180 (e.g., the insulating layer 160 and the insulating layer 170) is much smaller than the aforementioned profile lengths, the inner profile length of the insulating layer 180 is approximately equal to the outer profile length of the interconnect 151. Therefore, in the same unit and order of magnitude, the product of the thickness 180d of the insulating layer 180 and the thermal conductivity of the insulating layer 180 can be substantially equal to or greater than the product of the thickness 140d of the interconnect 151 and the thermal conductivity of the interconnect 151.

[0076] In one embodiment, the thickness 180d of the insulating layer 180 is less than or substantially equal to 100 nanometers. In another embodiment, the thickness 180d of the insulating layer 180 is about 10 angstroms to 700 angstroms. In another embodiment, the thickness 180d of the insulating layer 180 is about 10 angstroms to 400 angstroms.

[0077] Figures 2A-2E Various cross-sectional views of some embodiments of a method of forming an electronic component are illustrated. In some embodiments, Figures 2A-2B An example method of forming an electronic component after the structure shown can be illustrated. Figure 1E An example method of forming an electronic component after the structure shown can be illustrated.

[0078] As shown in the cross-sectional view of FIG. 2A, a structure 200A including a sacrificial layer 199 is formed. The formation process and / or material of the sacrificial layer 199 can be the same as or similar to the formation process and / or material of the sacrificial layer 109 shown in FIG. 1A. Figure 2A As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figure 1G As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B.

[0079] As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figure 2B As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figure 1H As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B.

[0080] As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figures 2B-2C As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figure 2B As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figures 1H-1I As shown in the cross-sectional view of FIG. 2B, a structure 200B including an insulating layer 179 is formed. The formation process and / or material of the insulating layer 179 can be the same as or similar to the formation process and / or material of the insulating layer 169 shown in FIG. 1B. Figure 2CAs shown in the cross-sectional view, structure 200C is formed, which includes an air gap S1 between two adjacent interconnects (e.g., two interconnects 151 and 152 and two interconnects 151 and 153).

[0081] It is worth noting that this disclosure reserves the possibility that the sacrificial layer 299 may not have been completely removed. For example, a small amount of residual sacrificial layer 299 may be located on interconnects 151, 152, 153 and / or insulating layer 279.

[0082] like Figure 2D As shown in the cross-sectional view, a structure 200D is formed, including an insulating layer 189. The forming process and / or material of the insulating layer 189 may be related to... Figure 1J The insulating layer 189 shown has the same or similar forming process and / or material.

[0083] It is worth noting that, in cases such as Figures 2B-2D In the illustrated embodiment, the sacrificial layer 299 is removed before the insulating layer 189 is formed, but this disclosure is not limited thereto. In another embodiment, the sacrificial layer 299 may be removed after the insulating layer 189 is formed.

[0084] like Figure 2E As shown in the cross-sectional view, a structure 200E is formed, including insulating layer 270 and insulating layer 180. (As shown in the cross-sectional view...) Figures 2D-2E As shown, insulating layers 270 and 180 can be formed by removing a portion of insulating layers 279 and 189 and performing an appropriate removal process (e.g., planarization). Furthermore, in the aforementioned removal process, capping layer 149 (e.g., Figure 2D (As shown) is removed. After performing the aforementioned removal process, interconnects 151, 152, and 153 are exposed. The top surface 140a of interconnects 151, 152, and 153, the top surface 270a of insulating layer 270, and the top surface 180a of insulating layer 180 may be substantially on the same plane. A portion of insulating layer 270 and insulating layer 180 is perpendicularly spaced from a portion of insulating layer 132 by an air gap S1. Insulating layer 270 extends from the sidewall of the upper portion 1511 of interconnect 151 to the sidewall of the upper portion 1521 of interconnect 152 and the sidewall of the upper portion 1521 of interconnect 153, and the air gap S1 is closed by a portion of insulating layer 132, a portion of insulating layer 270, and interconnects 151, 152, and 153.

[0085] It is worth noting that, in cases such as Figures 2B-2E In the illustrated embodiment, the sacrificial layer 299 is removed before the insulating layer 180 is formed, but this disclosure is not limited thereto. In another embodiment, the sacrificial layer 299 may be removed after the insulating layer 180 is formed.

[0086] As Figure 2E shown, structure 200E can be part of an electronic component. As Figure 2E shown, the electronic component can include substrate 110, a plurality of interconnects 151, 152, 153 on substrate 110, and an insulating layer 180 between two adjacent interconnects (e.g., interconnect 151 and interconnect 152, and interconnect 151 and interconnect 153). An air gap S1 is formed between insulating layer 180 and substrate 110. In one embodiment, air gap S1 surrounds at least one interconnect (e.g., interconnect 151) as viewed from a top view.

[0087] As Figure 2E shown, the electronic component can be similar to the electronic component shown in Figure 1K except that Figure 2E the electronic component shown in Figure 1K does not include insulating layer 160. In addition, Figure 2E various portions of the electronic component shown in Figure 1K may be similar to the top view shown in Figure 2E As shown, insulating layer 270 can be in contact with the upper portions of the sidewall surfaces of interconnects 151, 152, 153.

[0088] Figures 3A-3C Various cross-sectional views of some embodiments of a method of forming an electronic component are illustrated. In some embodiments, Figures 3A-3C an exemplary method of forming an electronic component after the structure shown in Figure 2A may be depicted.

[0089] As Figure 3A shown in the cross-sectional view, structure 300A including insulating layer 389 is formed. The formation process and / or material of insulating layer 389 can be the same as or similar to the formation process and / or material of insulating layer 189 shown in Figure 2D . Insulating layer 389 can be in contact with the top surface of sacrificial layer 299 and the upper portions of the sidewall surfaces of interconnects 151, 152, 153.

[0090] As Figures 3A-3B shown in the cross-sectional view, a removal process is performed. The removal process can be performed on structure 300A shown in Figure 3A , and the removal process can be the same as or similar to the removal process shown in Figures 1H-1I or Figures 2B-2C . Thus, as Figure 3BAs shown in the cross-sectional view, a structure 300B is formed, including an air gap S1 located between two adjacent interconnects (e.g., between two interconnects 151 and 152 and two interconnects 151 and 153). A portion of the insulating layer 380 and a portion of the insulating layer 132 are perpendicularly spaced by the air gap S1, and the air gap S1 is closed by a portion of the insulating layer 132, a portion of the insulating layer 380, and interconnects 151, 152, and 153.

[0091] It is worth noting that this disclosure reserves the possibility that the sacrificial layer 299 may not have been completely removed. For example, a small amount of residual sacrificial layer 299 may be located on interconnects 151, 152, 153 and / or insulating layer 389.

[0092] like Figure 3C As shown in the cross-sectional view, a structure 300C is formed, including an insulating layer 380. (As...) Figures 3B-3C As shown, insulating layer 380 can be formed by removing a portion of insulating layer 389 by performing an appropriate removal process (e.g., planarization process). Furthermore, in the aforementioned removal process, capping layer 149 (e.g.) Figure 3B (As shown) is removed. After performing the aforementioned removal process, interconnects 151, 152, and 153 are exposed. The top surface 140a of interconnects 151, 152, and 153 and the top surface 380a of insulating layer 380 may be substantially coplanar.

[0093] like Figure 3C The structure 300C shown may be part of an electronic component. For example... Figure 3C As shown, the electronic component may include a substrate 110, a plurality of interconnects 151, 152, 153 located on the substrate 110, and an insulating layer 380 located between two adjacent interconnects (e.g., two interconnects 151 and 152 and two interconnects 151 and 153). An air gap S1 is formed between the insulating layer 380 and the substrate 110. The insulating layer 380 is laterally disposed between the upper portion 1511 of interconnect 151 and the upper portion 1521 of interconnect 152 and the upper portion 1531 of interconnect 153. In one embodiment, viewed from a top view, the air gap S1 surrounds at least one interconnect (e.g., interconnect 151).

[0094] like Figure 3C The electronic components shown may be related to Figure 2E The electronic components and / or shown Figure 1K The electronic components shown are similar, except that... Figure 3C The electronic components shown do not include Figure 2E The insulating layer 270 is shown. Furthermore... Figure 3C The partial top view of the electronic components shown may be related to Figure 1K The top view shown is similar. (As shown) Figure 3CAs shown, the insulating layer 380 can contact the upper portion of the sidewall surface of the interconnect 151, the interconnect 152, and the interconnect 153.

[0095] Figure 4 An exemplary cross-sectional view of a die (e.g., one of electronic components) 400 is illustrated. The die 400 can include a substrate, active components (e.g., transistors), passive components (e.g., resistors, capacitors, or inductors), and / or interconnect structures. The components can be formed using front-end-of-line (FEOL) fabrication techniques. The interconnect structures can be formed using back-end-of-line (BEOL) fabrication techniques and can be electrically connected to the corresponding components. As shown, Figure 4 As shown, the die 400 exemplarily depicts corresponding active components 41 and corresponding interconnect structures 42. The die 400 can be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die, an application-specific integrated circuit (ASIC) die, an application processor (AP) die, a system on chip (SoC) die, or a high performance computing (HPC) die, but the present disclosure is not limited thereto. The active components 41 and / or the interconnect structures 42 are exemplarily as shown in FIG. 1. Figure 4 As illustrated, the formation or type of the active components 41 and / or the interconnect structures 42 is not limited by the present disclosure.

[0096] The interconnect structures 42 can include a plurality of interconnect layers (e.g., M0 layer, M1 layer,... or Mn layer). Each interconnect layer can include corresponding interconnects. The corresponding interconnects in adjacent interconnect layers are electrically connected by corresponding conductive vias in the intervening conductive via layers (e.g., V1 layer, V2 layer,... or Vn-1 layer). The material of the M0 layer, the V1 layer, and / or the M1 layer can include copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), aluminum (Al). The thickness of the M0 layer, the V1 layer, and / or the M1 layer can be about 100 nm to about 500 nm, but the present disclosure is not limited thereto. to The conductive adhesive layer (e.g., conductive layer 121) may be made of tantalum (Ta), titanium (Ti), or other metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN)). The thickness of the conductive adhesive layer may be approximately [missing information]. to

[0097] The topmost interconnect layer in interconnect structure 42 may include multiple die pads. For example, die pad 48 may be a signal pad (e.g., an input / output pad (I / O pad)) and die pad 48 may be a ground pad. The corresponding interconnects in the bottommost interconnect layer (e.g., the MO layer) of interconnect structure 42 are electrically connected to the corresponding regions of the device (e.g., source S, drain D, or gate G, but this disclosure is not limited thereto) through one or more conductors (e.g., conductive vias).

[0098] Reference Figure 4 As with the foregoing diagrams, structures 100K, 200E, and 300C of the aforementioned embodiments may be part of grain 400. For example, as... Figure 4 The interconnects 51, 52, and 53 shown may be related to Figure 1K , Figure 2E and / or Figure 3C The interconnects 151, 152, and 153 shown in the diagram are the same or similar. Furthermore, for the sake of simplicity, Figure 4 The corresponding air gap S1 or insulation layer (e.g., insulation layer 180, insulation layer 380) is omitted.

[0099] Figure 5 Flowcharts illustrating some embodiments of methods for forming electronic components are shown.

[0100] In action 501, a structure including a substrate and at least one conductive layer located on the substrate is provided. Figure 1D Cross-sectional views corresponding to various embodiments of action 501 are illustrated. Optionally, multiple patterned or unpatterned layers or regions are disposed on or embedded in the substrate.

[0101] In action 502, the conductive layer is patterned to form interconnects and to form at least one trench laterally between the interconnects. Figure 1E Cross-sectional views corresponding to various embodiments of action 502 are illustrated. Optionally, in the cross-sectional views, the shape of the trench is the same as or similar to an inverted trapezoid or inverted triangle, and the shape of the interconnection is the same as or similar to a trapezoid.

[0102] In Action 503, a dielectric capping layer is selectively formed to cover the trench. Figure 1F Cross-sectional views corresponding to various embodiments of action 503 are shown.

[0103] In action 504, a sacrificial layer is formed in the trench. The top surface of the sacrificial layer is lower than the top surface of the conductive layer. Figure 1G , Figure 2A or Figure 3A Cross-sectional views corresponding to various embodiments of action 504 are shown.

[0104] In Action 505, an insulating support layer is selectively formed on the sacrificial layer and the trench is covered. Figure 1H or Figure 2B Cross-sectional views corresponding to various embodiments of action 505 are shown.

[0105] In action 506, at least a portion of the sacrificial layer is removed via a removal process to form an air gap. Figure 1I , Figure 2C or Figure 3B Cross-sectional views corresponding to various embodiments of action 506 are depicted.

[0106] In action 507, an insulating layer is formed covering the trench and laterally between the interconnects. Figure 1J , Figure 1K , Figure 2D , Figure 2E , Figure 3A , Figure 3B or Figure 3C Cross-sectional views corresponding to various embodiments of action 507 are depicted. For example... Figure 1K , Figure 2E or Figure 3C As shown, the top surface of the interconnect and the top surface of the insulating layer may be approximately coplanar.

[0107] like Figures 1I-1K , Figures 2C-2E or Figures 3B-3C As shown, the sacrificial layer can be removed before the insulating layer covering the trench is formed. Figures 3A-3C As shown, an insulating layer covering the trench can be formed before the sacrificial layer is removed.

[0108] Based on the above, in some embodiments, this disclosure relates to an electronic component comprising at least one interconnect, a space, and an insulating layer. The insulating layer is located on the space. The insulating layer and / or the space surrounds the at least one interconnect, or the dielectric layer and / or the space is located between two adjacent interconnects. The electronic component may have better electrical performance and / or heat dissipation.

[0109] According to some embodiments of the present disclosure, an electronic component includes a first interconnect, a second interconnect, and an insulating layer. A lower portion of the first interconnect is laterally spaced from a lower portion of the second interconnect by an air gap. The insulating layer is laterally between an upper portion of the first interconnect and an upper portion of the second interconnect. In an embodiment, a top dimension of the first interconnect is less than a bottom dimension of the first interconnect. In an embodiment, a top surface of the insulating layer is substantially coplanar with a top surface of the first interconnect, and a thickness of the insulating layer is less than a thickness of the first interconnect. In an embodiment, a thermal conductivity of the insulating layer is higher than a thermal conductivity of the first interconnect and the second interconnect, and the insulating layer is thermally coupled to the first interconnect and the second interconnect. In an embodiment, a product of the thickness and the thermal conductivity of the insulating layer is substantially equal to or greater than a product of the thickness and the thermal conductivity of the first interconnect. In an embodiment, the first interconnect and the second interconnect are substantially identical in thickness. In an embodiment, the electronic component further includes an insulating support layer extending from a sidewall of the upper portion of the first interconnect to a sidewall of the upper portion of the second interconnect. In an embodiment, the electronic component further includes a dielectric cap layer extending from a sidewall of the first interconnect to a sidewall of the second interconnect, wherein the air gap is enclosed by a portion of the insulating support layer and a portion of the dielectric cap layer. In an embodiment, a thermal conductivity of the dielectric cap layer is higher than a thermal conductivity of the first interconnect and the second interconnect, and the dielectric cap layer is thermally coupled to the first interconnect, the insulating layer, and the second interconnect. In an embodiment, the electronic component further includes an active element, wherein the first interconnect is electrically connected to and thermally coupled to the active element. In an embodiment, the first interconnect structurally overlaps the active element. In an embodiment, the second interconnect is electrically insulated from the first interconnect. In an embodiment, the second interconnect is a dummy pattern.

[0110] According to some embodiments of the present disclosure, an electronic component includes a substrate, an interconnect, a first insulating layer, and a second insulating layer. The interconnect is on the substrate. The first insulating layer is on the substrate. The second insulating layer is over the first insulating layer and surrounds the interconnect. A portion of the first insulating layer is vertically spaced from a portion of the second insulating layer by an air gap. In an embodiment, a thermal conductivity of the second insulating layer is higher than a thermal conductivity of the interconnect, and the second insulating layer is thermally coupled to the interconnect. In an embodiment, a product of a thickness and the thermal conductivity of the second insulating layer is substantially equal to or greater than a product of a thickness and the thermal conductivity of the interconnect. In an embodiment, the electronic component further includes an active element on the substrate, wherein the interconnect is electrically connected to and thermally coupled to the active element, and the interconnect structurally overlaps the active element.

[0111] According to some embodiments of the present disclosure, a method includes providing a structure including a substrate and at least one conductive layer on the substrate; patterning the conductive layer to form interconnects and at least one trench laterally between the interconnects; forming a sacrificial layer in the at least one trench; forming a first insulating layer covering the at least one trench; and performing a removal process to remove at least a portion of the sacrificial layer and form an air gap. In one embodiment, the first insulating layer includes an insulating support layer on the interconnects and the sacrificial layer, and the method further includes forming a second insulating layer on the first insulating layer and laterally between the interconnects. In one embodiment, the first insulating layer has a higher thermal conductivity than the interconnects.

[0112] The above summary presents several embodiments in order to provide a better understanding of the present disclosure. It should be apparent to those skilled in the art that they can design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein without departing from the spirit and scope of the present disclosure. It should also be apparent to those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

[0113] Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the present disclosure, rather than limiting them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some or all of the technical features; and such modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic component, characterized by comprising: comprising: a first interconnect; a second interconnect, wherein a lower portion of the first interconnect is laterally spaced from a lower portion of the second interconnect by an air gap; and an insulating layer laterally between an upper portion of the first interconnect and an upper portion of the second interconnect, wherein a product of a thickness and a thermal conductivity of the insulating layer is equal to or greater than a product of a thickness and a thermal conductivity of the first interconnect.

2. The electronic component according to claim 1, characterized in that, wherein a top dimension of the first interconnect is less than a bottom dimension of the first interconnect.

3. The electronic component of claim 1, wherein wherein a top surface of the insulating layer is coplanar with a top surface of the first interconnect, and a thickness of the insulating layer is less than a thickness of the first interconnect.

4. The electronic component of claim 1, wherein wherein the first interconnect and the second interconnect are the same in thickness.

5. The electronic component of claim 1, wherein further comprising: an insulating support layer extending from a sidewall of the upper portion of the first interconnect to a sidewall of the upper portion of the second interconnect.

6. The electronic component of claim 5, wherein further comprising: a dielectric cap layer extending from a sidewall of the first interconnect to a sidewall of the second interconnect, wherein the air gap is enclosed by a portion of the insulating support layer and a portion of the dielectric cap layer.

7. The electronic component of claim 1, wherein further comprising: an active element, wherein the first interconnect is electrically connected to and thermally coupled to the active element.

8. The electronic component of claim 7, wherein wherein the first interconnect and the active element structurally overlap.

9. The electronic component of claim 7, wherein wherein the second interconnect is electrically insulated from the first interconnect.

10. An electronic component, characterized by comprising: comprising: a substrate; an interconnect on the substrate; a first insulating layer on the substrate; and a second insulating layer over the first insulating layer and surrounding the interconnect, wherein a portion of the first insulating layer is vertically spaced from a portion of the second insulating layer by an air gap.

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