Radio frequency identification chip
By employing a diode-based electrostatic discharge circuit in the RFID chip, the problem of insufficient anti-static capability was solved, resulting in a smaller layout area and stronger electrostatic discharge capability, thereby improving the chip yield and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2026-03-31
AI Technical Summary
Insufficient anti-static capability during the manufacturing process of radio frequency identification chips leads to yield loss. Existing electrostatic discharge circuits occupy a large area and affect chip performance.
A diode-based electrostatic discharge circuit is adopted, including a first diode and a second diode, which connects the input and output ports with the charge discharge path, reducing the layout area and optimizing the breakdown weak points, thereby enhancing the electrostatic discharge capability.
It effectively protects chips from electrostatic damage, reduces defect rates, minimizes the area occupied by electrostatic discharge circuits on the chip, and improves chip performance.
Smart Images
Figure CN224067227U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electrostatic discharge protection, and in particular to a radio frequency identification chip with electrostatic discharge protection. Background Technology
[0002] Radio Frequency Identification (RFID) chips, also known as RFID tags, communicate with card readers in a contactless manner to achieve target identification.
[0003] The manufacturing supply chain for RFID chips is quite long, including chip manufacturing, antenna processing, inlay processing, lamination, printing, and labeling. RFID chip manufacturing involves multiple processing stages, which are geographically dispersed. Each stage generates some defects and yield losses, with anti-static capability being a crucial indicator affecting yield. Utility Model Content
[0004] In view of this, this application provides a radio frequency identification (RFID) chip with electrostatic discharge (ESD) protection. The RFID chip includes an antenna, an input / output port, a protected circuit, and a charge discharge path. The input / output port is connected to the antenna. The protected circuit is connected to the input / output port. The ESD discharge circuit includes a first diode and a second diode. The anode of the first diode is connected to the input / output port, and the cathode of the first diode is connected to the charge discharge path. The cathode of the second diode is connected to the input / output port, and the anode of the second diode is connected to the charge discharge path.
[0005] In some embodiments, the RFID chip further includes a sealing ring, which serves as the charge release path.
[0006] In some embodiments, the layout of the first diode and the second diode is rectangular.
[0007] In some embodiments, the radio frequency identification chip further includes a guard ring.
[0008] In some embodiments, the input / output port includes a first input / output port and a second input / output port, wherein the first input / output port is connected to the charge release path through a first diode and a second diode, and the second input / output port is connected to the charge release path through a first diode and a second diode.
[0009] According to the technical solution of this application, the input / output ports of the RFID chip are connected to the charge release path through an electrostatic discharge (ESD) circuit. The ESD circuit includes a first diode and a second diode. The anode of the first diode is connected to the input / output port, and the cathode of the first diode is connected to the charge release path. The cathode of the second diode is connected to the input / output port, and the anode of the second diode is connected to the charge release path. Compared to ESD circuits based on GGMOS, transistors, or RC structures, the diode-based ESD circuit has a smaller layout area, reducing the parasitic capacitance introduced by the ESD circuit. Attached Figure Description
[0010] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0011] Figure 1 A circuit diagram of a radio frequency identification chip according to an embodiment of this application is shown;
[0012] Figure 2 A circuit diagram of an electrostatic discharge circuit is shown.
[0013] Figure 3 This application illustrates a radio frequency identification chip according to another embodiment;
[0014] Figure 4 This application illustrates a radio frequency identification chip according to another embodiment;
[0015] Figure 5 This application illustrates a radio frequency identification chip according to another embodiment;
[0016] Figure 6 This application illustrates a radio frequency identification chip according to another embodiment;
[0017] Figure 7 The protected circuit of the RFID chip is shown. Detailed Implementation
[0018] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0019] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0020] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0021] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0022] Unless otherwise specified, the embodiments and features described in this application may be combined arbitrarily with each other.
[0023] This application provides a radio frequency identification (RFID) chip, comprising: an antenna, an input / output (Input / Output) port, a protected circuit, an electrostatic discharge (ESD) circuit, and a charge release path. The input / output port is connected to the antenna. The protected circuit is connected to the input / output port. The ESD circuit includes a first diode and a second diode. The anode of the first diode is connected to the input / output port, and the cathode of the first diode is connected to the charge release path. The cathode of the second diode is connected to the input / output port, and the anode of the second diode is connected to the charge release path. The input / output port is a pad with a certain area. The RFID chip receives signals sent by a card reader through the antenna and sends signals back to the card reader through the antenna.
[0024] Figure 1 This is a circuit diagram of an exemplary RFID chip. Figure 1 As shown, the RFID chip 10 includes: an antenna, a first input / output port 101, a second input / output port 102, a protected circuit 103, and an electrostatic discharge (ESD) circuit 104. The RFID chip can be either an active or passive RFID chip. An active RFID chip has its own power supply module and can actively transmit signals. A passive RFID chip receives power from the card reader via its antenna, operates based on the received power, and transmits response signals via the antenna.
[0025] The first input / output port 101 is connected to the first end of the antenna, and the second input / output port 102 is connected to the second end of the antenna. The protected circuit 130 is connected to the first input / output port 101 and the second input / output port 102. For example, the protected circuit 130 is connected to the first input / output port 101 and the second input / output port 102 via transmission lines 106 and 107, respectively. The protected circuit 130 includes multiple circuit modules, such as RF front-end circuits, power management circuits, clock generation circuits, digital circuits, and memory. The RF front-end circuit includes, for example, voltage clamping circuits, rectifier circuits, and modulation / demodulation circuits. Figure 1 As shown, the exemplary protected circuit 130 includes circuit modules 131 and 132.
[0026] Electrostatic discharge (ESD) is a phenomenon that instantaneously releases electrical charge. When a charged object comes into contact with a chip, the charge on the object is released to the chip through its ports. This discharge can generate very high currents and voltages, potentially damaging the circuitry or degrading the chip's performance. The ESD circuit 140 provides a low-impedance discharge path for static electricity at the first input / output port 101 and the second input / output port 102, releasing the charge to ground and preventing excessive charge from entering the protected circuit 130.
[0027] Figure 2 A circuit diagram of an electrostatic discharge circuit is shown. (For example...) Figure 2 As shown, the electrostatic discharge circuit 140 includes a first electrostatic discharge circuit 141 and a second electrostatic discharge circuit 142. The first electrostatic discharge circuit 141 is connected between the first input / output port 101 and the charge release path 105. The second electrostatic discharge circuit 142 is connected between the second input / output port 102 and the charge release path 105. The charge release path 105 is grounded.
[0028] The first electrostatic discharge circuit 141 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the first input / output port 101, and the cathode of the first diode D1 is connected to the charge discharge path 105. The cathode of the second diode D2 is connected to the first input / output port 101, and the anode of the second diode D2 is connected to the charge discharge path 105. That is, the first diode D1 and the second diode D2 are connected in parallel in reverse.
[0029] The second electrostatic discharge circuit 142 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the second input / output port 102, the cathode of the first diode D2 is connected to the charge discharge path 105, the cathode of the second diode D2 is connected to the second input / output port 102, and the anode of the second diode D2 is connected to the charge discharge path 105.
[0030] When the RFID chip is working normally, the voltage difference between the first input / output port 101 and the second input / output port 102 is usually less than 100mV. Therefore, the first electrostatic discharge circuit 141 and the second electrostatic discharge circuit 142 will not electrically connect the first input / output port 101 and the second input / output port 102.
[0031] When a large amount of positive charge appears at the first input / output port 101, the second diode D2 of the first electrostatic discharge circuit 141 breaks down, becoming a low-impedance path. The charge is released through the second diode D2 and the charge release path 105, and will not enter the protected circuit 130. When a large amount of negative charge appears at the first input / output port 101, the first diode D1 of the first electrostatic discharge circuit 141 breaks down, becoming a low-impedance path. The charge is released through the first diode D1 and the charge release path 105, and will not enter the protected circuit 130.
[0032] In some embodiments, the first diode D1 and the second diode D2 of the first electrostatic discharge circuit 141 and the second electrostatic discharge circuit 142 are Zener diodes.
[0033] The RFID chip 10 is fabricated, for example, on a P-type silicon substrate. A first diode D1 and a second diode D2 are formed in an N-well within the P-type silicon substrate. The layout area of the first diode D1 and the second diode D2 refers to the area of the N-well containing the diodes. The layout area of the first diode D1 and the second diode D2 can be simulated and optimized using a Human Body Model (HBM). The HBM is used to simulate the electrostatic discharge phenomenon that may occur when a charged human body touches an electronic device (e.g., the RFID chip 10). After determining the layout area of the first diode D1 and the second diode D2, the perimeter and shape of the layout of the first diode D1 and the second diode D2 are further determined. For the same layout area, a longer layout perimeter results in a larger cross-section of the diode and a stronger electrostatic discharge capability. This ensures the electrostatic discharge capability of the RFID chip while maintaining its area and the performance of its input / output ports. In some embodiments, the layout shape of the first diode D1 and the second diode D2 is rectangular, i.e., the first diode D1 and the second diode D2 are rectangular from a top-view perspective.
[0034] Simulations for optimizing diode area can also be based on machine models, charging device models, IEC models, TLP (Transmission LinePulse) models, etc.
[0035] In some embodiments, the first electrostatic discharge circuit 141 includes a first diode D1 and a second diode D2, and the second electrostatic discharge circuit 142 includes a first diode D1 and a second diode D2.
[0036] In some embodiments, the first electrostatic discharge circuit 141 includes a plurality of first diodes D1 connected in parallel and a plurality of second diodes D2 connected in parallel.
[0037] In some embodiments, internal breakdown weak points are optimized by adjusting the layout to increase the impedance from the input / output ports to the interior.
[0038] Figure 3 A radio frequency identification chip according to another embodiment of this application is shown. For example... Figure 3 As shown, the RFID chip 10 further includes a capacitor 108 connected between the first input / output terminal 101 and the protected circuit 130, and a capacitor 109 connected between the second input / output terminal 102 and the protected circuit 130. Capacitors 108 and 109 are preferably MIM (Metal-Insulator-Metal) capacitors. Specifically, the connection point between the first input / output terminal 101 and the first diode D1 and the second diode D2 is node A, and capacitor 108 is connected between node A and the protected circuit 130. The connection point between the second input / output terminal 102 and the first diode D1 and the second diode D2 is node B, and capacitor 108 is connected between node B and the protected circuit 130. By setting capacitors 108 and 109, the withstand voltage capability of the protected circuit 130 can be increased.
[0039] In some embodiments, capacitors 108 and 109 are respectively provided between circuit module 131 and the first input / output terminal 101 and the second input / output terminal 102, and capacitors 108 and 109 are respectively provided between circuit module 132 and the first input / output terminal 101 and the second input / output terminal 102.
[0040] Figure 4 A radio frequency identification chip according to another embodiment of this application is shown. For example... Figure 4 As shown, the RFID chip 10 further includes a resistor 111 connected between the first input / output terminal 101 and the protected circuit 130, and a resistor 112 connected between the second input / output terminal 102 and the protected circuit 130. Specifically, the connection point between the first input / output terminal 101 and the first diode D1 and the second diode D2 is node A, and resistor 111 is connected between node A and the protected circuit 130. The connection point between the second input / output terminal 102 and the first diode D1 and the second diode D2 is node B, and resistor 112 is connected between node B and the protected circuit 130. By setting resistors 111 and 112, the withstand voltage capability of the protected circuit 130 can be increased.
[0041] In some embodiments, resistors 111 and 112 are respectively provided between circuit module 131 and the first input / output terminal 101 and the second input / output terminal 102, and resistors 111 and 112 are respectively provided between circuit module 132 and the first input / output terminal 101 and the second input / output terminal 102.
[0042] Figure 5 A radio frequency identification chip according to another embodiment of this application is shown. For example... Figure 5 As shown, the RFID chip 10 further includes: a capacitor 108 and a resistor 111 connected between the first input / output terminal 101 and the protected circuit 130, and a capacitor 109 and a resistor 112 connected between the second input / output terminal 102 and the protected circuit 130. Specifically, the connection point between the first input / output terminal 101 and the first diode D1 and the second diode D2 is node A, and the capacitor 108 and resistor 111 are connected between node A and the protected circuit 130. The connection point between the second input / output terminal 102 and the first diode D1 and the second diode D2 is node B, and the resistor 112 is connected between node B and the protected circuit 130.
[0043] Figure 6 A radio frequency identification (RFID) chip according to another embodiment of this application is shown. The RFID chip 10 also includes a seal ring 105. The seal ring 105 serves as a charge discharge path 105. An exemplary seal ring 105 includes structures such as a metal layer, an oxide layer, and a passivation layer, and the seal ring 105 protects the protection circuit 130 within the ring. For example, the seal ring 105 is disposed between the protection circuit 130 and the scribe line. By reusing the seal ring as a charge discharge path for the electrostatic discharge circuit 140, the impedance between the electrostatic discharge loops is reduced, enhancing the electrostatic discharge capability while simultaneously reducing the chip area.
[0044] Figure 7 The internal circuitry of the RFID chip is shown. (Example) Figure 7 As shown, both circuit modules 131 and 132 are surrounded by guard rings 113. For example, the RFID chip 10 is fabricated on a P-type substrate, and circuit module 131 is fabricated in an N-well; the guard ring 113 of circuit module 131 is an N-type guard ring. By setting the guard ring 113, the substrate resistance can be reduced, and the breakdown voltage of the circuit module can be improved.
[0045] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A radio frequency identification chip, characterized by The radio frequency identification chip comprises: an antenna; an input-output port connected to the antenna; a protected circuit connected to the input-output port; an electrostatic discharge circuit; and a charge release path, the electrostatic discharge circuit comprises a first diode and a second diode, an anode of the first diode is connected to the input-output port, a cathode of the first diode is connected to the charge release path, a cathode of the second diode is connected to the input-output port, and an anode of the second diode is connected to the charge release path.
2. The radio frequency identification chip of claim 1, wherein, The radio frequency identification chip further comprises a sealing ring, and the sealing ring serves as the charge release path.
3. The radio frequency identification chip of claim 1, wherein, Layouts of the first diode and the second diode are rectangular.
4. The radio frequency identification chip of claim 1, wherein, The radio frequency identification chip further comprises a protection ring.
5. The radio frequency identification chip of claim 1, wherein, The input-output port comprises a first input-output port and a second input-output port, the first input-output port is connected to the charge release path through one first diode and one second diode, and the second input-output port is connected to the charge release path through one first diode and one second diode.