Full-localization video decoding deck

Abstract

The full-localization video decoding board comprises a processor adopting a domestic chip, an FPGA (Field Programmable Gate Array), a storage unit, an interface unit and a power supply system, the interface unit comprises a first connector and a second connector; a serial port of the processor is connected to the first connector through the serial port conversion chip; the output end of the processor is connected with the receiving end of the FPGA; the FPGA is connected to the second connector through the first conversion chip and the second conversion chip in sequence; the first conversion chip is used for converting an RGB signal output by the FPGA into a VGA single-ended signal and accessing the VGA single-ended signal to the second conversion chip; the second conversion chip is used for converting the VGA single-ended signal into an XGA signal and outputting the XGA signal to the second connector; the FPGA is further connected to the second connector through a third conversion chip, and the third conversion chip is used for converting RGB signals output by the FPGA into VGA single-end signals and outputting the VGA single-end signals to the second connector. The utility model has the advantages of simple circuit structure, low cost, strong compatibility, high transmission stability and the like.

Description

Technical Field

[0001] This utility model relates to the field of video decoding technology, and in particular to a fully domestically produced video decoding board. Background Technology

[0002] The function of a video decoding board is to decode compressed video data and restore it into a playable video stream. The decoding board processes the video stream using specific algorithms, converting compressed data into recognizable image frames, enabling playback or further analysis. In practical applications, the performance of the decoding board is crucial in many fields, especially real-time monitoring and video analytics. Decoding boards are widely used in defense, government, scientific research, and communications, holding significant strategic importance. In the past, decoding boards were mainly imported, facing external technological restrictions and supply risks. With national information security receiving increasing attention, localization and self-reliance are the ongoing pursuit of all technical personnel in this field.

[0003] Furthermore, some video decoding boards on the market use domestically produced chips for signal decoding. These boards typically have different types of interfaces to support various signal input and output requirements. However, due to the significant differences in the interface formats supported by different decoding boards, users often need to select the appropriate interface type based on their specific application requirements. Designing various interface formats on the decoding board would lead to increased power consumption, higher costs, and increased complexity. Since different applications have different requirements for signal input and output, this application urgently needs to design a completely domestically produced, simple video decoding board capable of meeting the application requirements of HDMI, VGA, XGA, and other signal formats. Utility Model Content

[0004] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide a domestically produced video decoding board with simple circuit structure, low cost, strong compatibility, and high transmission stability.

[0005] The technical solution of this utility model is: a fully domestically produced video decoding board, including a processor, FPGA, storage unit, interface unit, and power system using domestically produced chips; the interface unit includes a first connector and a second connector; the serial port of the processor is connected to the first connector through a serial port conversion chip, for receiving externally transmitted video compressed data through the first connector; the output of the processor is connected to the receiving end of the FPGA, for receiving the video signal generated after decoding by the processor, and converting the video signal into RGB format; the FPGA is connected to the second connector in sequence through the first conversion chip and the second conversion chip; the first conversion chip is used to convert the RGB signal output by the FPGA into a VGA single-ended signal and input it to the second conversion chip, and the second conversion chip is used to convert the VGA single-ended signal into an XGA signal and output it to the second connector; the FPGA is also connected to the second connector through a third conversion chip, and the third conversion chip is used to convert the RGB signal output by the FPGA into a VGA single-ended signal and output it to the second connector.

[0006] Furthermore, the processor used is the domestically produced Rockchip RK3588 processor.

[0007] Furthermore, the storage unit includes a first memory chip and a first storage chip connected to the processor, and a second memory chip and a second storage chip connected to the FPGA; the second memory chip is used for video data caching of the FPGA.

[0008] Furthermore, the interface unit also includes a debugging interface, and the processor is connected to the debugging interface through a gigabit Ethernet PHY chip; the processor is also connected to the debugging interface through a dedicated Uart1 interface; the FPGA is connected to the debugging interface through a JTAG debugging port.

[0009] Furthermore, the serial port conversion chip is an RS422 serial port chip.

[0010] Furthermore, the interface unit also includes a third connector, through which the processor is connected to a device that supports an HDMI interface via the third connector.

[0011] Furthermore, the FPGA provides SPI interface, IIC interface, GPIO interface, and UART interface to interact with the RK3588.

[0012] Furthermore, the FPGA is connected to the processor's output via a MIPI receiver port to receive video signals of the corresponding format decoded by the processor.

[0013] Furthermore, the first conversion chip uses the GMG7123 chip, while the second and third conversion chips use the GM7148 chip.

[0014] Furthermore, the FPGA provides one SPI interface, one IIC interface, two GPIO interfaces, and two UART interfaces to interact with the RK3588.

[0015] The beneficial effects of this utility model are:

[0016] (1) By adopting the RK3588+FPGA framework to implement video decoding function, the performance and flexibility of the system can be effectively improved; the RK3588 processor is used to receive externally transmitted video compression data and decode and output it, while the FPGA is used to implement video format conversion, ensuring the compatibility and diversity of video signals, and better meeting different video processing needs.

[0017] (2) All chips are domestically designed, which reduces system costs, enhances self-controllability, and reduces dependence on external suppliers;

[0018] (3) The video data is received through RS422 signal and the decoded video signal is output and displayed through XGA or VGA signal. The number of chips used is small, which can ensure the compatibility between modern display devices and old devices.

[0019] (4) The FPGA provides one MIPI receiver port connected to the output of the RK3588 processor to receive the decoded video signal and buffer it before converting it into RGB format. On the one hand, the MIPI receiver port provides high-speed and low-power transmission capabilities, which can effectively reduce the delay and signal loss during data transmission and ensure high-quality transmission of video signals. Moreover, the MIPI interface supports high bandwidth and can handle high-definition video and large-volume video streams, which are suitable for high-resolution and high-frame-rate application scenarios. At the same time, the widespread application and standardization of the MIPI protocol ensures compatibility between different devices and improves the reliability and scalability of the system. On the other hand, the conversion of RGB format makes the video signal more compatible with various display devices, ensuring accurate image quality reproduction and compatibility.

[0020] (5) By setting up an RS422 serial port chip to receive video data, it has stable signal transmission and long-distance communication capabilities. That is, the RS422 standard supports differential signal transmission, which can effectively resist electromagnetic interference and ensure high-quality signal transmission even in complex industrial environments. In addition, RS422 has a long transmission distance, which is suitable for application scenarios that require remote transmission of video data. Compared with traditional single-ended signal transmission, differential signal not only improves noise immunity but also reduces signal attenuation, ensuring the integrity and accuracy of video data. Attached Figure Description

[0021] Figure 1This is a schematic diagram of the circuit principle of an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1 The image shows a domestically produced video decoding board, installed inside a chassis. It is a non-standard board, primarily functioning to receive image streams, decode them, and output them via an XGA interface. The decoding board communicates externally through its network port, XGA port, and RS422 interface.

[0024] The decoding board includes a processor, FPGA, storage unit, interface unit, and power system. The power system supplies power to all components. The storage unit is connected to both the processor and FPGA, and the processor and FPGA are connected via interfaces with different functions. The interface unit includes connectors XS1, XS2, and XS3, and a debugging interface. Connector XS1 is used to send compressed video data from external devices to the decoding board. Connector XS2 is used to send the decoded video signal to the display device. Connector XS3 is used to output the decoded video signal to a device that supports an HDMI interface.

[0025] In this embodiment, the power supply system supplies power to the decoding board via connector XS1, using a +5V DC input, which is converted into the voltage required by each device by a DC / DC converter chip to power each device on the decoding board.

[0026] In this embodiment, the processor preferably uses the domestically produced Rockchip RK3588 processor, a high-end general-purpose SoC using an 8nm process. The CPU employs an octa-core architecture with four A76 cores and four A55 cores, while the GPU is a Mali G610 MP4 with an integrated 6-TOPS independent NPU. It supports quad-channel LPDDR4 / 5, hardware encoding and decoding of 8K video, and can decode and output at up to 8K@60fps. In short, the RK3588 uses an independent hardware decoder, resulting in higher decoding efficiency, effectively reducing power consumption, and not consuming CPU resources. This allows the CPU to continue processing other applications, ensuring performance.

[0027] In this embodiment, according to the decoding board's technical protocol requirements, the video output interface is an XGA signal. However, the RK3588's video output interface cannot support the requirements of the current technical protocol. For these reasons, an FPGA chip is needed to complete the video data format conversion and interface design. After comprehensively evaluating the logic resources required to implement the interface requirements in the technical protocol and the requirements for domestic production, Fudan Microelectronics' JFM7K325T-N was selected as the FPGA chip for the video decoding board.

[0028] In this embodiment, the storage unit includes a first memory chip and a first storage chip connected to the RK3588 processor, and a second memory chip and a second storage chip connected to the FPGA.

[0029] Specifically, the first memory chip is preferably a 4GB RS1G32LO4D2BDS-46IT surface-mount memory chip from Crystal Memory. The RK3588 processor provides two 32-bit LPDDR4x memory controller interfaces. Considering the size of the decoding board and the required capacity, 32-bit LPDDR4x is chosen. Each channel requires only one 32-bit memory chip, for a total of two chips, forming two 32-bit dual-channel 8GB memory capacities. The memory controller bandwidth reaches 29.8GB / s. Furthermore, using surface-mount memory chips instead of the traditional memory slot and memory module method enhances the board's vibration and shock resistance. The FPGA design uses 1GB of DDR3 memory as video data cache, and the second memory chip uses two XZF41J256M16 chips from Zhongtian Xingkong.

[0030] The first storage chip is a 32GB eMMC chip, connected to the storage side of the RK3588 processor, used to store the file system, operating system, and upgradeable programs. A Guowei SMFC32GBMP device is selected. The second storage chip is a NOR Flash chip, specifically one EFM25F128A chip configured in the FPGA to form a 16MB capacity, used to store the FPGA's configuration file.

[0031] In this embodiment, the RK3588 processor is connected to the debugging interface via a Gigabit Ethernet PHY chip. Specifically, the decoding board provides one Gigabit Ethernet port for debugging, supporting 1000 / 100Mbps auto-negotiation. The design uses the domestically produced JXYI8211QFN Gigabit Ethernet PHY chip from Yutai Microelectronics. Through the RK3588 processor's built-in RGMII port, one 1000 / 100 / 10Mbps auto-negotiation Ethernet interface can be implemented.

[0032] In this embodiment, the RK3588 processor is connected to the debug interface via a USB download interface, enabling system or U-Boot upgrades. An external PC can download the file system or IMG file required by the RK3588 processor, facilitating upgrades for the customer. The RK3588 processor also connects to the debug interface via a dedicated UART1 interface for printing system boot logs. An external PC can observe the boot process of parts of the RK3588 processor system, facilitating debugging for the user.

[0033] In this embodiment, the FPGA is connected to the debug interface via the JTAG debug port to provide debug access.

[0034] In this embodiment, the UART interface of the RK3588 processor is connected to connector XS1 via an RS422 serial port chip. Connector XS1 serves as the input terminal for video compression data, used to send externally transmitted video compression data to the decoding board. For example, the decoding board connects to an interface board via connector XS1, and the interface board sends video compression data to the RS422 serial port chip on the decoding board for signal conversion before sending it to the RK3588 processor. The RS422 serial port chip used is the CP3490S from Chuantu Microelectronics. It is understood that the decoding board can be configured with multiple synchronous RS422 serial ports to receive video compression data.

[0035] In this embodiment, the RK3588 processor can also be directly connected to a device that supports an HDMI interface via the HDMI interface and connector XS3.

[0036] In this embodiment, the FPGA provides one SPI interface, one IIC interface, two GPIO interfaces, and two UART interfaces to interact with the RK3588; the FPGA also provides one MIPI receiving port, which is connected to the output of the RK3588 processor to receive the corresponding format video signal after being decoded by the RK3588 processor. After receiving the data, the FPGA buffers it and converts the buffered data into RGB format.

[0037] In this embodiment, the FPGA is connected to connector XS2 sequentially via a first conversion chip and a second conversion chip. The first conversion chip converts the RGB signal output by the FPGA into a VGA signal, which is then fed into the second conversion chip. The second conversion chip converts the VGA signal into an XGA signal and outputs it to connector XS2, from where it is sent to the display device. In other words, after receiving the signal from the RK3588 processor, the FPGA converts it into an RGB signal, which is then fed into the first conversion chip, where it is converted into a VGA single-ended signal. The second conversion chip then converts the VGA single-ended signal into the required XGA signal for output. Preferably, the first conversion chip is a GMG7123 chip, and the second conversion chip is a GM7148 chip.

[0038] In this embodiment, the FPGA is also connected to connector XS2 via a third conversion chip. This third conversion chip converts the RGB signal output from the FPGA into a VGA single-ended signal for output to connector XS2. The third conversion chip also uses the GM7148 chip.

[0039] This embodiment, by designing one XGA interface and reserving one VGA interface, can accommodate different display needs, provide diversified display support, and reduce costs. Specifically, the XGA interface provides higher resolution, suitable for applications requiring high-resolution displays, and is commonly used in modern monitors and devices; the VGA interface is an older but still widely used display interface, suitable for lower-resolution display devices, especially older monitors or devices that do not support digital interfaces. Reserving a VGA interface allows the design to be compatible with more devices, ensuring compatibility with older equipment. Furthermore, reserving a VGA interface reduces the need for adapters or additional conversion devices. If the device only provides an XGA interface while the monitor only supports VGA input, an additional converter needs to be purchased, increasing costs. By providing both interfaces simultaneously, this additional expense can be avoided.

[0040] The working principle of the decoding board in this embodiment is as follows: The decoding board receives video compressed data transmitted from an external device through connector XS1. Specifically, the received video compressed data is converted into a signal by an RS422 serial port chip and then sent to the RK3588 processor. The RK3588 processor decodes the video compressed data and then sends the resulting MIPI signal to the FPGA for buffering via the FPGA's MIPI receiving port. The FPGA converts the buffered data into RGB format and outputs it to the first conversion chip. The first conversion chip converts the RGB signal output by the FPGA into a VGA single-ended signal and inputs it to the second conversion chip. The second conversion chip converts the VGA single-ended signal into an XGA signal and outputs it to connector XS2, which then outputs it to the display device. Alternatively, the FPGA converts the buffered data into RGB format and outputs it to the third conversion chip. The third conversion chip converts the RGB signal into a VGA single-ended signal and outputs it to connector XS2, which then outputs it to the display device. Or, the RK3588 processor converts the decoded video signal into HDMI format and sends it to a device that supports an HDMI interface via connector XS3.

[0041] In summary, this embodiment, by employing an RK3588+FPGA framework to implement video decoding, effectively improves system performance and flexibility. The RK3588 processor receives and decodes externally transmitted compressed video data, while the FPGA handles video format conversion, ensuring video signal compatibility and diversity, and better addressing various video processing needs. Furthermore, all chips are domestically designed, reducing system costs, enhancing self-control, and minimizing reliance on external suppliers. On the other hand, the terminal primarily receives video data via RS422 signals and outputs the decoded video signal via XGA or VGA signals for display. The use of fewer chips ensures compatibility between modern and older display devices.

Claims

1. A national production video decoding board, comprising a processor, an FPGA, a storage unit, an interface unit and a power supply system using domestic chips; the interface unit comprises a first connector and a second connector; characterized in that, A serial port of the processor is connected to the first connector through a serial port conversion chip, for receiving video compression data sent by an external device through the first connector; an output end of the processor is connected to a receiving end of the FPGA, for receiving a video signal generated after decoding by the processor and converting the video signal into an RGB format; the FPGA is connected to the second connector through the first conversion chip and the second conversion chip in sequence; the first conversion chip is used to convert the RGB signal output by the FPGA into a VGA single-end signal and input the VGA single-end signal into the second conversion chip, and the second conversion chip is used to convert the VGA single-end signal into an XGA signal and output the XGA signal to the second connector; the FPGA is also connected to the second connector through the third conversion chip, and the third conversion chip is used to convert the RGB signal output by the FPGA into a VGA single-end signal and output the VGA single-end signal to the second connector.

2. The nationally produced video decoding board according to claim 1, wherein The processor is a domestic Ruiyi micro RK3588 processor.

3. The nationally produced video decoding board according to claim 1, wherein, The storage unit includes a first memory chip and a first storage chip connected to the processor, and a second memory chip and a second storage chip connected to the FPGA; the second memory chip is used for video data buffering of the FPGA.

4. The nationally produced video decoding board according to claim 2, wherein The interface unit further includes a debugging interface, the processor is connected to the debugging interface through a gigabit Ethernet PHY chip; the processor is also connected to the debugging interface through a dedicated Uart1 interface; the FPGA is connected to the debugging interface through a JTAG debugging port.

5. The nationally produced video decoding board according to claim 1, wherein, The serial port conversion chip is an RS422 serial port chip.

6. The nationally produced video decoding board according to claim 1, wherein, The interface unit further includes a third connector, the processor is connected to a device supporting an HDMI interface through the third connector via an HDMI interface.

7. The nationally produced video decoding board according to claim 1, wherein The FPGA is provided with an SPI interface, an IIC interface, a GPIO interface, a UART interface and RK3588 for interaction.

8. The nationally produced video decoding board according to claim 1, wherein, The FPGA is connected to an output end of the processor through an MIPI receiving port, for receiving a video signal of a corresponding format decoded by the processor.

9. The nationally produced video decoding board according to claim 1, wherein, The first conversion chip is a GMG7123 chip, and the second conversion chip and the third conversion chip are GM7148 chips.

10. The nationally produced video decoding board according to claim 7, wherein, The FPGA is provided with one SPI interface, one IIC interface, two GPIO interfaces and two UART interfaces for interaction with RK3588. The FPGA is provided with one SPI interface, one IIC interface, two GPIO interfaces and two UART interfaces for interaction with RK3588.

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