Segmented power device

Abstract

The utility model provides a separately-packaged power device, which is based on a separately-packaged packaging mode, divides a target packaging circuit into two groups of separately-packaged circuits, separately packages the two groups of separately-packaged circuits on two substrates, and carries out combined packaging by taking the two substrates as an upper substrate and a lower substrate. And meanwhile, the electric connection relation between the two groups of sub-packaging circuits is formed based on the sealing between the two substrates, so that the target sub-packaging circuit is formed, and the target packaging circuit is correspondingly packaged in the packaging structure between the two substrates in a sub-packaging manner. And an up-and-down bidirectional heat dissipation channel is formed, so that the heat dissipation performance of the divided power device is ensured.

Description

Technical Field

[0001] This utility model relates to the field of power device packaging, and in particular to a packaged power device. Background Technology

[0002] Advances in semiconductor technology have greatly promoted the development and application of power electronic systems. Power semiconductor devices, as a core component of power electronic systems, are widely used in fields such as daily life, transportation, power, industrial control, and aerospace. Over the past few decades, with the continuous improvement of chip manufacturing processes, the size of semiconductor chips has been reduced, allowing more chips to be integrated into the same volume to achieve more powerful functions. As a result, the power density of power semiconductor devices has also been increased.

[0003] However, as chip size shrinks, the thermal resistance increases, while the heat capacity decreases, resulting in a higher junction temperature. This leads to more pronounced junction temperature fluctuations, impacting the reliability of power semiconductor devices. In other words, current power semiconductor devices are characterized by high voltage, high power, and high temperature, posing a significant challenge to the heat dissipation of their packaging structures. A good packaging structure needs to balance the stability of both the electrical and mechanical properties of power semiconductor devices, and high temperature is a major factor affecting both. Therefore, when designing the packaging structure of power semiconductor devices, effectively and promptly dissipating the heat generated by the chip to the external environment within a limited packaging space to ensure the stability of the electrical and mechanical properties has become a primary consideration in packaging design.

[0004] Current power semiconductor device packaging mainly adopts methods corresponding to Figure 1 and Figure 2 Two packaging structure designs. Specifically, in corresponding to Figure 1In the packaging structure design, power semiconductor devices adopt a single-sided heat dissipation packaging structure design. The power semiconductor device includes a substrate 10A, circuits 20A and multiple chips 30A carried on the same side of the substrate 10A, and a metal heat dissipation layer 101A attached to the other side of the substrate 10A. An insulating colloid 40A is covered on the side of the substrate 10A carrying the circuits 20A and chips 30A to encapsulate the circuits 20A and chips 30A. The metal heat dissipation layer 101A is usually made of copper, which takes into account both thermal conductivity and cost. However, the thermal conductivity of the insulating colloid 40A is much lower than that of the metal heat dissipation layer 101A. The heat generated by the chips 30A is mainly dissipated through the unidirectional heat dissipation path formed by the substrate 10A and the metal heat dissipation layer 101A. This single-sided heat dissipation packaging structure design, which mainly dissipates heat through a unidirectional heat dissipation path, is difficult to meet the heat dissipation performance requirements of power semiconductor devices with higher power density. Therefore, based on the requirement for higher heat dissipation performance, current power semiconductor devices tend to adopt... Figure 2 The double-sided heat dissipation packaging structure design is shown. Specifically, in Figure 2 In the double-sided heat dissipation packaging structure design shown, the power semiconductor device includes two substrates 10B and a circuit 20B and multiple chips 30B carried on the same side of one of the substrates 10B. The substrate 10B carrying the circuit 20B and the chips 30B is the lower substrate 11B, and the other substrate 10B is the upper substrate 12B. A metal pad 40B is placed on the upper surface of each chip 30B. Based on the corresponding thickness of the metal pad 40B, the upper surface of the metal pad 40B is set at the same height. Correspondingly, a metal heat dissipation layer 101B is attached to both the upper and lower surfaces of the upper substrate 12B and the lower surface of the lower substrate 11B. This allows each chip 30B to form a downward heat dissipation path not only through the lower substrate 11B and the metal heat dissipation layer 101B attached to its lower surface, but also an upward heat dissipation path through the metal pad, the upper substrate 12B, and the metal heat dissipation layers 101B attached to the upper and lower surfaces of the upper substrate 12B. This results in a higher heat dissipation capacity relative to the upper substrate 12B. Figure 1The packaging structure shown improves the heat dissipation performance of the power semiconductor device. However, by placing a metal pad 40B on the upper surface of the chip 30B and designing the upper surface of the metal pad 40B to be set at the same height based on the corresponding thickness of the metal pad 40B, on the one hand, the matching accuracy between the thicknesses of the various components is required to be extremely high, especially when the chip 30B uses different thickness specifications, the matching accuracy between the thicknesses of the various components is extremely demanding, resulting in a low packaging yield; on the other hand, based on the aforementioned accuracy requirements, while increasing the packaging difficulty and cost, additional thermal resistance layers are also formed between the metal pad 40B and the chip 30B, and between the metal pad 40B and the corresponding metal heat dissipation layer 101B of the upper substrate 12B, based on insulation and / or buffering design requirements. Therefore, Figure 2 The double-sided heat dissipation packaging structure design shown is relative to Figure 1 The packaging design shown increases costs significantly, but the actual improvement in heat dissipation performance of the power semiconductor device is not ideal. Utility Model Content

[0005] One objective of this invention is to provide a packaged power device, wherein the packaged power device, based on a packaged method, can form a bidirectional heat dissipation path to ensure the heat dissipation performance of the packaged power device.

[0006] Another objective of this invention is to provide a packaged power device, wherein the packaged power device, based on a packaged packaging method, can achieve greater heat dissipation performance at a lower cost compared to the traditional double-sided heat dissipation packaging structure design, and can adapt to the packaging of the packaged power device with higher power density while reducing costs.

[0007] Another objective of this invention is to provide a packaged power device, wherein the packaged power device, based on a packaged method, can achieve a significant improvement in heat dissipation performance at a lower cost compared to the traditional single-sided heat dissipation package structure design, and thus has important commercial value and significance.

[0008] Another objective of this invention is to provide a packaged power device, wherein the packaged power device is based on a packaged packaging method, which splits the target packaged circuit into two packaged circuits, and packages the two packaged circuits onto two substrates, and uses the two substrates as upper and lower substrates for sealing. At the same time, the sealing between the two substrates forms an electrical connection between the two packaged circuits to form the target packaged circuit, thereby realizing a packaging structure in which the target packaged circuit is packaged between the two substrates. In this way, based on the aforementioned packaged packaging method, a bidirectional heat dissipation path is formed to ensure the heat dissipation performance of the packaged power device.

[0009] Another objective of this invention is to provide a packaged power device, wherein the packaged power device includes an upper substrate, a lower substrate, a first metal line disposed on the lower surface of the upper substrate, a first chip soldered to the first metal line, a second metal line disposed on the upper surface of the lower substrate, and a second chip soldered to the second metal line, wherein the upper substrate and the lower substrate are packaged together in a misaligned state of the first chip and the second chip, and the first metal line and the second metal line are electrically connected based on the packaging of the upper substrate and the lower substrate, thereby encapsulating the target packaged circuit formed by connecting the first metal line, the second metal line, the first chip, and the second chip between the upper substrate and the lower substrate.

[0010] Another objective of this invention is to provide a packaged power device, wherein the upper substrate and the lower substrate are packaged together in a state where the first chip and the second chip are misaligned. That is, in the packaged power device, the first chip and the second chip are arranged in a misaligned manner. Therefore, the aforementioned packaged packaging method will not require additional substrate area of ​​the upper substrate and the lower substrate, nor will it require additional thickness of the packaged power device, thus adapting to the trend of miniaturization.

[0011] Another objective of this invention is to provide a packaged power device in which the first chip and the second chip are staggered. This arrangement ensures the upward heat dissipation area of ​​the first chip and the downward heat dissipation area of ​​the second chip while shortening the downward heat dissipation path of the first chip and the upward heat dissipation path of the second chip. This further improves heat dissipation efficiency compared to the traditional double-sided heat dissipation packaging structure design, thus achieving a greater improvement in heat dissipation performance at a lower cost compared to the traditional double-sided heat dissipation packaging structure design.

[0012] According to one aspect of the present invention, a split-type power device is provided, the split-type power device comprising:

[0013] An upper substrate and a lower substrate are provided. A first metal circuit is disposed on the lower surface of the upper substrate, a first chip is soldered to the first metal circuit, a second metal circuit is disposed on the upper surface of the lower substrate, and a second chip is soldered to the second metal circuit. The relative positional relationship between the first chip and the second chip satisfies the condition that the lower surface of the upper substrate and the upper surface of the lower substrate are opposite to each other. The upper substrate and the lower substrate are sealed together in the state where the lower surface of the upper substrate and the upper surface of the lower substrate are opposite to each other. The first metal circuit and the second metal circuit are electrically connected based on the sealing of the upper substrate and the lower substrate. In this way, a target package circuit formed by connecting the first metal circuit, the second metal circuit, the first chip, and the second chip is packaged between the upper substrate and the lower substrate.

[0014] In one embodiment, a first metal boss is provided at a corresponding position of the first metal line, and a second metal boss is provided at a corresponding position of the second metal line, wherein either the first metal boss and the opposite second metal boss are electrically connected by being soldered together based on the sealing of the upper substrate and the lower substrate.

[0015] In one embodiment, the packaged power device further includes a plurality of pins connected to the target package circuit and extending from between the upper substrate and the lower substrate.

[0016] In one embodiment, the pin has a positioning hole at one end and is pre-soldered to the second metal line of the lower substrate at the end with the positioning hole. The upper substrate has a positioning post at a position corresponding to the positioning hole, which matches the positioning hole. During the sealing process of the upper substrate and the lower substrate, the relative positional relationship between the upper substrate and the lower substrate can be defined based on the matching relationship between the positioning hole and the positioning post. In the sealed power device formed by sealing, the positioning post is inserted into the positioning hole.

[0017] In one embodiment, the encapsulated power device formed by sealing the upper substrate and the lower substrate further includes an colloid that is injected between the upper substrate and the lower substrate and then further cured.

[0018] In one embodiment, the upper substrate and the lower substrate are disposed of as ceramic substrates.

[0019] In one embodiment, the packaged power device further includes a first metal heat dissipation layer disposed on the upper surface of the upper substrate and a second metal heat dissipation layer disposed on the lower surface of the lower substrate.

[0020] In one embodiment, the packaged power device is a rectifier bridge circuit as the target packaged circuit.

[0021] In one embodiment, the first metal line includes a positive electrode patch, a negative electrode patch, and two AC electrodes disposed between the positive and negative electrode patches. The number of first chips is two, each first chip being soldered to one of the two AC electrodes and electrically connected to the negative electrode patch via wire bonding. These two first chips correspond to two diode chips directly connected to the negative output terminal of the rectifier bridge circuit. Similarly, the second metal line includes a positive electrode patch, a negative electrode patch, and two AC electrodes disposed between the positive and negative electrode patches. The number of second chips is two, each second chip being soldered to the positive electrode patch and electrically connected to the two AC electrodes via wire bonding. In the rectifier bridge circuit, the two second chips correspond to the two diode chips directly connected to the positive output terminal of the rectifier bridge circuit. Based on the encapsulation of the upper substrate and the lower substrate, the positive patch of the first metal line is electrically connected to the positive patch of the second metal line, the negative patch of the first metal line is electrically connected to the negative patch of the second metal line, and the two AC patches of the first metal line are respectively electrically connected to the two AC patches of the second metal line, thus forming the rectifier bridge circuit. The target package circuit formed by connecting the first metal line, the second metal line, the first chip, and the second chip is encapsulated between the upper substrate and the lower substrate.

[0022] The further objectives and advantages of this invention will become fully apparent from the following description and accompanying drawings. Attached Figure Description

[0023] Figure 1 This is a diagram of the packaging structure of an existing power semiconductor device designed with a single-sided heat dissipation packaging structure.

[0024] Figure 2 This is a diagram of the packaging structure of an existing power semiconductor device designed with a double-sided heat dissipation packaging structure.

[0025] Figure 3 This is a schematic diagram of the circuit connection of the rectifier bridge circuit.

[0026] Figure 4 This is a schematic diagram of the upper substrate of a sealed power device according to an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the lower substrate of the encapsulated power device according to the above embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram of the packaging principle of the encapsulated power device according to the above embodiments of the present invention.

[0029] Figure 7 This is a schematic diagram of the circuit connection principle of the upper substrate of the encapsulated power device according to the above embodiments of the present invention.

[0030] Figure 8 This is a schematic diagram of the circuit connection principle of the lower substrate of the encapsulated power device according to the above embodiment of the present invention. Detailed Implementation

[0031] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0032] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the elements can be multiple, and the term "a" should not be understood as a limitation on the number.

[0033] This utility model provides a packaged power device, wherein the packaged power device is based on a packaged packaging method, which splits the target packaged circuit into two packaged circuits, and packages the two packaged circuits onto two substrates, and uses the two substrates as upper and lower substrates for sealing. At the same time, the sealing between the two substrates forms an electrical connection between the two packaged circuits to form the target packaged circuit, and correspondingly realizes the packaged structure of the target packaged circuit packaged between the two substrates. In this way, based on the aforementioned packaged packaging method, a bidirectional heat dissipation path is formed to ensure the heat dissipation performance of the packaged power device.

[0034] Specifically, with Figure 3 The rectifier bridge circuit shown is an example of the target packaged circuit. Refer to the accompanying drawings of this utility model specification. Figures 4 to 6As shown, the structure of a packaged power device according to an embodiment of the present invention is illustrated. The packaged power device includes an upper substrate 10, a lower substrate 20, a first metal line 11 disposed on the lower surface of the upper substrate 10, a first chip 12 soldered to the first metal line 11, a second metal line 21 disposed on the upper surface of the lower substrate 20, and a second chip 22 soldered to the second metal line 21. The relative positional relationship between the first chip 12 and the second chip 22 satisfies the condition that the lower surface of the upper substrate 10 and the upper surface of the lower substrate 20 are opposite to each other. The upper substrate 10 and the lower substrate 20 are packaged together in the state where the lower surface of the upper substrate 10 and the upper surface of the lower substrate 20 are opposite to each other. The first metal line 11 and the second metal line 21 are electrically connected based on the packaging of the upper substrate 10 and the lower substrate 20, so as to package the target package circuit formed by connecting the first metal line 11, the second metal line 21, the first chip 12 and the second chip 22 between the upper substrate 10 and the lower substrate 20.

[0035] It is understood that the packaged power device is a device formed by encapsulating the target packaged circuit between the upper substrate 10 and the lower substrate 20. Therefore, based on the descriptions that "the relative positional relationship between the first chip 12 and the second chip 22 satisfies the state of misalignment between the lower surface of the upper substrate 10 and the upper surface of the lower substrate 20" and "the upper substrate 10 and the lower substrate 20 are packaged together in a state of mutual encapsulation between the lower surface of the upper substrate 10 and the upper surface of the lower substrate 20," it can be concluded that in the packaged power device, the first chip 12 and the second chip 22 are arranged in a misaligned manner. Thus, the aforementioned packaged method does not impose additional requirements on the substrate area of ​​the upper substrate 10 and the lower substrate 20, nor does it impose additional requirements on the thickness of the packaged power device, thereby adapting to the trend of miniaturization.

[0036] Furthermore, in the packaged power device, the first chip 12 is soldered to the first metal line 11, which is disposed on the lower surface of the upper substrate 10, and the second chip 22 is soldered to the second metal line 21, which is disposed on the upper surface of the lower substrate 20. Based on the staggered arrangement between the first chip 12 and the second chip 22, on the one hand, the upward heat dissipation area of ​​the first chip 12 and the downward heat dissipation area of ​​the second chip 22 can be guaranteed, and on the other hand, it is also beneficial to shorten the downward heat dissipation path of the first chip 12 and the upward heat dissipation path of the second chip 22. Therefore, the heat dissipation efficiency can be further improved compared with the traditional double-sided heat dissipation packaging structure design, thereby achieving a greater improvement in heat dissipation performance at a lower cost.

[0037] Furthermore, in this embodiment of the present invention, in order to ensure the sealing accuracy and stability of the upper substrate 10 and the lower substrate 20, and correspondingly ensure the consistency and stability of the sealed power device, the upper substrate 10 is provided with a first positioning wall 13 around the first metal line 11 on its lower surface, and the lower substrate 20 is provided with a second positioning wall 23 around the second metal line 21 on its upper surface. The first positioning wall 13 and the second positioning wall 23 have matching sealing surface (top surface) designs. For example, if the sealing surface of the first positioning wall 13 is designed as a stepped surface with an inner bottom and an outer high, the sealing surface of the second positioning wall 23 is designed as a matching stepped surface with an inner high and an outer low; or if the sealing surface of the first positioning wall 13 is designed as a convex surface, the sealing surface of the second positioning wall 23 is designed as a matching concave surface. By defining the sealing position based on the sealing cover of the first positioning wall 13 and the sealing cover of the second positioning wall 23, the relative positional relationship between the upper substrate 10 and the lower substrate 20 is defined, thereby ensuring the sealing accuracy and stability of the upper substrate 10 and the lower substrate 20.

[0038] Furthermore, in this embodiment of the present invention, in the sealed power device formed by the upper substrate 10 and the lower substrate 20, the sealing surface of the first positioning wall 13 and the sealing surface of the second positioning wall 23 are welded together, thereby ensuring the stability and sealing of the sealing structure between the upper substrate 10 and the lower substrate 20.

[0039] For example, in this embodiment of the present invention, when the upper substrate 10 and the lower substrate 20 are not yet sealed, at least one of the sealing surfaces of the first positioning wall 13 and the second positioning wall 23 is coated with solder, so that during the sealing process of the upper substrate 10 and the lower substrate 20, the sealing surfaces of the first positioning wall 13 and the second positioning wall 23 can be welded together by heating.

[0040] Specifically, in order to enable the first metal line 11 and the second metal line 21 to be electrically connected based on the sealing of the upper substrate 10 and the lower substrate 20, a first metal boss 111 is provided at a corresponding position of the first metal line 11, and a second metal boss 211 is provided at a corresponding position of the second metal line 21. Each of the first metal boss 111 and the corresponding second metal boss 211 is electrically connected by soldering based on the sealing of the upper substrate 10 and the lower substrate 20, and the stability of the sealing structure between the upper substrate 10 and the lower substrate 20 can be enhanced by the soldering connection between the first metal boss 111 and the corresponding second metal boss 211.

[0041] For example, in the unsealed state of the upper substrate 10 and the lower substrate 20, at least one of the first metal bosses 111 and the opposite second metal bosses 211 is coated with solder. This allows the first metal bosses 111 and the opposite second metal bosses 211 to be electrically connected by heating during the sealing process of the upper substrate 10 and the lower substrate 20, thereby realizing the electrical connection between the first metal line 11 and the second metal line 21.

[0042] It is worth mentioning that, based on the sealing positioning between the sealing cover of the first positioning wall 13 and the sealing cover of the second positioning wall 23, the distance between the first metal boss 111 and the opposite second metal boss 211 has good consistency, which helps to simplify the control of the amount of solder between the first metal boss 111 and the opposite second metal boss 211, and thus helps to ensure the yield of the packaged power device.

[0043] Furthermore, the packaged power device also includes a plurality of pins 30 connected to the target package circuit and extending from the upper substrate 10 and the lower substrate 20. To enhance the stability of the connection between the pins 30 and the target package circuit, and to reduce the impact of external forces acting on the pins 30 on the packaged power device, in this embodiment of the present invention, each pin 30 has a positioning hole 301 at one end, and the end with the positioning hole 301 is pre-soldered to the second metal line 21 of the lower substrate 20. A positioning post 14 corresponding to the positioning hole 301 is provided on the upper substrate 10 at a position corresponding to the positioning hole 301. During the sealing process of the upper substrate 10 and the lower substrate 20, the relative positional relationship between the upper substrate 10 and the lower substrate 20 can be defined based on the matching relationship between the positioning hole 301 and the positioning post 14, thereby further ensuring the sealing accuracy and stability of the upper substrate 10 and the lower substrate 20. In the sealed power device formed by sealing, the positioning post 14 is inserted into the positioning hole 301, and the stability of the connection relationship between the pin 30 and the target package circuit is enhanced based on this structural state. Correspondingly, the influence of the external force acting on the pin 30 on the sealed power device can be reduced, thereby ensuring the stability of the sealed power device during installation and use.

[0044] In particular, in this embodiment of the present invention, the sealed power device formed by sealing the upper substrate 10 and the lower substrate 20 further includes a colloid that is poured between the upper substrate 10 and the lower substrate 20 and then further cured, thereby forming a potting of the space between the upper substrate 10 and the lower substrate 20 to ensure the structural stability and heat dissipation performance of the sealed power device.

[0045] Furthermore, in this embodiment of the present invention, in order to ensure the heat dissipation performance of the upper substrate 10 and the lower substrate 20, the upper substrate 10 and the lower substrate 20 are disposed on ceramic substrates, including but not limited to oxide ceramics, nitride ceramics, carbide ceramics and boride ceramics.

[0046] In addition, to further improve the heat dissipation performance of the packaged power device, the packaged power device also includes a first metal heat dissipation layer 15 disposed on the upper surface of the upper substrate 10 and a second metal heat dissipation layer 24 disposed on the lower surface of the lower substrate 20, so as to further improve the heat dissipation performance of the packaged power device based on the arrangement of the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24.

[0047] It is worth mentioning that, in some embodiments of this utility model, the heat dissipation performance of the packaged power device can be further improved by increasing the specific surface area of ​​the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24. For example, by roughening the surface of the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24, and / or by forming metal pillars on the surface of the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24, the specific surface area of ​​the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24 can be increased.

[0048] It is understood that, in order to fully disclose the present invention, in this embodiment of the present invention, the target package circuit is corresponding to Figure 3 The rectifier bridge circuit shown, wherein the specific circuit structure of the target package circuit does not constitute a limitation of the present invention, and the packaged power device of the present invention can also be a target package circuit of other power electronic circuits.

[0049] Specifically, in this embodiment of the present invention, with Figure 3 The rectifier bridge circuit shown is the target packaged circuit, as described in the accompanying drawings of this utility model specification. Figure 7 and Figure 8 As shown, the correspondence between the first metal line 11, the second metal line 21, the first chip 12, the second chip 22, and the rectifier bridge circuit is further illustrated.

[0050] Corresponding to Figure 7 The first metal line 11 includes a positive electrode patch 111, a negative electrode patch 112, and two AC patches 113 arranged between the positive electrode patch 111 and the negative electrode patch 112. The number of the first chips 12 is two. The two first chips 12 are respectively soldered to the two AC patches 113 and are electrically connected to the negative electrode patch 112 by chip bonding wires. The two first chips 12 correspond to the two diode chips in the rectifier bridge circuit that are directly connected to the negative output terminal of the rectifier bridge circuit.

[0051] Corresponding to Figure 8 The second metal line 21 also includes a positive electrode patch 211, a negative electrode patch 212, and two AC patches 213 arranged between the positive electrode patch 211 and the negative electrode patch 212. The number of the second chips 22 is two. Both second chips 22 are soldered to the positive electrode patch 212 and electrically connected to the two AC patches 213 by chip bonding wires. The two second chips 22 correspond to the two diode chips directly connected to the positive output terminal of the rectifier bridge circuit.

[0052] Further, the positive electrode patch 111, the negative electrode patch 112, and the two AC patches 113 of the first metal line 11 are each provided with at least one first metal boss 111, and the positive electrode patch 211, the negative electrode patch 212, and the two AC patches 213 of the second metal line 21 are each provided with at least one second metal boss 211. Based on the electrical connection between the first metal boss 111 and its counterpart second metal boss 211, the positive electrode patch 111 of the first metal line 11 is electrically connected to the positive electrode patch 211 of the second metal line 21, the negative electrode patch 112 of the first metal line 11 is electrically connected to the negative electrode patch 212 of the second metal line 21, and the two AC patches 113 of the first metal line 11 are respectively electrically connected to the two AC patches 213 of the second metal line 21, thus forming a corresponding... Figure 3 The rectifier bridge circuit is used to encapsulate the target packaged circuit formed by connecting the first metal line 11, the second metal line 21, the first chip 12 and the second chip 22 between the upper substrate 10 and the lower substrate 20.

[0053] It is worth mentioning that, based on different ways of splitting the target packaged circuit and / or different layouts of the split-encapsulated circuits, even if the target packaged circuit is the same as the rectifier bridge circuit, the first metal line 11 and the second metal line 12 still have diverse structural forms and layouts, and this utility model does not limit them.

[0054] To further understand this utility model, corresponding to the foregoing description of the packaged power device, this utility model also provides a packaging method for the packaged power device, the packaging method comprising the following steps:

[0055] S1. The first metal line 11 is provided on the lower surface of the upper substrate 10 and the first positioning wall 13 is provided around the first metal line 11, and the second metal line 21 is provided on the upper surface of the lower substrate 20 and the second positioning wall 23 is provided around the second metal line 21, wherein the first metal boss 111 is provided at the corresponding position of the first metal line 11, and the second metal boss 211 is provided at the corresponding position of the second metal line 21;

[0056] S2. The first chip 12 is fixed to the first metal line 11 and electrically connected to the corresponding line of the first metal line 11 by chip bonding wire, and the second chip 22 is fixed to the second metal line 21 and electrically connected to the corresponding line of the second metal line 21 by chip bonding wire, wherein the relative positional relationship between the first chip 12 and the second chip 22 satisfies the state that the lower surface of the upper substrate 10 and the upper surface of the lower substrate 20 are opposite to each other, and the first chip 12 and the second chip 22 are misaligned relative to each other;

[0057] S3. Solder is applied to at least one of the mounting covers of the first positioning wall 13 and the second positioning wall 23, and solder is applied to at least one of the first metal bosses 111 and the opposite second metal bosses 211. The upper substrate 10 and the lower substrate 20 are sealed and heated so that the mounting covers of the first positioning wall 13 and the second positioning wall 23 are soldered together. The first metal bosses 111 and the opposite second metal bosses 211 are soldered together to realize the electrical connection between the first metal line 11 and the second metal line 21. Correspondingly, the target package circuit formed by the connection of the first metal line 11, the second metal line 21, the first chip 12 and the second chip 22 is packaged between the upper substrate 10 and the lower substrate 20.

[0058] S4. Inject colloid between the upper substrate 10 and the lower substrate 20 to expel the air between the upper substrate 10 and the lower substrate 20 and cure the colloid.

[0059] It is worth mentioning that, corresponding to the aforementioned packaged power device, step S1 preferably further includes the step of: providing the first metal heat dissipation layer 15 on the upper surface of the upper substrate 10 and providing the second metal heat dissipation layer 24 on the lower surface of the lower substrate 20. Optionally, it further includes the steps of: roughening the surfaces of the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24, and / or providing metal pillars on the surfaces of the first metal heat dissipation layer 15 and the second metal heat dissipation layer 24.

[0060] Specifically, corresponding to the packaged power device described above, step S1 preferably further includes the step of soldering the pin 30 to the second metal line 21 of the lower substrate 20.

[0061] Those skilled in the art should understand that, in the disclosure of this utility model, the terms "upper" and "lower" indicate the orientation or positional relationship when either of the two substrates of the packaged power device is the lower substrate, describing the relative positional relationship of the device or element referred to. They are only for the purpose of facilitating the description and understanding of the relative positional relationship of the device or element referred to, and do not indicate or imply that the device or element referred to must be placed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this utility model.

[0062] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are merely examples and do not limit the present invention. The purpose of the present invention has been fully and effectively achieved. The functions and structural principles of the present invention have been shown and explained in the embodiments. Without departing from the stated principles, the implementation of the present invention may have any variations or modifications.

Claims

1. A blocking power device, characterized by The power device comprises: an upper substrate, a lower substrate, a first metal line arranged on the lower surface of the upper substrate, a first chip fixedly soldered to the first metal line, a second metal line arranged on the upper surface of the lower substrate, and a second chip fixedly soldered to the second metal line, wherein the relative position relationship between the first chip and the second chip satisfies the misaligned relative position relationship when the lower surface of the upper substrate and the upper surface of the lower substrate are opposite to each other, the upper substrate and the lower substrate are sealed when the lower surface of the upper substrate and the upper surface of the lower substrate are opposite to each other, the first metal line and the second metal line are electrically connected based on the sealing of the upper substrate and the lower substrate, and thus the target packaging circuit formed by the first metal line, the second metal line, the first chip and the second chip is sealed and packaged between the upper substrate and the lower substrate.

2. The power device according to claim 1, wherein the corresponding position of the first metal line is provided with a first metal boss, and the position of the second metal line corresponding to the first metal boss is provided with a second metal boss, wherein any first metal boss and the second metal boss opposite to it are electrically connected by being fixedly soldered based on the sealing of the upper substrate and the lower substrate.

3. The power device according to claim 2, wherein the power device further comprises a plurality of pins connected to the target packaging circuit and drawn from between the upper substrate and the lower substrate.

4. The power device according to claim 3, wherein the pin is provided with a positioning hole at one end thereof, and is pre-soldered to the second metal line of the lower substrate at the end provided with the positioning hole, wherein the position of the upper substrate corresponding to the positioning hole is provided with a positioning column matched with the positioning hole, and the relative position relationship between the upper substrate and the lower substrate can be defined based on the matching relationship between the positioning hole and the positioning column during the sealing of the upper substrate and the lower substrate, and the structure state of the positioning column inserted into the positioning hole is formed in the sealed power device.

5. The power device according to claim 4, wherein the power device formed by the sealing of the upper substrate and the lower substrate further comprises a glue body further solidified after being filled between the upper substrate and the lower substrate.

6. The power device according to claim 5, wherein the upper substrate and the lower substrate are provided with ceramic substrates.

7. The power device according to any one of claims 2 to 6, wherein the power device further comprises a first metal heat dissipation layer arranged on the upper surface of the upper substrate, and a second metal heat dissipation layer arranged on the lower surface of the lower substrate.

8. The power device according to claim 7, wherein the surfaces of the first metal heat dissipation layer and the second metal heat dissipation layer are provided with metal columns.

9. The power device according to claim 7, wherein the power device takes a rectifier bridge circuit as the target packaging circuit. ​ 10. The power device of claim 9, wherein the first metal line includes a positive pad, a negative pad, and two AC pads arranged between the positive pad and the negative pad, wherein the first chips are two in number, the two first chips are each soldered to one of the two AC pads and are each electrically connected to the negative pad by a chip wire, and the two first chips correspond to two diode chips in the rectifier bridge circuit that are directly connected to a negative output terminal of the rectifier bridge circuit; the second metal line also includes a positive pad, a negative pad, and two AC pads arranged between the positive pad and the negative pad, wherein the second chips are two in number, the two second chips are each soldered to the positive pad and are each electrically connected to one of the two AC pads by a chip wire, and the two second chips correspond to two diode chips in the rectifier bridge circuit that are directly connected to a positive output terminal of the rectifier bridge circuit, wherein based on the sealing of the upper substrate and the lower substrate, the positive pad of the first metal line is electrically connected to the positive pad of the second metal line, the negative pad of the first metal line is electrically connected to the negative pad of the second metal line, and the two AC pads of the first metal line are respectively electrically connected to the two AC pads of the second metal line, so as to form the rectifier bridge circuit, thereby sealing the target package circuit formed by the first metal line, the second metal line, the first chips, and the second chips between the upper substrate and the lower substrate.

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