FPGA-based multi-channel acoustic signal processing system and electronic equipment

Abstract

The utility model relates to the technical field of acoustic signal acquisition, in particular to a multi-channel acoustic signal processing system based on an FPGA (Field Programmable Gate Array) and electronic equipment. The system comprises a signal reconstruction module, a signal processing module and a data communication module. The input end of the signal reconstruction module is connected with an external acoustic signal source, the output end of the signal reconstruction module is connected with the input end of the signal processing module, and the signal reconstruction module is used for performing signal amplification and analog-to-digital conversion on a sound source signal output by the acoustic signal source and outputting an obtained first digital signal to the signal processing module; the signal processing module comprises a filtering unit and a cache unit, the input end of the filtering unit is connected with the output end of the signal reconstruction module, and the output end of the filtering unit is connected with the input end of the cache unit; the output end of the cache unit is connected with the input end of the data communication module, and the output end of the data communication module is connected with an external PC end. According to the invention, the system can be optimized, so that the technical requirements of the signal processing system are met, and the high performance and reliability of the system are ensured.

Description

Technical Field

[0001] This application relates to the technical field of acoustic signal acquisition, and in particular to a multi-channel acoustic signal processing system and electronic device based on FPGA. Background Technology

[0002] Underwater acoustic signals refer to information propagated by sound waves in an underwater environment. This information can be voice, images, or data. Because electromagnetic waves attenuate very quickly in seawater, while sound waves travel long distances and attenuate less in water, underwater acoustic communication has become the primary method of underwater communication. Therefore, underwater acoustic signal processing is an extremely important technical field. It not only supports the basic needs of underwater communication but also drives the development and application of related technologies. The technical requirements of underwater acoustic signal processing systems include, but are not limited to, multi-channel operation and high precision. Therefore, how to optimize the system to meet the technical requirements of signal processing systems and ensure high performance and reliability is a pressing technical problem that needs to be solved. Utility Model Content

[0003] To overcome the shortcomings of existing technologies, this application provides a multi-channel acoustic signal processing system and electronic device based on FPGA. It adopts multi-channel independent acquisition of underwater acoustic signals and uses a high-precision ADC to capture weak signal changes, thereby improving the resolution and accuracy of the signal, meeting the technical requirements of the signal processing system, and ensuring the high performance and reliability of the system.

[0004] The technical solution adopted by this application to solve its technical problem is:

[0005] In a first aspect, this application provides a multi-channel acoustic signal processing system based on FPGA, the system comprising: a signal reconstruction module, a signal processing module, and a data communication module;

[0006] The signal reconstruction module has multiple input terminals connected to an external acoustic signal source and an output terminal connected to the input terminal of the signal processing module. It is used to amplify and convert the acoustic source signal output by the acoustic signal source into an analog-to-digital signal, and output the resulting first digital signal to the signal processing module in an orderly manner.

[0007] The signal processing module includes a filtering unit and a buffer unit. The input terminal of the filtering unit is connected to the output terminal of the signal reconstruction module, and the output terminal of the filtering unit is connected to the input terminal of the buffer unit. The filtering unit is used to perform bandpass sampling on the first digital signal to obtain a second digital signal, and output the second digital signal to the buffer unit.

[0008] The output of the buffer unit is connected to the input of the data communication module, and the output of the data communication module is connected to an external PC. If a setting command is obtained, the system's acquisition frequency and the number of working channels are adjusted based on the PC.

[0009] It is also used to send the second digital signal in the buffer unit to the PC through the data communication module if a collection command is obtained, so as to restore the second digital signal and complete the transmission of the underwater acoustic signal.

[0010] Optionally, the signal reconstruction module includes a signal amplification unit and an analog-to-digital conversion unit;

[0011] The input terminal of the signal amplification unit is connected to the acoustic signal source, and the output terminal of the signal amplification unit is connected to the input terminal of the analog-to-digital conversion unit. The signal amplification unit is used to amplify the sound source signal and output the amplified sound source signal to the analog-to-digital conversion unit.

[0012] The output of the analog-to-digital converter is connected to the input of the filter unit, and is used to convert the amplified sound source signal into the first digital signal through the analog-to-digital converter, and output the first digital signal to the filter unit.

[0013] Optionally, the signal amplification unit includes a signal amplifier and a filter;

[0014] The input terminal of the signal amplifier is connected to the acoustic signal source, and the output terminal of the signal amplifier is connected to the input terminal of the analog-to-digital conversion unit.

[0015] The filter is connected in series at the connection between the signal amplifier and the analog-to-digital converter unit, and is used to filter the amplified sound source signal before outputting it to the analog-to-digital converter unit.

[0016] Optionally, the analog-to-digital conversion unit includes an ADS8361 analog-to-digital conversion chip.

[0017] Optionally, the signal processing module includes a multi-channel pin FPGA, and the FPGA includes a CIC filter and a buffer unit;

[0018] The input terminal of the CIC filter is connected to the output terminal of the signal reconstruction module, and the output terminal of the CIC filter is connected to the input terminal of the buffer unit. It is used to perform bandpass sampling processing on the first digital signal to reduce the data rate of the first digital signal, thereby obtaining the second digital signal, and storing the second digital signal in the buffer unit.

[0019] The buffer unit is equipped with a data mode control signal, which is used to control the buffer unit to select the output raw data mode or demodulated data mode according to the number of channels currently used.

[0020] The output of the buffer unit is connected to the input of the data communication module, and is used to output the second digital signal to the data communication module according to the selected data mode.

[0021] Optionally, the FPGA used is a Xilinx Artix-7 FPGA.

[0022] Optionally, the data communication module includes an Ethernet chip;

[0023] The input terminal of the Ethernet chip is connected to the output terminal of the signal processing module, and the output terminal of the Ethernet chip is connected to the input terminal of the PC.

[0024] Optionally, the Ethernet chip used is the RTL8211E.

[0025] Optionally, the system may also include a power management module;

[0026] The input terminal of the power management module is connected to an external DC signal source. The power management module includes multiple output terminals, at least one of which is connected to the signal reconstruction module, the signal processing module, and the data communication module. It is used to convert the DC signal output by the DC signal source into the power supply signals required by the signal reconstruction module, the signal processing module, and the data communication module respectively, and then output them.

[0027] Secondly, this application provides an electronic device equipped with the aforementioned FPGA-based multi-channel acoustic signal processing system.

[0028] By adopting the above technical solution, this application first uses a signal reconstruction module to amplify the received sound source signal, amplifying the weak signal output by the acoustic signal source to achieve sufficient intensity for subsequent processing. Then, the signal reconstruction module performs digital-to-analog conversion on the amplified sound source signal to obtain a first digital signal, which is then transmitted to the signal processing module. The signal processing module uses an Artix-7 FPGA to control the timing of the ADC chip in the signal reconstruction module, enabling the ADC chip to convert the sound source signal into the first digital signal. The processed first digital signal is then bandpass sampled by the filtering unit in the signal processing module to obtain a second digital signal. All obtained digital signals are stored in a buffer unit. The digital signals stored in the buffer unit can be output to a PC via a data communication module. This application includes at least one of the following beneficial effects:

[0029] 1. This application uses an Artix-7 FPGA programmable logic FPGA to realize functions such as acoustic signal analysis, processing, system control, data acquisition, storage and transmission. The acquisition uses a 60-channel 16-bit ADS8361 analog-to-digital converter chip, which can be flexibly configured through SPI (Serial Peripheral Interface) control mode.

[0030] 2. The first digital signal obtained by conversion is bandpass sampled to reduce the data rate and ensure that the processed signal is free of aliasing and distortion. The second digital signal, after being processed by the filtering unit, is stored in the buffer unit. Multiple transmission modes are designed for data transmission, applying different data volumes according to different scenarios. When the number of channels is small, using raw data is more suitable because raw data usually does not require additional processing and can be transmitted directly. However, when the number of channels is large, using demodulated data is more efficient because demodulated data may be more suitable for transmission in a multi-channel environment, better utilizing the parallel transmission advantages brought by multiple channels.

[0031] 3. The power supply module used in this application provides separate power supplies for analog power, digital power, and different modules, reducing signal interference caused by power supply and ensuring the high performance and reliability of the system. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the first module of the FPGA-based multi-channel acoustic signal processing system provided in the embodiments of this application;

[0033] Figure 2 This is a schematic diagram of the second module of the FPGA-based multi-channel acoustic signal processing system provided in the embodiments of this application. Detailed Implementation

[0034] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0035] The following will clearly and completely describe the concept, specific structure, and resulting technical effects of this application in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this application can be combined interactively without contradicting each other.

[0036] Reference Figure 1 and Figure 2 ,, Figure 1 This is a schematic diagram of the first module of the FPGA-based multi-channel acoustic signal processing system provided in this application embodiment. Figure 2 This is a schematic diagram of the second module of the FPGA-based multi-channel acoustic signal processing system provided in this application embodiment. The system specifically includes the following modules, which are described in detail below:

[0037] The signal reconstruction module has multiple input terminals connected to an external acoustic signal source and an output terminal connected to the input terminal of the signal processing module. It is used to amplify and convert the acoustic source signal output by the acoustic signal source into an analog-to-digital signal, and output the resulting first digital signal to the signal processing module in an orderly manner.

[0038] Regarding the signal reconstruction module: refer to... Figure 2 The signal reconstruction module consists of a signal amplification unit and an analog-to-digital conversion unit. The signal amplification unit mainly consists of an operational amplifier and a filter circuit. The operational amplifier amplifies the weak signal collected from the acoustic signal source to make it strong enough for subsequent processing. The filter circuit uses a combination of resistors and capacitors to design various types of filters to filter out unwanted frequency components.

[0039] More specifically, the analog-to-digital conversion unit includes a 60-channel 16-bit ADS8361 chip. This chip has a data acquisition precision of 16 bits and an acquisition rate of up to 2 MSPS, which can convert the sound source signal (analog signal) after amplification and filtering by the aforementioned receiving section into a first digital signal. Multiple channels independently acquire external acoustic signal sources, and based on the aforementioned ADS8361 chip to ensure recognition accuracy, the processed signals are then sequentially input into the subsequent FPGA.

[0040] The number of ADS8361 chips operating in the analog-to-digital converter module is variable, controlled by the FPGA's internal signal AdcCs (Analog-to-Digital Converter Chip Select Signal). The signal width is 4 bits, and each route consists of 20 channels. When one bit of AdcCs is high, the ADC chip with the high level is selected as the working chip. The acquisition frequency is determined by a fixed frequency and a fixed time step frequency issued by the PC (the setting command below). Both of these parameters can be defined on the PC.

[0041] Furthermore, the signal processing module includes a filtering unit and a buffer unit. The input terminal of the filtering unit is connected to the output terminal of the signal reconstruction module, and the output terminal of the filtering unit is connected to the input terminal of the buffer unit. The filtering unit is used to perform bandpass sampling on the first digital signal to obtain a second digital signal, and output the second digital signal to the buffer unit.

[0042] The output of the buffer unit is connected to the input of the data communication module, and the output of the data communication module is connected to an external PC. If a setting command is obtained, the system's acquisition frequency and the number of working channels are adjusted based on the PC.

[0043] Regarding the signal processing module: The signal processing module uses an Artix-7 FPGA, which has abundant internal logic resources and can perform various logic transformations. During analog data acquisition, the timing of the control signals for the analog-to-digital conversion module needs to change, which can be provided by the FPGA to facilitate the aforementioned analog-to-digital conversion. However, due to the limited number of pin interfaces, the FPGA can only support a maximum of 60 channels. In this embodiment, if more than 60 channels are needed, the FPGA can be expanded using a JTAG (Joint Test Action Group Daisy Chain) daisy chain, with one FPGA chip acting as the master and the rest as slave chips, allowing for more flexible subsequent configuration.

[0044] The signal processing module includes a filtering unit and a buffer unit. The filtering unit includes a CIC filter (Cascade Integrator Comb), which is used to perform bandpass sampling on the converted first digital signal to reduce the data rate of the first digital signal and obtain the second digital signal, thereby ensuring that the processed signal is free of aliasing and distortion. Then, the processed second digital signal is stored in the buffer unit inside the FPGA (i.e., the buffer unit).

[0045] The theorem used for bandpass sampling of the first digital signal via a CIC filter is the bandpass sampling theorem, which describes how to determine a suitable sampling frequency to avoid aliasing when sampling a band-limited signal. This theorem is particularly applicable to processing signals located within a specific frequency band, where the signal's spectrum is limited to a lower limit frequency. and upper limit frequency In between, specifically:

[0046] For a band-limited signal, its sampling frequency The following conditions must be met:

[0047] ;

[0048] in, It is an integer that satisfies:

[0049] ;

[0050] Here This represents the floor function.

[0051] Among them, when the upper limit frequency It is bandwidth When it is an integer multiple of , that is, there exists an integer such that The minimum sampling frequency required at this time is:

[0052] ;

[0053] This is because, in this case, the signal's spectrum can perfectly adapt to the sampling frequency, thus avoiding aliasing.

[0054] like Not bandwidth multiples of integers, let ,in It is an integer, and The minimum sampling frequency is:

[0055] ;

[0056] In this case, due to It is not exactly an integer multiple of the bandwidth; the sampling frequency needs to be increased slightly to ensure that all frequency components are sampled correctly and to avoid aliasing.

[0057] On the other hand, this application sets multiple transmission modes for the buffer unit during data transmission. Specifically, the buffer unit is provided with a data mode control signal, which is used to control the buffer unit to select the output raw data mode or demodulated data mode according to the number of channels currently used.

[0058] The output of the buffer unit is connected to the input of the data communication module, and is used to output the second digital signal to the data communication module according to the selected data mode.

[0059] Specifically, the data mode control signal is an internal signal that changes the data format. It can switch between raw data and demodulated data, and different data volumes are applied in different scenarios. Generally speaking, when the number of channels is small, the raw data mode can be used, while when the number of channels is large, the demodulated data mode can be used. Among them, the data acquired by the ADC chip without being processed by the FPGA is the raw data (first digital signal), while the data that has been filtered, demodulated, and downsampled by the FPGA is the demodulated data (second digital signal).

[0060] Furthermore, the output of the buffer unit is connected to the input of the data communication module, and the output of the data communication module is connected to an external PC, which is used to adjust the acquisition frequency and the number of working channels of the system based on the PC if a setting command is obtained.

[0061] It is also used to send the second digital signal in the buffer unit to the PC through the data communication module if a collection command is obtained, so as to restore the second digital signal and complete the transmission of the underwater acoustic signal.

[0062] Regarding the data communication module: It uses the RTL8211E Ethernet chip, which supports three Ethernet speeds: 10M, 100M, and 1000M. The PC can send commands (setting commands) through the Ethernet chip to change the signal acquisition frequency and the number of working channels within the system. When a acquisition command is sent, the second digital signal in the FPGA's buffer unit can be packaged using the RGMII protocol (Reduced Gigabit Media Independent Interface), and the packaged data can be sent to the PC via the Ethernet chip. The second digital signal is then restored.

[0063] Furthermore, referring to Figure 1 The FPGA-based multi-channel acoustic signal processing system provided in this application also includes a power management module, specifically:

[0064] The input terminal of the power management module is connected to an external DC signal source. The power management module includes multiple output terminals, at least one of which is connected to the signal reconstruction module, the signal processing module, and the data communication module. It is used to convert the DC signal output by the DC signal source into the power supply signals required by the signal reconstruction module, the signal processing module, and the data communication module respectively, and then output them.

[0065] Specifically, an external DC signal source provides a 20V DC signal. The power management module includes voltage conversion modules for different modules, which convert the 20V DC power into voltages that allow each module device to operate normally. This separates the analog and digital power supplies, thereby reducing interference and ensuring the system's high performance and reliability.

[0066] By adopting the above technical solution, the system features stability, reliability, convenient configuration, and low power consumption, ensuring accurate serial transmission and storage of multi-channel data. Furthermore, this system can simultaneously acquire and transmit up to 60 channels of analog signals in real time, fully meeting the requirements of underwater acoustic acquisition systems.

[0067] Secondly, this application provides an electronic device equipped with the aforementioned FPGA-based multi-channel acoustic signal processing system.

[0068] The above is a detailed description of the preferred embodiments of this application. However, the invention of this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A multi-channel acoustic signal processing system based on FPGA, characterized in that, The system includes: a signal reconstruction module, a signal processing module, and a data communication module; The signal reconstruction module has multiple input terminals connected to an external acoustic signal source and an output terminal connected to the input terminal of the signal processing module. It is used to amplify and convert the acoustic source signal output by the acoustic signal source into an analog-to-digital signal, and output the resulting first digital signal to the signal processing module in an orderly manner. The signal processing module includes a filtering unit and a buffer unit. The input terminal of the filtering unit is connected to the output terminal of the signal reconstruction module, and the output terminal of the filtering unit is connected to the input terminal of the buffer unit. The filtering unit is used to perform bandpass sampling on the first digital signal to obtain a second digital signal, and output the second digital signal to the buffer unit. The output of the buffer unit is connected to the input of the data communication module, and the output of the data communication module is connected to an external PC. If a setting command is obtained, the system's acquisition frequency and the number of working channels are adjusted based on the PC. It is also used to send the second digital signal in the buffer unit to the PC through the data communication module if a collection command is obtained, so as to restore the second digital signal and complete the transmission of the underwater acoustic signal.

2. The FPGA-based multi-channel acoustic signal processing system according to claim 1, characterized in that, The signal reconstruction module includes a signal amplification unit and an analog-to-digital conversion unit; The input terminal of the signal amplification unit is connected to the acoustic signal source, and the output terminal of the signal amplification unit is connected to the input terminal of the analog-to-digital conversion unit. The signal amplification unit is used to amplify the sound source signal and output the amplified sound source signal to the analog-to-digital conversion unit. The output of the analog-to-digital converter is connected to the input of the filter unit, and is used to convert the amplified sound source signal into the first digital signal through the analog-to-digital converter, and output the first digital signal to the filter unit.

3. The FPGA-based multi-channel acoustic signal processing system according to claim 2, characterized in that, The signal amplification unit includes a signal amplifier and a filter; The input terminal of the signal amplifier is connected to the acoustic signal source, and the output terminal of the signal amplifier is connected to the input terminal of the analog-to-digital conversion unit. The filter is connected in series at the connection between the signal amplifier and the analog-to-digital converter unit, and is used to filter the amplified sound source signal before outputting it to the analog-to-digital converter unit.

4. The FPGA-based multi-channel acoustic signal processing system according to claim 2, characterized in that, The analog-to-digital conversion unit includes the ADS8361 analog-to-digital conversion chip.

5. The FPGA-based multi-channel acoustic signal processing system according to claim 1, characterized in that, The signal processing module includes a multi-channel pin FPGA, and the FPGA includes a CIC filter and a buffer unit; The input terminal of the CIC filter is connected to the output terminal of the signal reconstruction module, and the output terminal of the CIC filter is connected to the input terminal of the buffer unit. It is used to perform bandpass sampling processing on the first digital signal to reduce the data rate of the first digital signal, thereby obtaining the second digital signal, and storing the second digital signal in the buffer unit. The buffer unit is equipped with a data mode control signal, which is used to control the buffer unit to select the output raw data mode or demodulated data mode according to the number of channels currently used. The output of the buffer unit is connected to the input of the data communication module, and is used to output the second digital signal to the data communication module according to the selected data mode.

6. The FPGA-based multi-channel acoustic signal processing system according to claim 5, characterized in that, The FPGA used is an Artix-7 FPGA.

7. The FPGA-based multi-channel acoustic signal processing system according to claim 1, characterized in that, The data communication module includes an Ethernet chip; The input terminal of the Ethernet chip is connected to the output terminal of the signal processing module, and the output terminal of the Ethernet chip is connected to the input terminal of the PC.

8. The FPGA-based multi-channel acoustic signal processing system according to claim 7, characterized in that, The Ethernet chip used is model RTL8211E.

9. The FPGA-based multi-channel acoustic signal processing system according to claim 1, characterized in that, The system also includes a power management module; The input terminal of the power management module is connected to an external DC signal source. The power management module includes multiple output terminals, at least one of which is connected to the signal reconstruction module, the signal processing module, and the data communication module. It is used to convert the DC signal output by the DC signal source into the power supply signals required by the signal reconstruction module, the signal processing module, and the data communication module respectively, and then output them.

10. An electronic device, characterized in that, It is equipped with an FPGA-based multi-channel acoustic signal processing system as described in any one of claims 1-9.

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